Patent application number | Description | Published |
20090077133 | SYSTEM AND METHOD FOR EFFICIENT RULE UPDATES IN POLICY BASED DATA MANAGEMENT - A method, system, and computer program product is provided for efficient policy rule update in a data management system. A policy rule is stored along with the attributes of a data object when the application of the policy rule results in action taken on the data object. A stored policy rule, called an effective policy rule, is subsequently used to restrict the number of data objects examined when a policy rule is added, deleted, modified, or otherwise updated. | 03-19-2009 |
20090141619 | SYSTEM AND METHOD FOR ENABLING EFFICIENT SMALL WRITES TO WORM STORAGE - According to the present invention, there is provided a method of providing a WORM storage system, the method including a sector-append capability. The method includes receiving data to be written to a WORM storage system. In addition, the method includes identifying a target sector at which the data is to be written. Also, the method includes determining if the received data can be added to the target sector. Moreover, the method includes adding the received data to the target sector if it is determined that the received data can be added to the target sector. | 06-04-2009 |
20090210374 | METHODOLOGY AND COMPUTER PROGRAM PRODUCT FOR EFFECTING RULE EVALUATION IN POLICY BASED DATA MANAGEMENT - The invention relates to a system and method for providing efficient policy rule updates in policy-based data management. More particularly, the invention relates to a system and method for restraining the size of the set of data objects to be examined after a policy rule evaluation. | 08-20-2009 |
20090210375 | METHODOLOGY AND COMPUTER PROGRAM PRODUCT FOR EFFECTING RULE EVALUATION IN POLICY BASED DATA MANAGEMENT - The invention relates to a system and method for providing efficient policy rule updates in policy-based data management. More particularly, the invention relates to a system and method for restraining the size of the set of data objects to be examined after a policy rule evaluation. | 08-20-2009 |
20090210878 | SYSTEM AND METHOD FOR DATA MANAGEMENT JOB PLANNING AND SCHEDULING WITH FINISH TIME GUARANTEE - A method is disclosed for scheduling data management jobs on a computer system that uses a dual level scheduling method. Macro level scheduling using a chained timer schedules the data management job for execution in the future. Micro level scheduling using an algorithm controls the actual dispatch of the component requests of a data management job to minimize impact on foreground programs. | 08-20-2009 |
20100223665 | SYSTEM AND METHOD FOR PROVIDING A VIRTUAL BINDING FOR A WORM STORAGE SYSTEM ON REWRITABLE MEDIA - A virtual binding system ensures that the WORM logic for protecting data immutability cannot be circumvented, effectively guaranteeing WORM property of a WORM storage system composed of rewritable magnetic hard disks. To close the security hole between the rewritable media and the WORM logic, virtual binding securely authenticates the legitimacy of a WORM logic controller before granting data access on a WORM storage media. Furthermore, the system verifies the legitimacy of the WORM logic controller during data access. This approach virtually binds together the WORM logic controller and the WORM storage media even though the WORM logic controller and the WORM storage media may be physically separate. | 09-02-2010 |
20120096458 | Method and System for Synchronizing Fault-Tolerant Virtual Machines - Primary and secondary virtual machines each executing on a separate physical host and forming a fault-tolerant pair synchronize their execution with each other as closely as possible such that the secondary can take over execution of the primary with little or no disruption of service and no loss of data. To provide fast takeover, the execution latency between the two virtual machines is kept to a minimum by incrementally adjusting the CPU allocation to the primary virtual machine. The CPU allocation to the primary virtual machine decreases when the execution latency is large and increases when the execution latency is small. In order to maximize the performance of the primary virtual machine, the system seeks to maximize the CPU resource limit for the primary virtual machine for as long as possible while minimizing the execution latency. | 04-19-2012 |
Patent application number | Description | Published |
20090115470 | MEMORY RESET APPARATUS - A memory reset apparatus including a first inverse circuit, a logic circuit, and a plurality of second inverse circuits is provided. The first inverse circuit receives a control signal generated by a north bridge and generates a first signal, in which the control signal controls reset of a plurality of memories. The logic circuit performs a logic operation of the first signal and an indicating signal and generates a second signal, in which the indicating signal indicates each component of a computer system completely powered on. The plurality of second inverse circuits is respectively coupled between the logic circuit and the memories. The second inverse circuits inverse the second signal and respectively generate a plurality of reset signals to the memories, so as to reset the memories. | 05-07-2009 |
20090125731 | CORE VOLTAGE CONTROLLING APPARATUS - A core voltage controlling apparatus suitable for a center processing unit (CPU) is provided. The apparatus includes a level shifting unit, a time-delay unit and a logic unit. An input terminal of the level shifting unit receives and shifts a first voltage signal, and an output terminal generates a second voltage signal, in which the first voltage signal indicates a power-on stable state, and the second voltage signal indicates a magnitude of the core voltage. The time-delay unit delays the second voltage signal to generate a third voltage signal. The logic unit is coupled to the time-delay unit for performing a logic operation on the third voltage and a fourth voltage signal transmitted by a power supply, and generating a fifth voltage signal for controlling a core voltage generator whether to provide the core voltage to the CPU or not, in which the fourth voltage signal indicates a power state. | 05-14-2009 |
20090154088 | STORAGE DEVICE BACKPLANE AND IDENTIFICATION CIRCUIT - A storage device backplane and an identification circuit for identifying using situations of the storage device backplane are provided. The storage device backplane possesses a first connection interface and a second connection interface, for being used as a first backplane supporting a motherboard, or a second backplane cascaded to the first backplane, or a first backplane supporting a daughterboard of the motherboard. The first and second backplanes possess the same storage device backplane structure. If the storage device backplane is used as the first backplane, a first connection interface of the first backplane is coupled to the motherboard or the daughterboard thereof; if the storage device backplane is used as the second backplane, a first connection interface of the second backplane is coupled to a second connection interface of the first backplane. The identification circuit identifies using situations of the storage device backplane and display corresponding correct indicator number. | 06-18-2009 |
20100095138 | COMPUTER START-UP TIMING CONTROL DEVICE AND METHOD THEREOF - A computer start-up timing control device and a method thereof are provided for generating a power supply signal to enable a power supply unit (PSU) to provide power. The device includes a chipset, a delay circuit, and a logic gate. The delay circuit delays a standby power ready signal of the computer to generate a standby power delay signal. The chipset generates a power supply signal. The standby power delay signal enables the logic gate to transmit the power supply signal to the PSU via the logic gate. The PSU provides a power to make the computer enter a start-up procedure. The standby power delay signal delays the time for the chipset to send a power supply signal, so that a baseboard management controller (BMC) has enough time to complete initialization. Therefore, the chipset is prevented from accessing the BMC and obtaining erroneous information before the BMC finishes initialization. | 04-15-2010 |
Patent application number | Description | Published |
20110263513 | Pharmaceutical Being Used For Treating Cancer and Fibrosis Disease and the Composition and Uses Thereof - Provided is the composition of a peptide and its mutagenic version, or other derivatives with the same 3-D structure with activity to bind the extracellular domain of PDGFR-α, or -β, but does not dimerize by itself, wherein said peptide comprises the sequence shown as SEQ ID NO: 1, 2 or 3. Also provided is the composition of the nucleotide sequence encoding said peptide and its derivatives, and the usage of said peptide and derivatives of the peptide in preparation of medicine for the prevention and treatment of fibrosis diseases, such as liver, kidney, and lung fibrosis, primary cancer, and cancer metastasis, especially stomach cancer, liver cancer, breast cancer, and lung cancer. | 10-27-2011 |
20140156980 | SERVER SYSTEM AND AUTO-RESET METHOD OF THE SAME - A server system having an auto-reset mechanism is provided. The server system comprises a power control circuit, a power processing circuit, a CPLD and a control circuit. The power control circuit generates a control signal. The power processing circuit operates according to the control signal to receive a first power and generate a second power. The CPLD receives the second power and operates accordingly and generates a power reset signal when the CPLD finishes a update process. The control circuit controls the power control circuit to stop to generate the control signal to turn off the power processing circuit to further disable the CPLD in a certain time period according to the power reset signal and controls the power control circuit to activate the power processing circuit to further activate and reset the CPLD after the certain time period. | 06-05-2014 |
20150113187 | Server System - A server system includes a baseboard management controller and calculation modules. Each calculation module includes a system on chip, slave devices and a switch. The switch is connected with the baseboard management controller, the system on chip and the slave devices. The switch issues an address selection signal to select one of the slave devices to be connected with the switch. The switch switches the baseboard management controller and the system on chip to be connected with one of the slave devices by a control signal. | 04-23-2015 |