Lambrecht, US
Amoret Margaret Lambrecht, St. Charles, MO US
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20140210165 | Surface Sealing System - A method and apparatus comprising a sealing member, an integral structure associated with the sealing member, and an engagement section extending from the sealing member. The sealing member is configured to be attached to a surface of an object. The sealing member is consolidated with the integral structure. The engagement section is deformable and configured to engage a receiving structure in the object. | 07-31-2014 |
Bram Lambrecht, Mountain View, CA US
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20140338477 | FORCE TRANSMISSION MECHANISM FOR TELEOPERATED SURGICAL SYSTEM - A force transmission mechanism for a teleoperated surgical instrument may include a gear, a push/pull drive element, and a connection element. The push/pull drive element may be configured to transmit force to actuate an end effector of the surgical instrument and to rotate with a shaft of the surgical instrument when the shaft is rotated by the force transmission mechanism. The connection element may operatively couple the gear and the push/pull drive element. The connection element may be configured to convert rotational movement of the gear to a substantially linear movement of the push/pull drive element. The connection element may be configured to rotate with the push/pull drive element and relative to the gear. | 11-20-2014 |
Bram Gilbert Antoon Lambrecht, Berkeley, CA US
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20100023133 | Semi-actuated transfemoral prosthetic knee - A semi-actuated above knee prosthetic system, which is mostly passive in nature and includes a shank link coupled to an artificial foot, a knee mechanism connected to the shank link and a thigh link attached to an above-knee remaining lower limb of an amputee, is operable in either an actuated mode or an un-actuated mode controlled by a signal processor linked to various prosthetic mounted sensors. In the actuated mode, power is delivered to a torque generator connected to the knee mechanism to cause a forced movement between the thigh and shank links. In the un-actuated mode, a control circuit operates in a non-powered manner to allow operation of the knee mechanism with modulated resistance. Power is delivered through an electric motor connected to a battery source and employed to drive a hydraulic pump which is part of an overall hydraulic power unit including the torque generator. | 01-28-2010 |
Bram Gilbert Antoon Lambrecht, Sunnyvale, CA US
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20130150980 | Powered Lower Extremity Orthotic and Method of Operation - A powered lower extremity orthotic, including a shank link coupled to an artificial foot, a knee mechanism connected to the shank link and a thigh link, is controlled by based on signals from various orthotic mounted sensors such that the artificial foot follows a predetermined trajectory defined by at least one Cartesian coordinate. | 06-13-2013 |
20140275791 | Sealing Multiple Surgical Instruments - In accordance with aspects of the present invention, a door mechanism is provided. A door mechanism according to some embodiments of the present invention includes a door that includes a sealing part, an arm connected to the sealing part, and a pivot part connected to the arm, the door rotating around a pivot axis at the pivot part; and a lever, the lever engaging the door at the pivot part such that the lever opens the door when engaged but is not affected when the door is opened without the lever. | 09-18-2014 |
20140276464 | SEALING MULTIPLE SURGICAL INSTRUMENTS - A cannula seal is presented. The cannula seal includes a cross-slit seal that can include a side wall that includes folded sidewalls; slits that are formed by the folded sidewalls when the cross-slit seal is in a closed position; and a concave end surface at the slits. The cross-slit seal can include energizing ribs formed to close the seal. The instrument guide includes a pyramidal shaped seal that seals against doors when no instrument is inserted and seals against an instrument when the instrument is inserted. | 09-18-2014 |
20140276465 | Sealing Multiple Surgical Instruments - A cannula cap is disclosed. A cannula cap according to some embodiments of the invention includes an instrument guide attachment; a cannula attachment; and a seal captured between the instrument guide attachment and the cannula attachment. In some embodiments, a cannula cap can include a lid; a locking ring; a base; and a cannula seal captured between the lid and the base. | 09-18-2014 |
20140276946 | Sealing Multiple Surgical Instruments - In accordance with aspects of the present invention, an instrument guide is provided. An instrument guide according to some embodiments of the present invention includes a channel portion, the channel portion including a plurality of channels through which surgical instruments can be inserted; a lower part mechanically fixed to the channel portion, the lower part including doors to seal each of the channels; an upper part, the upper part mechanically attached to the lower part and including a funnel for guiding the instruments into the plurality of channels; and one or more seals fixed between the upper part and the lower part, the seal(s) having openings corresponding to the channels and sealing against the doors when the doors are closed and sealing against surgical instruments when surgical instruments are inserted into the channels. | 09-18-2014 |
20140276947 | Sealing Multiple Surgical Instruments - In accordance with aspects of the present invention, an instrument is provided. An instrument seal according to some embodiments includes a seal body that can be captured between an upper part and a lower part of an instrument guide; and openings in the seal body that align with channels on the instrument guide, wherein the seal body seals against doors in the lower part and an instrument shaft inserted through the openings. | 09-18-2014 |
Chris Lambrecht, Santa Barbara, CA US
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20140267549 | ENHANCED VIDEO INTERACTION FOR A USER INTERFACE OF A TELEPRESENCE NETWORK - A telepresence device may relay video, audio, and/or measurement data to a user operating a control device. A user interface may permit the user to quickly view and/or understand temporally and/or spatially disparate information. The telepresence device may pre-gather looped video of spatially disparate areas in an environment. A temporal control mechanism may start video playback at a desired point in a current or historical video segment. Notations may be associated with time spans in a video and recalled by capturing an image similar to a frame in the time span of the video. An area of interest may be selected and video containing the area of interest may be automatically found. Situational data may be recorded and used to recall video segments of interest. The telepresence device may synchronize video playback and movement. A series of videos may be recorded at predetermined time intervals to capture visually trending information. | 09-18-2014 |
Christopher Lambrecht, Santa Barbara, CA US
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20150296177 | ENHANCED VIDEO INTERACTION FOR A USER INTERFACE OF A TELEPRESENCE NETWORK - A telepresence device may relay video, audio, and/or measurement data to a user operating a control device. A user interface may permit the user to quickly view and/or understand temporally and/or spatially disparate information. The telepresence device may pre-gather looped video of spatially disparate areas in an environment. A temporal control mechanism may start video playback at a desired point in a current or historical video segment. Notations may be associated with time spans in a video and recalled by capturing an image similar to a frame in the time span of the video. An area of interest may be selected and video containing the area of interest may be automatically found. Situational data may be recorded and used to recall video segments of interest. The telepresence device may synchronize video playback and movement. A series of videos may be recorded at predetermined time intervals to capture visually trending information. | 10-15-2015 |
Craig Lambrecht, Rochester, NY US
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20120314248 | SYSTEM AND METHOD FOR MULTI-SITE CELLULAR MANUFACTURING WITH TRANSPORTATION DELAYS - A system and method is used to manage scheduling of a plurality of print jobs in a multi-site print shop environment. The multi-site environment includes a plurality of print shops each having resources and equipment to complete at least one type of print job. Also included is a multi-site scheduler configuration arranged to assign and schedule print jobs to one of a home shop and a non-home shop. The assigning and scheduling is based on a fastest completion time, wherein a completion time of a print job in a home shop is defined as the actual time taken to complete the print job and a completion time of a print job in a non-home shop is defined as the actual time taken to complete the print job and a transportation delay. | 12-13-2012 |
20140307087 | METHODS AND SYSTEMS FOR PREVENTING TRAFFIC ACCIDENTS - Methods and systems for preventing traffic accidents. Video can be captured from a camera integrated with a traffic light signal located at the intersection. The video can be processed to determine if an accident is likely to occur based on images contained in the vide and particular factors. Drivers of vehicles in the vicinity of the camera/traffic light can be alerted if it is determined that an accident is likely to occur, thereby allowing the drivers to take corrective action to prevent the crash from occurring. | 10-16-2014 |
Craig Charles Lambrecht, Rochester, NY US
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20130128302 | METHODS AND SYSTEMS FOR DETERMINING CAPACITY ALLOCATION AND JOB SIZE THRESHOLDS FOR PRINT JOBS HAVING HEAVY-TAILED DISTRIBUTIONS - A method of identifying a cell configuration for a print shop may include determining a print job size distribution for a plurality of print jobs. The method may include identifying one or more print device requirements associated with a cell in a print shop, identifying a plurality of available print devices associated with the print shop and determining, by a computing device, a plurality of different configurations of the available print devices that satisfy the one or more print device requirements. The method may include, for each configuration, determining a print job size threshold value, and determining, by the computing device, a processing time associated with processing the plurality of print jobs by a cell having the configuration and the determined print job size threshold value. The method may include selecting, by the computing device, the cell having the configuration associated with the smallest processing time. | 05-23-2013 |
20130128303 | METHODS AND SYSTEMS FOR DETERMINING SUSTAINABILITY METRICS IN A PRINT PRODUCTION ENVIRONMENT - A method of determining a print shop sustainability metric over a period of time may include, for each of a plurality of print devices in a print shop, determining a low-activity state sustainability metric value associated with the print device operating in one or more low-activity states over a period of time, determining a print shop low-activity state sustainability metric value associated with the print shop, and determining a processing state sustainability metric value associated with the print device operating in a processing state over the period of time, determining a print shop processing state sustainability metric value associated with the print shop, determining a print shop sustainability metric value and displaying one or more of the low-activity state sustainability metric values, the processing state sustainability metric values, the print shop sustainability metric value, the print shop processing state sustainability metric value and the print shop sustainability metric value. | 05-23-2013 |
20130131871 | METHODS AND SYSTEMS FOR DETERMINING HEATING AND AIR CONDITIONING DEMANDS ON A PRINT SHOP - A method of estimating heat emissions for a print shop may include determining a total heat generation value associated with a print shop over the period of time by summing a non-print production heat generation value associated with the print shop over the period of time and a print production heat generation value associated with the print shop over the period of time, determining, by a computing device, a net heat emission value associated with the print shop over the period of time by reducing the total heat generation value by a heat loss rate, and displaying one or more of the non-print production heat generation value, the print production heat generation value, the total heat generation value, and the net heat emission value. | 05-23-2013 |
Frank Lambrecht, Danville, CA US
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20160125929 | METHODS AND APPARATUS FOR SYNCHRONIZING COMMUNICATION WITH A MEMORY CONTROLLER - A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals. | 05-05-2016 |
Frank Lambrecht, San Jose, CA US
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20120166863 | Methods And Apparatus For Synchronizing Communication With A Memory Controller - A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals. | 06-28-2012 |
20130082394 | STUB MINIMIZATION FOR MULTI-DIE WIREBOND ASSEMBLIES WITH PARALLEL WINDOWS - A microelectronic package can include a substrate having first and second opposed surfaces and first and second apertures extending between the first and second surfaces, first and second microelectronic elements each having a surface facing the first surface of the substrate, a plurality of terminals exposed at the second surface in a central region thereof, and leads electrically connected between contacts of each microelectronic element and the terminals. The apertures can have first and second parallel axes extending in directions of the lengths of the respective apertures. The second surface can have a central region disposed between the first and second axes. Each microelectronic element can embody a greater number of active devices to provide memory storage array function than any other function. The terminals can be configured to carry all of the address signals transferred to the microelectronic package. | 04-04-2013 |
20130094310 | METHODS AND APPARATUS FOR SYNCHRONIZING COMMUNICATION WITH A MEMORY CONTROLLER - A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals. | 04-18-2013 |
20140233333 | METHODS AND APPARATUS FOR SYNCHRONIZING COMMUNICATION WITH A MEMORY CONTROLLER - A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory controller to phase align a local data-sampling signal with the incoming data. The memory controller samples the data signal with the data-sampling signal. The memory controller can perform maintenance operations to update the phase relationship between the phase-providing and data-sampling signals. | 08-21-2014 |
Frank Lambrecht, Mountainview, CA US
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20130082380 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS IN ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic package can include a microelectronic element having a face and a plurality of element contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The microelectronic element can include a plurality of stacked electrically interconnected semiconductor chips. The substrate can have contacts facing the element contacts of the microelectronic element and joined thereto. The terminals can include first terminals arranged at positions within first and second parallel grids. The first terminals of each grid can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations within the microelectronic element. The signal assignments of the first terminals in the first grid can be a mirror image of the signal assignments of the first terminals in the second grid. | 04-04-2013 |
20130082395 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS IN ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic package can include a microelectronic element having a face and a plurality of element contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with at least one external component. The substrate can have substrate contacts on the first surface facing the element contacts of the microelectronic element and joined thereto. The terminals can include first terminals arranged at positions within first and second parallel grids. The first terminals of each grid can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. The signal assignments of the first terminals in the first grid can be a mirror image of the signal assignments of the first terminals in the second grid. | 04-04-2013 |
Frank Lambrecht, Mountain View, CA US
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20090186584 | TECHNIQUE FOR LOW-POWER OPERATION OF A WIRELESS DEVICE - Embodiments of a circuit are described. In this circuit, a receiver includes at least one input node that receives one or more signals from one or more antenna elements. Note that a given signal from a given antenna element may have an associated fixed bandwidth and/or may include directional information corresponding to a region in a space. Moreover, the receiver includes a measurement circuit, coupled to at least the one input node, that determines whether a metric of the given signal exceeds a corresponding threshold. Additionally, control logic in the circuit, which is coupled to the measurement circuit, instructs a communication circuit in the circuit to exit a first power-consumption mode if the metric of at least one of the signals exceeds the corresponding threshold. | 07-23-2009 |
20100058100 | DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS - A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function. | 03-04-2010 |
20100073047 | Apparatus for Data Recovery in a Synchronous Chip-to-Chip System - An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device. | 03-25-2010 |
20100078809 | Semiconductor Module with Micro-Buffers - The semiconductor module includes a plurality of memory die on a first side of a substrate and a plurality of buffer die on a second side of the substrate. Each of the memory die is disposed opposite and electrically coupled to one of the buffer die. | 04-01-2010 |
20100240327 | ANTENNA ARRAY WITH FLEXIBLE INTERCONNECT FOR A MOBILE WIRELESS DEVICE - An antenna array can be mounted on a flexible substrate and connected by a flexible interconnect to an integrated circuit such as a radio frequency front end. The antenna array can be mounted in a device housing that includes radio frequency interference (RFI) shielding. The antenna array is aligned with and next to an area of the housing that is not shielded against RFI. | 09-23-2010 |
20110005090 | DISPLACEMENT SENSING USING A FLEXIBLE SUBSTRATE - Angular displacement of a flexible substrate is determined based on an electrical change of a mm-wave circuit associated with the flexible substrate. This electrical change may relate to, for example, one or more of a phase shift, an amplitude shift, a frequency shift, or a pulse shift. In some implementations the flexible substrate may include conductors on multiple layers whereby an angular displacement of the flexible substrate causes a relative displacement between conductors of different layers, thereby inducing the electrical change of the mm-wave circuit. | 01-13-2011 |
20110119425 | DETACHABLE INTERCONNECT FOR CONFIGURABLE WIDTH MEMORY SYSTEM - The disclosure relates to a detachable signalling interconnect apparatus that provides connectivity between two or more components of a memory system in conjunction with different modes of operation of the components. The memory system comprises: a first socket to receive a first memory module; a second socket to receive a second memory module; a detachable signal-interconnect; and a memory controller coupled to the detachable signal-interconnect and configured to define a first mode of operation and a second mode of operation, wherein in the first mode of operation the detachable signal-interconnect is to couple the memory-controller to the first memory module and in the second mode of operation the detachable signal-interconnect is to couple the memory controller to the first memory module and the second memory module. | 05-19-2011 |
20110255615 | Apparatus for Data Recovery in a Synchronous Chip-to-Chip System - An apparatus that reduces sampling errors for data communicated between devices uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device. | 10-20-2011 |
20120181704 | SEMICONDUCTOR MODULE WITH MICRO-BUFFERS - The semiconductor module includes a plurality of memory die on a first side of a substrate and a plurality of buffer die on a second side of the substrate. Each of the memory die is disposed opposite and electrically coupled to one of the buffer die. | 07-19-2012 |
20130082374 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS IN ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The terminals can include first terminals at positions within first and second parallel grids. The first terminals can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of signal assignments of the first terminals in the second grid. | 04-04-2013 |
20130082375 | STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A system or microelectronic assembly can include one or more microelectronic packages each having a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region. | 04-04-2013 |
20130082381 | STUB MINIMIZATION USING DUPLICATE SETS OF TERMINALS FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic element having a memory storage array has a front face facing away from a substrate of a microelectronic package, and is electrically connected with the substrate through conductive structure extending above the front face. First terminals are disposed at locations within first and second parallel grids of the package. The first terminals of each grid are configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid. | 04-04-2013 |
20130082389 | STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic package can include a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region. | 04-04-2013 |
20130082390 | STUB MINIMIZATION USING DUPLICATE SETS OF TERMINALS FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid. | 04-04-2013 |
20130082391 | STUB MINIMIZATION FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic assembly can include a circuit panel having first and second surfaces and panel contacts at each surface, and first and second microelectronic packages having terminals mounted to the panel contacts at the first and second surfaces, respectively. The circuit panel can electrically interconnect terminals of the first package with corresponding terminals of the second package. Each package can include a substrate having first and second surfaces, a microelectronic element, conductive structure extending above a front face of the microelectronic element, and parallel columns of terminals at the second surface. The terminals of each package can include first terminals in a central region of the respective second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location within the respective microelectronic element. Each central region can have a width within three and one-half times a minimum pitch between adjacent terminals. | 04-04-2013 |
20130082396 | STUB MINIMIZATION USING DUPLICATE SETS OF TERMINALS FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic element having a memory storage array has a front face facing away from a substrate of a microelectronic package, and is electrically connected with the substrate through conductive structure extending above the front face. First terminals are disposed at locations within first and second parallel grids of the package. The first terminals of each grid are configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid. | 04-04-2013 |
20130082397 | STUB MINIMIZATION FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic package can include a substrate and a microelectronic element having a rear face facing a first surface of the substrate, a front face, and a column of element contacts extending in a first direction. The microelectronic element can include stacked electrically interconnected semiconductor chips. Edges of the microelectronic element can define an axial plane extending in the first direction and a third direction normal to the rear face. The package can include columns of terminals extending in the first direction at a second surface of the substrate. The terminals can include first terminals exposed in a central region of the second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location. The central region may have a width not more than 3.5 times a minimum pitch between adjacent terminal columns. The axial plane can intersect the central region. | 04-04-2013 |
20130082398 | STUB MINIMIZATION FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic package can include a substrate and a microelectronic element having a rear face facing a first surface of the substrate, a front face, and a column of element contacts extending in a first direction. Edges of the microelectronic element can define an axial plane extending in the first direction and a third direction normal to the rear face. The package can include columns of terminals extending in the first direction at a second surface of the substrate. The terminals can include first terminals exposed in a central region of the second surface and configured to carry address information usable by circuitry within the package to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between any two adjacent columns of the terminals. The axial plane can intersect the central region. | 04-04-2013 |
20130083582 | STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic package can include a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region. | 04-04-2013 |
20130083583 | STUB MINIMIZATION FOR MULTI-DIE WIREBOND ASSEMBLIES WITH PARALLEL WINDOWS - A microelectronic package can include a substrate having first and second opposed surfaces and first and second apertures extending between the first and second surfaces, first and second microelectronic elements each having a surface facing the first surface of the substrate, a plurality of terminals exposed at the second surface in a central region thereof, and leads electrically connected between contacts of each microelectronic element and the terminals. The apertures can have first and second parallel axes extending in directions of the lengths of the respective apertures. The central region of the second surface can be disposed between the first and second axes. The terminals can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic elements. | 04-04-2013 |
20130127062 | MULTIPLE DIE FACE-DOWN STACKING FOR TWO OR MORE DIE - A microelectronic assembly can include a substrate having first and second surfaces each extending in first and second transverse directions, a peripheral edge extending in the second direction, first and second openings extending between the first and second surfaces, and a peripheral region of the second surface extending between the peripheral edge and one of the openings. The assembly can also include a first microelectronic element having a front surface facing the first surface, a rear surface opposite therefrom, and an edge extending between the front and rear surfaces. The assembly can also include a second microelectronic element having a front surface facing the rear surface of the first microelectronic element and projecting beyond the edge of the first microelectronic element. The assembly can also include a plurality of terminals exposed at the second surface, at least one of the terminals being disposed at least partially within the peripheral region. | 05-23-2013 |
20130286707 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS - A microelectronic structure has active elements defining a storage array, and address inputs for receipt of address information specifying locations within the storage array. The structure has a first surface and can have terminals exposed at the first surface. The terminals may include first terminals and the structure may be configured to transfer address information received at the first terminals to the address inputs. Each first terminal can have a signal assignment which includes one or more of the address inputs. The first terminals are disposed on first and second opposite sides of a theoretical plane normal to the first surface, wherein the signal assignments of the first terminals disposed on the first side are a mirror image of the signal assignments of the first terminals disposed on the second side of the theoretical plane. | 10-31-2013 |
20130313721 | Semiconductor Module with Micro-Buffers - The semiconductor module includes a plurality of memory die on a first side of a substrate and a plurality of buffer die on a second side of the substrate. Each of the memory die is disposed opposite and electrically coupled to one of the buffer die. | 11-28-2013 |
20140103535 | STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic package can include a substrate and a microelectronic element having a face and one or more columns of contacts thereon which face and are joined to corresponding contacts on a surface of the substrate. An axial plane may intersect the face along a line in the first direction and centered relative to the columns of element contacts. Columns of package terminals can extend in the first direction. First terminals in a central region of the second surface can be configured to carry address information usable to determine an addressable memory location within the microelectronic element. The central region may have a width not more than three and one-half times a minimum pitch between the columns of package terminals. The axial plane can intersect the central region. | 04-17-2014 |
20140167278 | STUB MINIMIZATION USING DUPLICATE SETS OF TERMINALS FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid. | 06-19-2014 |
20140167279 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS IN ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE - A microelectronic assembly can include a circuit panel having first and second panel contacts at respective first and second surfaces thereof, and first and second microelectronic packages each having terminals mounted to the respective panel contacts. Each package can include a microelectronic element having a face and contacts thereon, a substrate having first and second surfaces, and terminals on the second surface configured for connecting the package with an external component. The terminals can include first terminals at positions within first and second parallel grids. The first terminals can be configured to carry address information usable by circuitry within the package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic element. Signal assignments of the first terminals in the first grid can be a mirror image of signal assignments of the first terminals in the second grid. | 06-19-2014 |
20140185354 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS - A microelectronic structure has active elements defining a storage array, and address inputs for receipt of address information specifying locations within the storage array. The structure has a first surface and can have terminals exposed at the first surface. The terminals may include first terminals and the structure may be configured to transfer address information received at the first terminals to the address inputs. Each first terminal can have a signal assignment which includes one or more of the address inputs. The first terminals are disposed on first and second opposite sides of a theoretical plane normal to the first surface, wherein the signal assignments of the first terminals disposed on the first side are a mirror image of the signal assignments of the first terminals disposed on the second side of the theoretical plane. | 07-03-2014 |
20140185725 | DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS - A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A communication link couples the first and second components. Calibration logic provides for setting an operation value for a parameter of the communication channel, such as by executing an exhaustive calibration sequence at initialization of the link. A tracking circuit, including a monitoring function, tracks drift in the parameter by monitoring a feedback signal that has a characteristic that correlates with drift in the communication channel, and updates, or indicates the need for updating of, the operation value of the parameter in response to the monitoring function. | 07-03-2014 |
20140328015 | STUB MINIMIZATION FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS - A microelectronic assembly ( | 11-06-2014 |
20140328016 | STUB MINIMIZATION FOR MULTI-DIE WIREBOND ASSEMBLIES WITH PARALLEL WINDOWS - A microelectronic assembly | 11-06-2014 |
20150198971 | Stub minimization for multi-die wirebond assemblies with parallel windows - A microelectronic assembly | 07-16-2015 |
20150221617 | MULTIPLE DIE FACE-DOWN STACKING FOR TWO OR MORE DIE - A microelectronic assembly can include a substrate having first and second surfaces each extending in first and second transverse directions, a peripheral edge extending in the second direction, first and second openings extending between the first and second surfaces, and a peripheral region of the second surface extending between the peripheral edge and one of the openings. The assembly can also include a first microelectronic element having a front surface facing the first surface, a rear surface opposite therefrom, and an edge extending between the front and rear surfaces. The assembly can also include a second microelectronic element having a front surface facing the rear surface of the first microelectronic element and projecting beyond the edge of the first microelectronic element. The assembly can also include a plurality of terminals exposed at the second surface, at least one of the terminals being disposed at least partially within the peripheral region. | 08-06-2015 |
20150293557 | DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS - A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal. | 10-15-2015 |
20160093339 | STUB MINIMIZATION USING DUPLICATE SETS OF SIGNAL TERMINALS - A microelectronic structure has active elements defining a storage array, and address inputs for receipt of address information specifying locations within the storage array. The structure has a first surface and can have terminals exposed at the first surface. The terminals may include first terminals and the structure may be configured to transfer address information received at the first terminals to the address inputs. Each first terminal can have a signal assignment which includes one or more of the address inputs. The first terminals are disposed on first and second opposite sides of a theoretical plane normal to the first surface, wherein the signal assignments of the first terminals disposed on the first side are a mirror image of the signal assignments of the first terminals disposed on the second side of the theoretical plane. | 03-31-2016 |
Frank Peter Lambrecht, Danville, CA US
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20140176439 | COMPUTING INTERFACE SYSTEM - Computing interface systems and methods are disclosed. Some implementations include a first accelerometer attached to a first fastening article that is capable of holding the first accelerometer in place on a portion of a thumb of a user. Some implementations may also include a second accelerometer attached to a second fastening article that is capable of holding the second accelerometer in place on a portion of a wrist of a user. Some implementations may additionally or alternatively include magnetometers and/or gyroscopes attached to the first and second fastening articles. Some implementations may also include a processing device configured to receive measurements from the accelerometers, magnetometers, and/or gyroscopes and identify, based on the measurements, symbols associated with motions of a user's hand and/or the orientation of the hand. Some implementations may allow a user to control a cursor in a three dimensional virtual space and interact with objects in that space. | 06-26-2014 |
20140267024 | COMPUTING INTERFACE SYSTEM - Computing interface systems and methods are disclosed. Some implementations include a first accelerometer attached to a first fastening article that is capable of holding the first accelerometer in place on a portion of a thumb of a user. Some implementations may also include a second accelerometer attached to a second fastening article that is capable of holding the second accelerometer in place on a portion of a wrist of a user. Some implementations may additionally or alternatively include magnetometers and/or gyroscopes attached to the first and second fastening articles. Some implementations may also include a processing device configured to receive measurements from the accelerometers, magnetometers, and/or gyroscopes and identify, based on the measurements, symbols associated with motions of a user's hand and/or the orientation of the hand. Some implementations may allow a user to control a cursor in a three dimensional virtual space and interact with objects in that space. | 09-18-2014 |
Greg Lambrecht US
Patent application number | Description | Published |
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20080255476 | Methods and devices for treating obesity - Methods and devices for treating obesity are provided. The consumption of calorie dense, lipid rich, or fatty foods is discouraged through the modulation of a subjects gallbladder function or output. Disclosed are devices and methods for delivering devices within the gallbladder and associated ducts and vasculature; other methods involve implanting devices on or around the gallbladder and associated ducts and vasculature. Further treatments involve the use of energy, surgery, or chemicals to alter the function of the gallbladder and biliary system. | 10-16-2008 |
Lonny Lambrecht, Byron, MN US
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20080307184 | MEMORY CONTROLLER OPERATING IN A SYSTEM WITH A VARIABLE SYSTEM CLOCK - The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access. | 12-11-2008 |
Lonny J. Lambrecht, Byron, MN US
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20150347333 | INTERCOMPONENT DATA COMMUNICATION - A request to send a message from a first component, located on a first processor, to a second component, located on a second processor, is received. It is determined that the second processor can be communicated with via a first bidirectional communication path. It is determined that bandwidth is available on the first bidirectional communication path. It is determined that bandwidth is available on a second bidirectional communication path. In response to a determination that bandwidth is available on the second bidirectional communication path, a data path is created between the first component and the second bidirectional communication path and the request to send the message to the second component is granted. In response to a determination that bandwidth is not available on the first bidirectional communication path or on the second bidirectional communication path, the grant of the request to send the message to the second component is delayed. | 12-03-2015 |
20150347334 | INTERCOMPONENT DATA COMMUNICATION - A request to send a first message from a first component to a second component is received at an arbiter. The first component is located in a first time zone and the second component is located in a second time zone. The arbiter determines that the second component is located in the second time zone. It is determined that the second time zone can be communicated with via one or more communications channels in a first direction. It is determined whether bandwidth is available on the one or more communications channels in the first direction. If bandwidth is available on the one or more communications channels in the first direction, a data path between the first component and the one or more communications channels in the first direction is created and the request is granted. Otherwise, the grant of the request is delayed. | 12-03-2015 |
20150347340 | INTERCOMPONENT DATA COMMUNICATION - A request to send a message from a first component, located on a first processor, to a second component, located on a second processor, is received. It is determined that the second processor can be communicated with via a first bidirectional communication path. It is determined that bandwidth is available on the first bidirectional communication path. It is determined that bandwidth is available on a second bidirectional communication path. In response to a determination that bandwidth is available on the second bidirectional communication path, a data path is created between the first component and the second bidirectional communication path and the request to send the message to the second component is granted. In response to a determination that bandwidth is not available on the first bidirectional communication path or on the second bidirectional communication path, the grant of the request to send the message to the second component is delayed. | 12-03-2015 |
20150347343 | INTERCOMPONENT DATA COMMUNICATION - A request to send a first message from a first component to a second component is received at an arbiter. The first component is located in a first time zone and the second component is located in a second time zone. The arbiter determines that the second component is located in the second time zone. It is determined that the second time zone can be communicated with via one or more communications channels in a first direction. It is determined whether bandwidth is available on the one or more communications channels in the first direction. If bandwidth is available on the one or more communications channels in the first direction, a data path between the first component and the one or more communications channels in the first direction is created and the request is granted. Otherwise, the grant of the request is delayed. | 12-03-2015 |
Mark J. Lambrecht, Mequon, WI US
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20100011653 | STEERABLE FISHING LURE - A fishing lure that includes an adjustable head member statically coupleable in a first and second position, about an axis of rotation, to a body member. The body member has a vertical centerline plane. The adjustable head comprises a steering bill member projecting therefrom in a first direction. When the adjustable head member is in the first position, the first direction of the steering bill member is directed away from a first side of the centerline plane to steer the fishing lure, when moved through water, in a first steering direction. When the adjustable head member is in the second position, the first direction is directed away from a second side of the vertical centerline plane opposite the first side of the vertical centerline plane to steer the fishing lure, when moved through water, in a second steering direction. | 01-21-2010 |
Richard M. Lambrecht, Milwaukee, WI US
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20140261392 | Solar Collector - A solar collector apparatus includes a parabolic mirror configured to direct solar energy through a double convex lens and towards a linear set of secondary mirrors, each of the secondary mirrors positioned to direct the solar energy towards a solar collection target. The subsequent diversion achieved by the solar collector apparatus allows collection of solar energy several times denser than natural sunlight, and can be captured using a substantially compact system. | 09-18-2014 |