Patent application number | Description | Published |
20110065825 | Method To Minimize Molecular Weight Drop Of Poly(L-Lactide) Stent During Processing - A method to reduce or minimize the reduction in molecular weight of a stent during processing is disclosed. The stent has a scaffolding including a polymer formulation comprising PLLA and polymandelide. The polymandelide reduces the molecular weight drop during processing, particularly during sterilization. The stent scaffolding can further include one or more additional stabilizing agents that additionally reduce the molecular weight drop during processing. | 03-17-2011 |
20120239135 | STENTS INCLUDING POLY(L-LACTIDE) FORMULATIONS THAT MINIMIZE MOLECULAR WEIGHT DROP DURING PROCESSING - A stent scaffolding including a polymer formulation comprising PLLA and polymandelide is disclosed. The polymandelide reduces the molecular weight drop during processing, particularly during sterilization. The stent scaffolding can further include one or more additional stabilizing agents that additionally reduce the molecular weight drop during processing. | 09-20-2012 |
20120285123 | Methods of Stabilizing Molecular Weight of Polymer Stents After Sterilization - Methods of stabilizing the molecular weight of polymer stents scaffolds after E-beam sterilization are disclosed. The molecular weight of the polymer of the irradiated scaffolds is stabilized through exposure to gas containing oxygen. | 11-15-2012 |
20140012365 | STENTS INCLUDING POLY(L-LACTIDE) FORMULATIONS THAT MINIMIZE MOLECULAR WEIGHT DROP DURING PROCESSING - A stent scaffolding including a polymer formulation comprising PLLA and polymandelide is disclosed. The polymandelide reduces the molecular weight drop during processing, particularly during sterilization. The stent scaffolding can further include one or more additional stabilizing agents that additionally reduce the molecular weight drop during processing. | 01-09-2014 |
20150054202 | METHOD TO MINIMIZE MOLECULAR WEIGHT DROP OF POLY(L-LACTIDE) STENT DURING PROCESSING - A method to reduce or minimize the reduction in molecular weight of a stent during processing is disclosed. The stent has a scaffolding including a polymer formulation comprising PLLA and polymandelide. The polymandelide reduces the molecular weight drop during processing, particularly during sterilization. The stent scaffolding can further include one or more additional stabilizing agents that additionally reduce the molecular weight drop during processing. | 02-26-2015 |
20150128527 | METHODS OF STABILIZING MOLECULAR WEIGHT OF POLYMER STENTS AFTER STERILIZATION - Methods of stabilizing the molecular weight of polymer stents scaffolds after E-beam sterilization are disclosed. The molecular weight of the polymer of the irradiated scaffolds is stabilized through exposure to gas containing oxygen. | 05-14-2015 |
20150137428 | METHODS OF STABILIZING MOLECULAR WEIGHT OF POLYMER STENTS AFTER STERILIZATION - Methods of stabilizing the molecular weight of polymer stents scaffolds after E-beam sterilization are disclosed. The molecular weight of the polymer of the irradiated scaffolds is stabilized through exposure to gas containing oxygen. | 05-21-2015 |
Patent application number | Description | Published |
20130119476 | Integrated Circuit Including Gate Electrode Level Region Including Cross-Coupled Transistors Having Gate Contacts Located Over Inner Portion of Gate Electrode Level Region and Offset Gate Level Feature Line Ends - A semiconductor device includes a cross-coupled transistor configuration formed by first and second PMOS transistors defined over first and second p-type diffusion regions, and by first and second NMOS transistors defined over first and second n-type diffusion regions, with each diffusion region electrically connected to a common node. Gate electrodes of the PMOS and NMOS transistors are formed by conductive features which extend in only a first parallel direction. The first and second p-type diffusion regions are formed in a spaced apart manner, such that no single line of extent that extends perpendicular to the first parallel direction intersects both the first and second p-type diffusion regions. The first and second n-type diffusion regions are formed in a spaced apart manner, such that no single line of extent that extends perpendicular to the first parallel direction intersects both the first and second n-type diffusion regions. | 05-16-2013 |
20130126978 | CIRCUITS WITH LINEAR FINFET STRUCTURES - A first transistor has source and drain regions within a first diffusion fin. The first diffusion fin projects from a surface of a substrate. The first diffusion fin extends lengthwise in a first direction from a first end to a second end of the first diffusion fin. A second transistor has source and drain regions within a second diffusion fin. The second diffusion fin projects from the surface of the substrate. The second diffusion fin extends lengthwise in the first direction from a first end to a second end of the second diffusion fin. The second diffusion fin is positioned next to and spaced apart from the first diffusion fin. Either the first end or the second end of the second diffusion fin is positioned in the first direction between the first end and the second end of the first diffusion fin. | 05-23-2013 |
20130146988 | Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels With Shared Diffusion Regions on Opposite Sides of Two-Transistor-Forming Gate Level Feature - A semiconductor device includes conductive features within a gate electrode level region that are each fabricated from a respective originating rectangular-shaped layout feature having a centerline aligned parallel to a first direction. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along a second gate electrode track. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device. | 06-13-2013 |
20130193524 | Cross-Coupled Transistor Circuit Having Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track and Gate Node Connection Through Single Interconnect Layer - A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection formed by linear-shaped conductive structures. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned. | 08-01-2013 |
20130200463 | Cross-Coupled Transistor Circuit Defined on Two Gate Electrode Tracks - A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A first NMOS transistor is defined by a gate electrode extending along a second gate electrode track. A second PMOS transistor is defined by a gate electrode extending along the second gate electrode track. A second NMOS transistor is defined by a gate electrode extending along the first gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node. | 08-08-2013 |
20130200464 | Cross-Coupled Transistor Circuit Defined on Three Gate Electrode Tracks - A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A second PMOS transistor is defined by a gate electrode extending along a second gate electrode track. A first NMOS transistor is defined by a gate electrode extending along the second gate electrode track. A second NMOS transistor is defined by a gate electrode extending along a third gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node. | 08-08-2013 |
20130200465 | Cross-Coupled Transistor Circuit Defined Having Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track with At Least Two Non-Inner Positioned Gate Contacts - A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection that includes two conductive contacting structures at a location not over an inner non-diffusion region. | 08-08-2013 |
20130200469 | Cross-Coupled Transistor Circuit Defined on Three Gate Electrode Tracks With Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track - A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned. | 08-08-2013 |
20130207196 | Cross-Coupled Transistor Circuit Defined on Four Gate Electrode Tracks - A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A second PMOS transistor is defined by a gate electrode extending along a second gate electrode track. A first NMOS transistor is defined by a gate electrode extending along a third gate electrode track. A second NMOS transistor is defined by a gate electrode extending along a fourth gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node. | 08-15-2013 |
20130207197 | Cross-Coupled Transistor Circuit Including Offset Inner Gate Contacts - A first conductive gate level feature forms a gate electrode of a first transistor of a first transistor type. A second conductive gate level feature forms a gate electrode of a first transistor of a second transistor type. A third conductive gate level feature forms a gate electrode of a second transistor of the first transistor type. A fourth conductive gate level feature forms a gate electrode of a second transistor of the second transistor type. A first contact connects to the first conductive gate level feature over an inner non-diffusion region. The first and fourth conductive gate level features are electrically connected through the first contact. A second contact connects to the third conductive gate level feature over the inner non-diffusion region and is offset from the first contact. The third and second conductive gate level features are electrically connected through the second contact. | 08-15-2013 |
20130207198 | Cross-Coupled Transistor Circuit Having Diffusion Regions of Common Node on Opposing Sides of Same Gate Electrode Track - A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned. | 08-15-2013 |
20130207199 | Finfet Transistor Circuit - A first gate level feature forms gate electrodes of a first finfet transistor of a first transistor type and a first finfet transistor of a second transistor type. A second gate level feature forms a gate electrode of a second finfet transistor of the first transistor type. A third gate level feature forms a gate electrode of a second finfet transistor of the second transistor type. The gate electrodes of the second finfet transistors of the first and second transistor types are electrically connected to each other. The gate electrodes of the second finfet transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first finfet transistors of the first and second transistor types are positioned. | 08-15-2013 |
20130214361 | Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels With Gate Contact Position and Offset Specifications - A semiconductor device includes conductive features that are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along a second gate electrode track. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device. | 08-22-2013 |
20130254732 | Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect - A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating is a set of equally spaced virtual lines of the GPG that supports a common layout shape run length thereon. The layout for the chip level is partitioned into subgrating regions. Each subgrating region has any one of the defined subgratings allocated thereto. Layout shapes placed within a given subgrating region in the chip level are placed in accordance with the subgrating allocated to the given subgrating region. Non-standard layout shape spacings at subgrating region boundaries can be mitigated by layout shape stretching, layout shape insertion, and/or subresolution shape insertion, or can be allowed to exist in the final layout. | 09-26-2013 |
20130256898 | Optimizing Layout of Irregular Structures in Regular Layout Context - A plurality of regular wires are formed within a given chip level, each having a linear-shape with a length extending in a first direction and a width extending in a second direction perpendicular to the first direction. The plurality of regular wires are positioned according to a fixed pitch such that a distance as measured in the second direction between lengthwise centerlines of any two regular wires is an integer multiple of the fixed pitch. At least one irregular wire is formed within the given chip level and within a region bounded by the plurality of regular wires. Each irregular wire has a linear-shape with a length extending in the first direction and a width extending in the second direction. A distance as measured in the second direction between lengthwise centerlines of any irregular wire and any regular wire is not equal to an integer multiple of the fixed pitch. | 10-03-2013 |
20140197543 | Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect - A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating is a set of equally spaced virtual lines of the GPG that supports a common layout shape run length thereon. The layout for the chip level is partitioned into subgrating regions. Each subgrating region has any one of the defined subgratings allocated thereto. Layout shapes placed within a given subgrating region in the chip level are placed in accordance with the subgrating allocated to the given subgrating region. Non-standard layout shape spacings at subgrating region boundaries can be mitigated by layout shape stretching, layout shape insertion, and/or subresolution shape insertion, or can be allowed to exist in the final layout. | 07-17-2014 |
20140210015 | Integrated Circuit Within Semiconductor Chip Including Cross-Coupled Transistor Configuration - A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection that includes respective gate contacts and a conductive interconnect structure. | 07-31-2014 |
20140239408 | SEMICONDUCTOR CHIP INCLUDING REGION HAVING CROSS-COUPLED TRANSISTOR CONFIGURATION WITH OFFSET ELECTRICAL CONNECTION AREAS ON GATE ELECTRODE FORMING CONDUCTIVE STRUCTURES AND AT LEAST TWO DIFFERENT INNER EXTENSION DISTANCES OF GATE ELECTRODE FORMING CONDUCTIVE STRUC - A first linear-shaped conductive structure (LCS) forms a gate electrode (GE) of a first transistor of a first transistor type. A second LCS forms a GE of a first transistor of a second transistor type. A third LCS forms a GE of a second transistor of the first transistor type. A fourth LCS forms a GE of a second transistor of the second transistor type. Each of the first, second, third, and fourth LCS's has a respective electrical connection area. The electrical connection areas of the first and third LCS's are offset from each other. The GE of the first transistor of the first transistor type is electrically connected to the GE of the second transistor of the second transistor type. The GE of the second transistor of the first transistor type is electrically connected to the GE of the first transistor of the second transistor type. | 08-28-2014 |
20140291730 | Semiconductor Chip Including Digital Logic Circuit Including Linear-Shaped Conductive Structures Having Electrical Connection Areas Located Within Inner Region Between Transistors of Different Type and Associated Methods - A first linear-shaped conductive structure (LCS) forms a gate electrode (GE) of a first transistor of a first transistor type. A second LCS forms a GE of a first transistor of a second transistor type. A third LCS forms a GE of a fourth transistor of the first transistor type. A fourth LCS forms a GE of a fourth transistor of the second transistor type. Transistors of the first transistor type are collectively separated from transistors of the second transistor type by an inner region. Each of the first, second, third, and fourth LCS's has a respective electrical connection area. At least two of the electrical connection areas of the first, second, third, and fourth LCS's are located within the inner region. The first and fourth transistors of the first transistor type and the first and fourth transistors of the second transistor type form part of a cross-coupled transistor configuration. | 10-02-2014 |
20140367799 | Semiconductor Chip Including Digital Logic Circuit Including At Least Nine Linear-Shaped Conductive Structures Collectively Forming Gate Electrodes of At Least Six Transistors with Some Transistors Forming Cross-Coupled Transistor Configuration and Associated Methods - At least nine linear-shaped conductive structures (LCS's) are positioned in accordance with a first pitch. Five of the at least nine LCS's collectively form three transistors of a first transistor type and three transistors of a second transistor type. Transistors of the first transistor type are collectively separated from transistors of the second transistor type by an inner region. Two transistors of the first transistor type and two transistors of the second transistor type are cross-coupled transistors. Each of four LCS's corresponding to the cross-coupled transistors has a respective electrical connection area located within the inner region. The two LCS's corresponding to the two transistors of the first transistor type of the cross-coupled transistors have electrical connections areas that are not aligned with each other. The four LCS's corresponding to the cross-coupled transistors include at least two different inner extension distances beyond their respective electrical connection areas. | 12-18-2014 |
20150187769 | Semiconductor Chip Including Digital Logic Circuit Including At Least Six Transistors with Some Transistors Forming Cross-Coupled Transistor Configuration and Associated Methods - A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection that includes respective gate contacts and one or more conductive interconnect structures. | 07-02-2015 |
20160079159 | Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect - A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating is a set of equally spaced virtual lines of the GPG that supports a common layout shape run length thereon. The layout for the chip level is partitioned into subgrating regions. Each subgrating region has any one of the defined subgratings allocated thereto. Layout shapes placed within a given subgrating region in the chip level are placed in accordance with the subgrating allocated to the given subgrating region. Non-standard layout shape spacings at subgrating region boundaries can be mitigated by layout shape stretching, layout shape insertion, and/or subresolution shape insertion, or can be allowed to exist in the final layout. | 03-17-2016 |
20160079276 | Semiconductor Chip Including Integrated Circuit Having Cross-Coupled Transistor Configuration and Method for Manufacturing the Same - A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type. A third conductive structure forms a gate electrode of a second transistor of the second transistor type. A fourth conductive structure forms a gate electrode of a third transistor of the first transistor type. A fifth conductive structure forms a gate electrode of a third transistor of the second transistor type. A sixth conductive structure forms gate electrodes of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. The second and third transistors of the first transistor type and the second and third transistors of the second transistor type are electrically connected to form a cross-coupled transistor configuration. | 03-17-2016 |
Patent application number | Description | Published |
20100287178 | REFINING LOCATION ESTIMATES AND REVERSE GEOCODING BASED ON A USER PROFILE - The present invention pertains to enhancement or refinement of estimated locations based upon user-specific information. Upon user authorization, geographical information is extracted from a number of user-related sources, including the web browser history, search history, maps history, address book, e-mail archives and calendar entries. Such information is used to build a spatial index of specific physical locations for a geocoded result set. From this, heat maps identifying particular locations from the user-related sources are created for different periods of time. The heat maps may be used to refine an initial location estimate of the user. This may be done by determining whether one or more positions in a given heat map provide a more accurate position of the user than the initial estimate. If so, a best position is selected. This can be used to provide enhanced driving directions to the user. | 11-11-2010 |
20110227699 | PERSONALIZED LOCATION TAGS - Systems and methods are provided for creating and using personalized location information tags (geotags). Personalized geotags take the place of generic location information such as latitude/longitude coordinates or granular city/state information. Such geotags may be published to present to selected people, e.g., family and friends, a user's current location. Thus, the user's location may be shown as “Home” or “Gym,” providing user-specific information without having to list a street address or latitude/longitude coordinates. Personalized geotags may be inferred based upon historical location information of the user. Geotags may also be inferred based upon geotag selections from other users in a network. A matching engine may select an appropriate geotag given the current location of a user device or based upon historical location information associated with the user. | 09-22-2011 |
20160027306 | RIDE CHAINING - A system for determining a dispatch includes an input interface, a processor, and an output interface. The input interface is to receive a request for a first pickup including a first pickup location and a first destination. The processor is configured to determining a driver to dispatch to the first pickup location. The output interface is to provide a first pickup indication to the driver to go to the first pickup location. The input interface is further to receive a first pickup arrival indication indicating the driver arrived at the first pickup location. The output interface is further to provide a first destination indication indicating to the driver to go to the first destination. The input interface is further to receive a request for a second pickup including a second pickup location and a second destination. | 01-28-2016 |
Patent application number | Description | Published |
20150346429 | WAVEGUIDE MODE EXPANDER USING AMORPHOUS SILICON - A waveguide mode expander couples a smaller optical mode in a semiconductor waveguide to a larger optical mode in an optical fiber. The waveguide mode expander comprises a shoulder made of crystalline silicon and a ridge made of non-crystalline silicon (e.g., amorphous silicon). In some embodiments, the ridge of the waveguide mode expander has a plurality of stages, the plurality of stages have different widths and/or thicknesses at a given cross section. | 12-03-2015 |
20150346430 | WAVEGUIDE MODE EXPANDER HAVING AN AMORPHOUS-SILICON SHOULDER - A waveguide mode expander couples a smaller optical mode in a semiconductor waveguide to a larger optical mode in an optical fiber. The waveguide mode expander comprises a shoulder and a ridge. In some embodiments, the ridge of the waveguide mode expander has a plurality of stages, the plurality of stages having different widths at a given cross section. | 12-03-2015 |
20150364441 | MICRO-PILLAR ASSISTED SEMICONDUCTOR BONDING - Micro pillars are formed in silicon. The micro pillars are used in boding the silicon to hetero-material such as III-V material, ceramics, or metals. In bonding the silicon to the hetero-material, indium is used as a bonding material and attached to the hetero-material. The bonding material is heated and the silicon and the hetero-material are pressed together. As the silicon and the hetero-material are pressed together, the micro pillars puncture the bonding material. In some embodiments, pedestals are used in the silicon as hard stops to align the hetero-material with the silicon. | 12-17-2015 |
20160133496 | SEMICONDUCTOR BONDING WITH COMPLIANT RESIN AND UTILIZING HYDROGEN IMPLANTATION FOR TRANSFER-WAFER REMOVAL - A transfer substrate with a compliant resin is used to bond one or more chips to a target wafer. An implant region is formed in a transfer substrate. A portion of the transfer substrate is etched to form a riser. Compliant material is applied to the transfer substrate. A chip is secured to the compliant material, wherein the chip is secured to the compliant material above the riser. The chip is bonded to a target wafer while the chip is secured to the compliant material. The transfer substrate and compliant material are removed from the chip. The transfer substrate is opaque to UV light. | 05-12-2016 |
Patent application number | Description | Published |
20130274950 | SERVER REQUEST FOR DOWNLOADED INFORMATION FROM A VEHICLE-BASED MONITOR - A system for triggered request for downloaded information from a vehicle-based monitor comprises a transmitter, a receiver, and a processor. The processor is coupled to the transmitter and the receiver. The processor is configured to determine whether it is desired to receive one or more data from a vehicle-based monitor. In the event that it is desired to receive one or more data from the vehicle-based monitor, the processor is configured to provide an indication that it is desired to receive the one or more data from the vehicle-based monitor. The processor is configured to receive the one or more data. | 10-17-2013 |
20140094992 | TRIGGERING A SPECIALIZED DATA COLLECTION MODE - A system for triggering a specialized data collection mode of a vehicle event recorder comprises an input interface, a processor, and an output interface. The input interface is configured to receive a trigger indication from an external trigger source. The processor is configured to determine whether the trigger indication comprises an indication to enter into a specialized data collection mode and, in the event that the trigger indication comprises the indication to enter into the specialized data collection mode, to determine a vehicle event recorder associated with the trigger indication. The output interface is configured to provide a specialized data collection mode indication to enter the specialized data collection mode to the vehicle event recorder in the event that the trigger indication comprises the indication to enter into the specialized data collection mode. | 04-03-2014 |
20140195105 | SERVER DETERMINED BANDWIDTH SAVING IN TRANSMISSION OF EVENTS - A system for receiving a driving event comprises an interface and a processor. An interface is configured to receive a portion of data regarding a driving event. A processor is configured to determine whether more data regarding the driving event should be requested and, in the event that more data regarding the driving event should be requested, request more data regarding the driving event. | 07-10-2014 |
20140236382 | SERVER REQUEST FOR DOWNLOADED INFORMATION FROM A VEHICLE-BASED MONITOR - A system for triggered request for downloaded information from a vehicle-based monitor comprises a transmitter, a receiver, and a processor. The processor is coupled to the transmitter and the receiver. The processor is configured to determine whether it is desired to receive one or more data from a vehicle-based monitor. In the event that it is desired to receive one or more data from the vehicle-based monitor, the processor is configured to provide an indication that it is desired to receive the one or more data from the vehicle-based monitor. The processor is configured to receive the one or more data. | 08-21-2014 |
20150088335 | DYNAMIC UPLOADING PROTOCOL - A dynamic uploading protocol comprises an input interface configured to receive a manifest comprising a plurality of events which may be uploaded; wherein the manifest additionally comprises sensor information relating to each of the plurality of events. The system for a dynamic uploading protocol additionally comprises a processor configured to determine whether to upload additional information about each event, wherein determining whether to upload additional information about each event is based at least in part on the sensor information and contextual information. The system for a dynamic uploading protocol additionally comprises an output interface configured to request the additional information. The system for a dynamic uploading protocol additionally comprises a memory coupled to the processor and configured to provide the processor with instructions. | 03-26-2015 |
20150175168 | AUTONOMOUS DRIVING COMPARISON AND EVALUATION - A system for autonomous driving comparison and evaluation comprises an input interface and a processor. The input interface is configured to receive trip information generated during a driver controlled trip and receive information from an autonomous driving system related to actions that the autonomous driving system would have taken had it been in control during the trip. The processor is configured to compare a trip factor of the driver controlled trip with a simulated trip factor that would have occurred had the autonomous driving system been in control. | 06-25-2015 |
20150183372 | MANAGING THE CAMERA ACQUIRING INTERIOR DATA - A system for managing a camera is comprises an input interface configured to detect a change in state; a processor configured to block transfer of data from an inward facing video camera; and an output interface configured to indicate that transfer of data is blocked. | 07-02-2015 |
20150287248 | SERVER DETERMINED BANDWIDTH SAVING IN TRANSMISSION OF EVENTS - A system for receiving a driving event comprises an interface and a processor. An interface is configured to receive a portion of data regarding a driving event. A processor is configured to determine whether more data regarding the driving event should be requested and, in the event that more data regarding the driving event should be requested, request more data regarding the driving event. | 10-08-2015 |
20150310676 | DYNAMIC UPLOADING PROTOCOL - A dynamic uploading protocol comprises an input interface configured to receive a manifest comprising a plurality of events which may be uploaded; wherein the manifest additionally comprises sensor information relating to each of the plurality of events. The system for a dynamic uploading protocol additionally comprises a processor configured to determine whether to upload additional information about each event, wherein determining whether to upload additional information about each event is based at least in part on the sensor information and contextual information. The system for a dynamic uploading protocol additionally comprises an output interface configured to request the additional information. The system for a dynamic uploading protocol additionally comprises a memory coupled to the processor and configured to provide the processor with instructions. | 10-29-2015 |
20160096531 | AUTOMATIC ENGAGEMENT OF A DRIVER ASSISTANCE SYSTEM - A system for automatic engagement of a driver assistance system comprises an input interface, a processor, and an output interface. The input interface is configured to receive data associated with one or more events. The processor is configured to evaluate the risk associated with the data and to determine that the risk indicates a state change in a driver assistance system is appropriate. The output interface is configured to provide an indication that the state change in the driver assistance system is appropriate. | 04-07-2016 |
20160098868 | TRIGGERING A SPECIALIZED DATA COLLECTION MODE - A system for triggering a specialized data collection mode of a vehicle event recorder comprises an input interface, a processor, and an output interface. The input interface is configured to receive a trigger indication from an external trigger source. The processor is configured to determine whether the trigger indication comprises an indication to enter into a specialized data collection mode and, in the event that the trigger indication comprises the indication to enter into the specialized data collection mode, to determine a vehicle event recorder associated with the trigger indication. The output interface is configured to provide a specialized data collection mode indication to enter the specialized data collection mode to the vehicle event recorder in the event that the trigger indication comprises the indication to enter into the specialized data collection mode. | 04-07-2016 |
20160109246 | DELETING UNNECESSARY MAP DATA - A system for deleting map data comprises an interface and a processor. The interface is configured to determine a location associated with a device. The processor is configured to determine one or more map bundles to delete based at least in part on the location and delete the one or more map bundles. | 04-21-2016 |
Patent application number | Description | Published |
20090176477 | SYSTEM AND METHOD FOR BENCHMARKING LOCATION DETERMINING SYSTEMS - Systems, methods, and software are described for benchmarking the location determination capabilities of a wireless communications network. A mobile communications device is configured to receive data identifying a reference location for the device. A communications network, communicatively coupled with the mobile communications device, calculates a computed location for the device using an alternative location determination technique. The reference location and computed location may be determined for any number of additional devices, as well. The accuracy and reliability of a system may then be assessed by comparing one or more computed locations with associated reference locations. The latency attributable to the calculation of one or more computed locations may also be determined. | 07-09-2009 |
20110028122 | SYSTEM AND METHOD FOR BENCHMARKING LOCATION DETERMINING SYSTEMS - Systems, methods, and software are described for benchmarking the location determination capabilities of a wireless communications network. A mobile communications device is configured to receive data identifying a reference location for the device. A communications network, communicatively coupled with the mobile communications device, calculates a computed location for the device using an alternative location determination technique. The reference location and computed location may be determined for any number of additional devices, as well. The accuracy and reliability of a system may then be assessed by comparing one or more computed locations with associated reference locations. The latency attributable to the calculation of one or more computed locations may also be determined. | 02-03-2011 |
20120122421 | SYSTEM AND METHOD FOR REDUCING LATENCY IN A WIRELESS LOCATION SYSTEM - A system and method for providing a location of a mobile device in a network. The method includes: receiving a location request; determining the location of the mobile device responsive to the location request; holding the determined location of the mobile device until a permission to send the determined location is received; receiving the permission to send the determined location; and transmitting the determined location of the mobile device responsive to the received permission. | 05-17-2012 |
20120164992 | SYSTEM AND METHOD FOR INITIATING AUXILIARY FUNCTIONS IN A TELECOMMUNICATION NETWORK - A method for initiating a service including initiating a communication to a destination according to an address of the destination; detecting the address during initiating of the communication; determining whether the detected address is associated with a trigger function; and triggering a request for the service when the detected address is associated with a trigger function. The request for the service is separate from the communication. | 06-28-2012 |
Patent application number | Description | Published |
20090221404 | INTERFACING PORTABLE MEDIA DEVICES AND SPORTS EQUIPMENT - Circuits, methods, and apparatus that allow sports or other equipment, such as gym or other cardio equipment, to write data to a media player. Examples further provide the uploading of this data to a computer and third-party website. To monitor progress, the third-party website can be used to track workout data over time. The third party-website can also collect data from other users, which is particularly useful for providing a competitive environment. This data can then be graphically displayed in various ways to provide encouragement. | 09-03-2009 |
20120028761 | INTERFACING PORTABLE MEDIA DEVICES AND SPORTS EQUIPMENT - Circuits, methods, and apparatus that allow sports or other equipment, such as gym or other cardio equipment, to write data to a media player. Examples further provide the uploading of this data to a computer and third-party website. To monitor progress, the third-party website can be used to track workout data over time. The third party-website can also collect data from other users, which is particularly useful for providing a competitive environment. This data can then be graphically displayed in various ways to provide encouragement. | 02-02-2012 |
20130173746 | INTERFACING PORTABLE MEDIA DEVICES AND SPORTS EQUIPMENT - Circuits, methods, and apparatus allow sports or other equipment, such as gym or other cardio equipment, to write data to a media player. Examples further provide the uploading of this data to a computer and third-party website. To monitor progress, the third-party website can be used to track workout data over time. The third party-website can also collect data from other users, which is particularly useful for providing a competitive environment. This data can then be graphically displayed in various ways to provide encouragement. | 07-04-2013 |
Patent application number | Description | Published |
20110005267 | AUTOMOTIVE ADSORPTION HEAT PUMP - An adsorber unit has an outer shell, a plurality of internal tubes extending through the shell for carrying heat transfer fluid, each tube having outwardly projecting fins along its entire length, and a solid adsorbent material in the shell surrounding the tubes such that the fins project into the adsorbent material, the fins being of a material (e.g., metal) of higher thermal conductivity than the adsorbent material. Metal wool loosely packed inside the tubes, or internal radial fins swaged into the tubes, increase internal surface area thereby enhancing convective heat transfer. Metal wool loosely packed between the external fins, or fine wire metal coils lightly squeezed between the external fins, further increase external surface area of the heat exchanger in contact with the adsorbent thereby enhancing contact heat transfer. Performance is enhanced because the external fins and wool or wire coils transport heat more efficiently to all regions of the adsorbent, and permit less non-adsorbent heat exchanger material (e.g., metal) to be used for a given amount of adsorbent. Two or more such units are used in an adsorption heat pump. This design utilizes existing components (e.g., shell-&-tube heat exchanger, internally and externally finned tubing, and metal wool or wire coils) in a novel manner heretofore untried. In one exemplary embodiment, automobile air conditioning, exhaust heat is used to power such an air conditioner. The significant additional power used by the mechanical compressor of an automobile (12%-17% during commuting for subcompact to midsize cars) can be nearly eliminated by powering the air conditioner with otherwise wasted exhaust heat. The adsorbent is heated and cooled by light oil (called Heat Transfer Fluid, HTF) which in turn is heated and cooled by exhaust and fresh air. Such indirect heating and cooling achieves the required efficiency, and allows using phase change material (e.g., wax) to store and therefore fully utilize exhaust heat. A refrigerant reservoir is included which provides immediate cooling after start-up of a cold engine, while the exhaust system and heat pump are still heating up in order to start pumping refrigerant. Eliminating the mechanical compressor increases fuel mileage by 14-18% for midsize, compact, MS and subcompact cars, or 4.6-6.0% annually, given a four-month cooling season. | 01-13-2011 |
Patent application number | Description | Published |
20090299302 | DEVICES AND METHODS FOR PROTECTING A USER FROM A SHARP TIP OF A MEDICAL NEEDLE - There are disclosed devices and methods for protecting a user from a sharp tip of a medical needle. In an embodiment, a device includes a central body portion, a medical needle having a sharp tip, a pair of wings in attachment to the central body portion, and a mechanical fastener disposed on at least one of the wings, the mechanical fastener configured to selectively attach the wings together with the medical needle positioned between the wings so as to protect a user from the sharp tip of the medical needle. In another embodiment, a method includes withdrawing a sharp tip of a medical needle from a patient, closing a pair of wings with the medical needle positioned between the wings, and fastening the wings together with the medical needle positioned between the wings so as to protect a user from the sharp tip of the medical needle. | 12-03-2009 |
20130138075 | VARIABLE FLOW CONTROL DEVICE, SYSTEM AND METHOD - A device, system and method are provided for controlling the rate of infusion of fluids during infusion therapy using non-electric infusion devices. Rotation of a flow regulator dial causes an orifice connected to the inlet to modify its position relative to a particular one or more orifices or groove portions, the characteristics of which provide a certain flow rate characteristic. The regulator allows for the infusion pump to infuse at a rate that may be varied during use by the user. | 05-30-2013 |
20130296804 | DEVICES AND METHODS FOR PROTECTING A USER FROM A SHARP TIP OF A MEDICAL NEEDLE - There are disclosed devices and methods for protecting a user from a sharp tip of a medical needle. In an embodiment, a device includes a central body portion, a medical needle having a sharp tip, a pair of wings in attachment to the central body portion, and a mechanical fastener disposed on at least one of the wings, the mechanical fastener configured to selectively attach the wings together with the medical needle positioned between the wings so as to protect a user from the sharp tip of the medical needle. In another embodiment, a method includes withdrawing a sharp tip of a medical needle from a patient, closing a pair of wings with the medical needle positioned between the wings, and fastening the wings together with the medical needle positioned between the wings so as to protect a user from the sharp tip of the medical needle. | 11-07-2013 |
20130296827 | DEVICES AND METHODS FOR PROTECTING A USER FROM A SHARP TIP OF A MEDICAL NEEDLE - There are disclosed devices and methods for protecting a user from a sharp tip of a medical needle. In an embodiment, a device includes a central body portion, a medical needle having a sharp tip, a pair of wings in attachment to the central body portion, and a mechanical fastener disposed on at least one of the wings, the mechanical fastener configured to selectively attach the wings together with the medical needle positioned between the wings so as to protect a user from the sharp tip of the medical needle. In another embodiment, a method includes withdrawing a sharp tip of a medical needle from a patient, closing a pair of wings with the medical needle positioned between the wings, and fastening the wings together with the medical needle positioned between the wings so as to protect a user from the sharp tip of the medical needle. | 11-07-2013 |
20140074050 | SHARPS PROTECTOR DEVICE FOR PROTECTING A USER FROM A SHARP TIP OF A MEDICAL NEEDLE - A device for protecting a user from a sharp tip of a medical needle includes a central body portion, a medical needle having a sharp tip, a pair of wings in attachment to the central body portion, and a mechanical fastener disposed on at least one of the wings. The mechanical fastener is configured to selectively attach the wings together with the medical needle positioned between the wings so as to protect a user from the sharp tip of the medical needle. In another embodiment, a sharp tip of a medical needle is withdrawn from a patient, a pair of wings with the medical needle positioned in between is closed, and the wings are fastened together with the medical needle positioned between the wings so as to protect a user from the sharp tip of the medical needle. | 03-13-2014 |
20140121694 | TROCAR DISPENSER AND GRIP RECEIVER SAFETY SYSTEM - A disposable system for safely deploying, retrieving and handling a trocar during open surgery. An embodiment comprises a dispenser handle that houses a trocar within a protective sheath during deployment of the trocar within the surgical wound area; and an adjoining receiver that provides a target, shield and active backstop when retrieving the trocar tip from the surgical site. The dispenser handle is shaped ergonomically for easy manipulation; contains a sheath to safely cover the trocar tip during manipulation; and integrates a coupler that permits independent motion between it and the sheath, while releasably gripping the trocar until deployed within the surgical site. The adjoining receiver is comprised of a compact receiver handle grip; an integrated trocar-locking mechanism that traps the trocar when extracting it, while trailing drainage tubing from the surgical site; and a removable safety shield. | 05-01-2014 |
20140221938 | SHARPS PROTECTOR DEVICE FOR PROTECTING A USER FROM A SHARP TIP OF A MEDICAL NEEDLE - A device for protecting a user from a sharp tip of a medical needle includes a central body portion, a medical needle having a sharp tip, a pair of wings in attachment to the central body portion, and a mechanical fastener disposed on at least one of the wings. The mechanical fastener is configured to selectively attach the wings together with the medical needle positioned between the wings so as to protect a user from the sharp tip of the medical needle. In another embodiment, a sharp tip of a medical needle is withdrawn from a patient, a pair of wings with the medical needle positioned in between is closed, and the wings are fastened together with the medical needle positioned between the wings so as to protect a user from the sharp tip of the medical needle. | 08-07-2014 |
20150080814 | MULTI-LUMEN MULTI-CLAMP LUER LOCK SYSTEM - An embodiment of the present invention comprises an adapter configured to divide a single input tubular line into multiple tubular lines used in infusion therapies, which has a manifold at one end that comprises a single input port (e.g., female luer, male luer, barbed tubular pole, or straight tubular port) to which a fluidic source may be connected, multiple output ports (e.g., female tubing ports or barbed tubular poles) to which output infusion tubular lines may be connected, a flow disburser feature to ensure even distribution of fluidic flow within the adapter, recessed slots in the sides of the adapter to clamp the output infusion tubular lines without the need for external clamps, and identifying markings on the outside of the adapter to uniquely identify each of the output tubular lines. The adapter may also incorporate an embedded flow restrictor or filter, eliminating the need for external components and their associated connectors. | 03-19-2015 |
20150335817 | PUMP APPARATUS, SYSTEM AND METHOD OF USE - A system and method of delivering and administering fluids used for infusion and similar therapies is provided that uses a reusable pump including a mechanism that eliminates contact between the pump material and the therapeutic fluid. An adapter for the pump, which is configured to interface with standard or customized drug reservoirs, is additionally provided. | 11-26-2015 |