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| 20100184524 | MOTION SIMULATOR - A motion simulator has a motive device having a base, a moving panel, twelve universal joints mounted on the base and the moving panel and six actuators connected to the universal joints and retractable. A seat assembly is mounted on the moving panel. Therefore, as the actuators retract, the seat assembly is moved in six degrees of freedom such as heave, sway, surge, pitch, roll and yaw. Audiences sitting on the seat assembly feel excited and experience a real virtual reality. Moreover, the actuators bear axial force such as drag force and thrust force and are endurable and safety. | 07-22-2010 |
| 20120258810 | LATERAL DYNAMIC SIMULATION DEVICE - A lateral dynamic simulation device includes a positioning platform ( | 10-11-2012 |
| 20130203512 | BIAXIAL SUSPENSION TYPE DYNAMIC SIMULATOR - A dynamic simulator includes a carrying platform, a movable platform, a load carrying seat, a first actuator pivotally coupled to carrying platform, and a second actuator pivotally coupled to movable platform, and an included angle is formed between the first actuator and the carrying platform, and an included angle is formed between the second actuator and the load carrying seat, and an included angle is formed between the second actuator and the first actuator, so as to simplify the dynamic simulator. | 08-08-2013 |
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| 20100085784 | Ripple Voltage Suppression Method for DC/DC Converter and Apparatus Thereof - A ripple voltage suppression apparatus includes a DC/DC converter and a control circuit. The DC/DC converter has a power electronic switch. The control circuit has a voltage detector detecting a DC output voltage of the DC/DC converter, a ripple voltage suppression circuit receiving the detected DC output voltage to generate an AC control signal for controlling an AC component of a duty ratio of the power electronic switch, an output voltage regulation circuit receiving the detected DC output voltage to generate a DC control signal for controlling an DC component of a duty ratio, an adder adding the AC and DC control signals to form a combined control signal, and a PWM circuit converting the combined control signal into a PWM signal to control the power electronic switch. Only the DC output voltage of the DC/DC converter has to be detected for the control circuit. | 04-08-2010 |
| 20100254170 | DC to AC inverter - A DC to AC inverter has a DC power input port, a buck converter, a buck/boost converter, an output filter and an AC output port. The DC power input port has a positive input terminal and a negative input terminal, both connected to a DC source. The AC output port is connected to a single-phase utility system. When the single-phase utility system is in positive half cycle, the buck converter generates a positive half-cycle signal of sinusoidal current. When the single-phase utility system is in negative half cycle, the buck/boost converter generates a negative half-cycle signal of sinusoidal current. In either the positive or negative half cycles, only one power electronic switch is switched in high frequency to reduce switching loss. Further, the negative input terminal of the DC power input port of the invention can be connected to a neutral line of the single-phase utility system. | 10-07-2010 |
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| 20100302769 | LAMP - A lamp includes a substrate having first and second sides. At least one lighting element is mounted on the first side. An air-guiding member is mounted to the substrate. An airflow chamber is formed between the air-guiding member and the second side of the substrate. The air-guiding member includes a plurality of air-guiding holes in communication with the air-guiding chamber. A plurality of heat-dissipating fans is respectively mounted to the air-guiding holes. A control unit is electrically connected to the heat-dissipating fans. The control unit controls operation timing and operation modes of the heat-dissipating fans so that the lamp has a plurality of heat-dissipating modes. | 12-02-2010 |
| 20110013419 | LINEAR LIGHT GUIDING MODULE - A linear light guiding module is provided, which includes a linear light guiding body, a plurality of light emitting bodies, a plurality of heat sinks, and a plurality of fans. With the linear light guiding body, the light emitting bodies, and the heat sinks linearly arranged, or with the fans further integrated, the linear light guiding module of the present invention has a small size and an effective heat-dissipation effect. Since only one linear light guiding module needs to be disposed on one side of a light guide plate, the linear light guiding module can be used in large-sized liquid crystal display panels. Moreover, the number of the linear light guiding modules used is decreased while the requirements for high brightness and brightness uniformity can still be met, so the cost can be reduced. | 01-20-2011 |
| 20110085342 | HEAT DISSIPATING DEVICE FOR LIGHTING MODULE - A heat dissipating device for a lighting module includes a frame having connecting portions and assembling portions each interconnected between two adjacent connecting portions. Each end of each connecting portion is connected to an adjacent assembling portion. A plurality of air-guiding members is located on the same side of the frame and each mounted on one of the connecting portions. Each air-guiding member includes an air guiding channel having an opening in each end thereof. Each of several heat dissipating fans is mounted to one of the assembling portions and located between two adjacent openings respectively of two adjacent air-guiding members. Each heat dissipating fan includes a first air guiding hole in communication with an environment and at least one second air guiding hole in communication with the two adjacent openings. The air guiding channels and the heat dissipating fans together form a cycling air channel. | 04-14-2011 |
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| 20110278739 | Semiconductor Package - The present invention relates to a semiconductor package. The semiconductor package includes a substrate, a first chip and an interposer. The first chip is mechanically and electrically connected to the substrate. Some signal pads of the interposer are capacitively coupled to some signal pads of the first chip, so as to provide proximity communication between the first chip and the interposer. Whereby, the capacitively coupled signal pads can be made in fine pitch, and therefore the size of the semiconductor package is reduced and the density of the signal pads is increased. | 11-17-2011 |
| 20110291690 | Apparatus and Method for Testing Non-Contact Pads of a Semiconductor Device to be Tested - The present invention relates to an apparatus and a method for testing non-contact pads of a semiconductor device to be tested. The apparatus includes an insulating body, at least one testing module and a plurality of probes. The insulating body includes an accommodating cavity, a lower opening and at least one side opening. The side opening communicates with the accommodating cavity and the lower opening. The testing module is disposed in the side opening, and each testing module includes a circuit board and an active chip. The active chip is disposed on to and electrically connected to the circuit board. The active chip has a plurality of testing pads exposed to the accommodating cavity. The probes are disposed in the lower opening. Whereby, the non-contact pads of the semiconductor device to be tested face but not in physically contact with the testing pads of the active chip, so as to test the proximity communication between the non-contact pads of the semiconductor device and the testing pads of the active chip. | 12-01-2011 |
| 20110298139 | Semiconductor Package - The present invention relates to a semiconductor package. The semiconductor package includes a substrate, a first chip and a second chip. The substrate has a first surface, a second surface and at least one through hole. The first chip is disposed adjacent to the first surface of the substrate. The first chip includes a first active surface and a plurality of first signal pads. Part of the first active surface is exposed to the through hole. The position of the first signal pads corresponds to the through hole. The second chip is disposed adjacent to the second surface. The second chip includes a second active surface and a plurality of second signal pads. Part of the second active surface is exposed to the through hole. The position of the second signal pads corresponds to the through hole, and the second signal pads are capacitively coupled to the first signal pads of the first chip, so as to provide proximity communication between the first chip and the second chip. Whereby, the strength of the first chip and the second chip is increased after being mounted to the substrate, so the yield of the semiconductor package is increased. | 12-08-2011 |
| 20110309516 | SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME - The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a first chip and a second chip. The first chip comprises a first active surface, at least one first non-top metal layer and a plurality of first signal coupling pads. The first non-top metal layer is disposed adjacent to and spaced apart from the first active surface by a second distance. The first signal coupling pads are disposed on the first non-top metal layer. The second chip is electrically connected to the first chip. The second chip comprises a second active surface, at least one second non-top metal layer and a plurality of third signal coupling pads. The second active surface faces the first active surface of the first chip. The second non-top metal layer is disposed adjacent to and spaced apart from the second active surface by a fourth distance. The third signal coupling pads are disposed on the second non-top metal layer and capacitively coupled to the first signal coupling pads of the first chip, so as to provide proximity communication between the first chip and the second chip. Whereby, the gap variation between the first signal coupling pads of the first chip and the third signal coupling pads of the second chip is under stringent control of the second distance and the fourth distance. Therefore, the mass-production yield of the semiconductor package is increased. | 12-22-2011 |
| 20120091575 | Semiconductor Package And Method For Making The Same - The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, at least one first chip, a dielectric layer and at least one second chip. The first chip is attached and electrically connected to the substrate. The first chip includes a first active surface and a plurality of first signal coupling pads. The first signal coupling pads are disposed adjacent to the first active surface. The dielectric layer is disposed on the first active surface. The second chip is attached and electrically connected to the substrate by metal bumps. The second chip includes a second active surface and a plurality of second signal coupling pads. The second active surface contacts the dielectric layer. The second signal coupling pads are disposed adjacent to the second active surface, and capacitively coupled to the first signal coupling pads of the first chip, so as to provide proximity communication between the first chip and the second chip. Whereby, the gap between the first signal coupling pads of the first chip and the second signal coupling pads of the second chip is controlled by the thickness of the dielectric layer. Therefore, the mass-production yield of the semiconductor package is increased. | 04-19-2012 |
| 20140332957 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - The present disclosure relates to a semiconductor package and a manufacturing method thereof The semiconductor package includes a semiconductor element including a main body, a plurality of conductive vias, and at least one filler. The conductive vias penetrate through the main body. The filler is located in the main body, and a coefficient of thermal expansion (CTE) of the filler is different from that of the main body and the conductive vias. Thus, the CTE of the overall semiconductor element can be adjusted, so as to reduce warpage. | 11-13-2014 |
