Patent application number | Description | Published |
20090026515 | Semiconductor memory device and method of forming the same - Example embodiments relate to a semiconductor memory device and a method of forming the semiconductor memory device. The semiconductor memory device may include a first interlayer insulating layer on a semiconductor substrate. A bit line may be arranged in a first direction on the first interlayer insulating layer. A bit line contact pad may be disposed in the first interlayer insulating layer and electrically connected to the bit line. A storage contact pad may be disposed in the first interlayer insulating layer. A top surface of the bit line contact pad may be lower than a top surface of the storage contact pad. | 01-29-2009 |
20090085083 | Semiconductor memory device and method of forming the same - Provided may be a semiconductor memory device and a method of forming the semiconductor memory device. The memory device of example embodiments may include a bit line structure including a bit line on a semiconductor substrate, and a buried contact plug structure including a buried contact pad and a buried contact plug that extends in a lower portion of the bit line from one side of the bit line and connected to the buried contact pad. A width of the buried contact plug near a top surface of the buried contact pad may be greater than a width of the buried contact plug adjacent to the bit line. | 04-02-2009 |
20100112768 | METHOD OF MANUFACTURING NON-VOLATILE SEMICONDUCTOR DEVICES - A non-volatile semiconductor device includes a memory cell in a first area of a substrate, a low voltage transistor in a second area of the substrate, and a high voltage transistor in a third area of the substrate. The memory cell includes a tunnel insulation layer formed on the substrate, a charge trapping layer pattern formed on the tunnel insulation layer in the first area of the substrate, a blocking layer pattern formed on the charge trapping layer pattern and a control gate formed on the blocking layer pattern. The control gate has a width substantially smaller than a width of the blocking layer pattern and the width of the control gate is substantially smaller than a width of the charge trapping layer pattern. In addition, an offset is formed between the control gate and the blocking layer pattern such that a spacer is not formed on a sidewall of the control gate. | 05-06-2010 |
20100173469 | METHODS OF MANUFACTURING CHARGE TRAP-TYPE NON-VOLATILE MEMORY DEVICES - Some methods are directed to manufacturing charge trap-type non-volatile memory devices. An isolation layer pattern can be formed that extends in a first direction in a substrate. A recess unit is formed in the substrate by recessing an exposed surface of the substrate adjacent to the isolation layer pattern. A tunnel insulating layer and a charge trap layer are sequentially formed on the substrate. The tunnel insulating layer and the charge trap layer are patterned to form an isolated island-shaped tunnel insulating layer pattern and an isolated island-shaped charge trap layer pattern by etching defined regions of the substrate, the isolation layer pattern, the tunnel insulating layer, and the charge trap layer until a top surface of the charge trap layer that is disposed on a bottom surface of the recess unit is aligned with a top surface of the isolation layer pattern. A blocking insulating layer is formed that covers the charge trap layer pattern, the isolation layer pattern, and a defined region of the substrate interposed between the charge trap patterns. A gate electrode pattern is formed on the blocking insulating layer to face the charge trap layer pattern. This manufacturing process may reduce charge spreading between unit memory cells and/or may prevent/avoid reduction in the breakdown voltage of the blocking insulating layer. | 07-08-2010 |
20100237401 | GATE STRUCTURES OF SEMICONDUCTOR DEVICES - Gate structures of semiconductor devices and methods of forming gate structures of semiconductor devices are provided. A first insulating pattern may be disposed on an active region of a semiconductor substrate. A data storage pattern may be disposed on the first insulating pattern. A second insulating pattern may be disposed on the data storage pattern and may contact the data storage pattern. A first conductive pattern may conform to the second insulating pattern and to sidewalls of a mold comprising the second insulating pattern. A second conductive pattern may be disposed within a cavity defined by the first conductive pattern. Spacers may be formed on sidewalls of at least one of the first insulating pattern, the data storage pattern, the second insulating pattern, and the conductive pattern. | 09-23-2010 |
20110045643 | Method of forming active region structure - A method of forming an active region structure includes preparing a semiconductor substrate including a cell array region and a peripheral circuit region, forming preliminary cell active regions in the cell array region of the semiconductor substrate, and forming cell active regions in the preliminary cell active regions and at least one peripheral active region in the peripheral circuit region of the semiconductor substrate, such that the preliminary cell active regions, the cell active regions, and the at least one peripheral active region are integrally formed with the semiconductor substrate and protrude from the semiconductor substrate. | 02-24-2011 |
20110053327 | METHOD OF FORMING RECESS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING THE SAME - Example embodiments relate to a method of forming a recess and a method of manufacturing a semiconductor device having the same. The method includes forming a field region defining an active region in a substrate. The active region extends in a first direction in the substrate. The method further includes forming a preliminary recess extending in a second direction different from the first direction and crossing the active region in the substrate, plasma-oxidizing the substrate to form a sacrificial oxide layer along a surface of the substrate having the preliminary recess, and removing portions of the sacrificial oxide layer and the active region by plasma etching to form a recess having a width larger than a width of the preliminary recess, where an etch rate of the active region is one to two times greater than an etch rate of the sacrificial oxide layer. | 03-03-2011 |
20110143537 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND SYNCHRONOUS PULSE PLASMA ETCHING EQUIPMENT FOR THE SAME - Provided are a method of fabricating a semiconductor device and synchronous pulse plasma etching equipment for the same. The method includes outputting a first radio frequency (RF) power and a control signal and outputting a second RF power. The first RF power is pulse-width modulated to have a first frequency and a first duty ratio, and is applied to a first electrode in a plasma etching chamber. The control signal includes information on a phase of the first RF power. The second RF power is pulse-width modulated to have the first frequency and a second duty ratio smaller than the first duty ratio, is applied to a corresponding second electrode among second electrodes in the plasma etching chamber, and is supplied for a time section in which the first RF power is supplied. | 06-16-2011 |
20110233653 | NON-VOLATILE SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING NON-VOLATILE SEMICONDUCTOR DEVICES - A non-volatile semiconductor device includes a memory cell in a first area of a substrate, a low voltage transistor in a second area of the substrate, and a high voltage transistor in a third area of the substrate. The memory cell includes a tunnel insulation layer formed on the substrate, a charge trapping layer pattern formed on the tunnel insulation layer in the first area of the substrate, a blocking layer pattern formed on the charge trapping layer pattern and a control gate formed on the blocking layer pattern. The control gate has a width substantially smaller than a width of the blocking layer pattern and the width of the control gate is substantially smaller than a width of the charge trapping layer pattern. In addition, an offset is formed between the control gate and the blocking layer pattern such that a spacer is not formed on a sidewall of the control gate. | 09-29-2011 |
20110284163 | PLASMA PROCESSING APPARATUS - A plasma processing apparatus includes a chamber for processing a substrate. A plasma generator is provided to generate plasma within the chamber. A window is provided in a sidewall of the chamber, and the window transmits light from the plasma within the chamber. A photocatalytic layer is provided on an inner surface of the window such that the photocatalytic layer is activated as a result of exposure to light from the plasma to decompose a residual product on the inner surface of the window. | 11-24-2011 |
20110318930 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A first gas for plasma etch and a second gas for plasma deposition are introduced onto a semiconductor substrate, the semiconductor substrate including a mask pattern. A flow rate of the first and second gases is periodically changed within a range of flow rates during a process cycle, such that a plasma etch process and a plasma deposition process are performed together to form an opening in the semiconductor substrate. | 12-29-2011 |
20120064709 | METHOD OF FORMING SEMICONDUCTOR DEVICE - Provided is a method of forming a semiconductor device. The method may include forming a first insulating layer on a semiconductor substrate. A first polycrystalline silicon layer may be formed on the first insulating layer. A second insulating layer may be formed on the first polycrystalline silicon layer. A second polycrystalline silicon layer may be formed on the second insulating layer. A mask pattern may be formed on the second polycrystalline silicon layer. The second polycrystalline silicon layer may be patterned using the mask pattern as an etch mask to form a second polycrystalline silicon pattern exposing a portion of the second insulating to layer. A sidewall of the second polycrystalline silicon pattern may include a first amorphous region. The first amorphous region may be crystallized by a first recrystallization process. The exposed portion of the second insulating layer may be removed to form a second insulating pattern exposing a portion of the first polycrystalline silicon layer. The exposed portion of the first polycrystalline silicon layer may be removed to form a first polycrystalline silicon pattern exposing a portion of the first insulating layer. The exposed portion of the first insulating layer may be removed to form a first insulating pattern exposing a portion of the semiconductor substrate. | 03-15-2012 |
20120126426 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME - Provided may be a semiconductor memory device and a method of forming the semiconductor memory device. The memory device of example embodiments may include a bit line structure including a bit line on a semiconductor substrate, and a buried contact plug structure including a buried contact pad and a buried contact plug that extends in a lower portion of the bit line from one side of the bit line and connected to the buried contact pad. A width of the buried contact plug near a top surface of the buried contact pad may be greater than a width of the buried contact plug adjacent to the bit line. | 05-24-2012 |
20120164809 | SEMICONDUCTOR DEVICES INCLUDING STRAINED SEMICONDUCTOR REGIONS, METHODS OF FABRICATING THE SAME, AND ELECTRONIC SYSTEMS INCLUDING THE DEVICES - A method of fabricating a semiconductor device includes forming a gate pattern on a substrate, forming an amorphous silicon (a-Si) region adjacent to the gate pattern by implanting a dopant containing a Group IV or VIII element into portions of the semiconductor substrate, forming gate spacers on sidewalls of the gate pattern, forming a first cavity by etching the a-Si region and the substrate using a first etching process, forming a second cavity by etching the substrate, such that the second cavity expands a profile of the first cavity in lateral and vertical directions, and forming a strained semiconductor region in the second cavity. | 06-28-2012 |
20130048603 | METHOD OF FORMING MICROPATTERNS - A method of forming micropatterns separated over a misalignment margin includes forming a first mold pattern including a main pattern and a separation-assist pattern, forming a first spacer mask having a first width around the first mold pattern, forming a second mold pattern using the first spacer mask as an etch mask, forming a second spacer mask having a second width around the second mold pattern, and forming a target pattern using the second spacer mask as an etch mask. | 02-28-2013 |
20130095654 | METHODS OF MANUFACTURING A VERTICAL TYPE SEMICONDUCTOR DEVICE - According to example embodiments of inventive concepts, a method includes forming cell patterns and insulating interlayers between the cell patterns on the substrate. An upper insulating interlayer including initial and preliminary contact holes is formed on an uppermost cell pattern. A first reflection limiting layer pattern and a first photoresist layer pattern are formed for exposing a first preliminary contact hole while covering inlet portion of the initial and preliminary contact holes. A first etching process is performed on layers under the first preliminary contact hole to expose the cell pattern at a lower position than a bottom of the first preliminary contact hole. A partial removing process of sidewall portions of the first reflection limiting layer pattern and the first photoresist layer pattern and an etching process on exposed layers through bottom portions of the preliminary contact holes are repeated for forming contact holes having different depths. | 04-18-2013 |
20130105983 | SEMICONDUCTOR DEVICE AND METHOD FORMING PATTERNS WITH SPACED PADS IN TRIM REGION | 05-02-2013 |
20130320486 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided. | 12-05-2013 |
20140162420 | METHOD OF FABRICATING SEMICONDUCTOR DEVICES HAVING VERTICAL CELLS - According to example embodiments, a method of fabricating a semiconductor device includes: forming a preliminary stack structure including upper and lower preliminary stack structures by alternately stacking a plurality of interlayer insulating and sacrificial layers on a cell, first pad area, sacrificial area and second pad area of a substrate; removing an entire portion of the upper preliminary stack structure on the second pad area; forming a first mask defining openings over parts of the first and second pad areas; etching an etch depth corresponding to ones of the plurality of interlayer insulating and sacrificial layers through a remaining part of the preliminary stack structure exposed by the first mask; and repetitively performing a first staircase forming process that includes shrinking sides of the first mask and etching the etch depth through remaining parts of the plurality of interlayer insulating and sacrificial layers exposed by the shrunken first mask. | 06-12-2014 |
20140332970 | SEMICONDUCTOR DEVICE AND METHOD FORMING PATTERNS WITH SPACED PADS IN TRIM REGION - In a semiconductor device, parallel first and second conductive lines having a unit width extend from a memory cell region into a connection region. A trim region in the connection region includes pads respectively connected to the first and second conductive lines but are separated by a width much greater than the unit width. | 11-13-2014 |
20150054054 | SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns. | 02-26-2015 |