Patent application number | Description | Published |
20110107344 | MULTI-CORE APPARATUS AND LOAD BALANCING METHOD THEREOF - A multi-core apparatus and method for balancing load in the multi-core apparatus. The multi-core apparatus includes a first core that sends a save request including a context of a task, when a task is switched from an active state to a sleep state, a second core that receives an execution request and executes a task corresponding to the execution request, and a load balancer that receives the save request transmitted by the first core, and sends the execution request to the second core. | 05-05-2011 |
20120060168 | VIRTUALIZATION SYSTEM AND RESOURCE ALLOCATION METHOD THEREOF - A virtualization system for supporting at least two operating systems and resource allocation method of the virtualization system are provided. The method includes allocating resources to the operating systems, calculating, when one of the operating systems is running, workloads for each operating system, and adjusting resources allocated to the operating systems according to the calculated workloads. The present invention determines the workloads of a plurality of operating systems running in the virtualization system and allocates time resources dynamically according to the variation of the workloads. | 03-08-2012 |
20120075316 | METHOD AND APPARATUS FOR COMPILING AND EXECUTING AN APPLICATION USING VIRTUALIZATION IN A HETEROGENEOUS SYSTEM - A method and apparatus for compiling and executing an application including Central Processing Unit (CPU) source code and Graphic Processing Unit (GPU) source code. The apparatus includes a hardware device including a CPU and a GPU; a compiler that compiles the GPU source code into a GPU virtual instruction; and a hybrid virtualization block that executes an execution file by translating the GPU virtual instruction into GPU machine code. | 03-29-2012 |
20120079498 | METHOD AND APPARATUS FOR DYNAMIC RESOURCE ALLOCATION OF PROCESSING UNITS - A method and apparatus for dynamic resource allocation in a system having at least one processing unit are disclosed. The method of dynamic resource allocation includes receiving information on a task to which resources are allocated and partitioning the task into one or more task parallel units; converting the task into a task block having a polygonal shape according to expected execution times of the task parallel units and dependency between the task parallel units; allocating resources to the task block by placing the task block on a resource allocation plane having a horizontal axis of time and a vertical axis of processing units; and executing the task according to the resource allocation information. Hence, CPU resources and GPU resources in the system can be used in parallel at the same time, increasing overall system efficiency. | 03-29-2012 |
20140156251 | SIMULATION DEVICE AND SIMULATION METHOD THEREFOR - The present invention relates to a simulation method and device. According to the present invention, a simulation method using a plurality of blocks comprises: a dividing step of dividing a simulation into computation operations for performing unique operations on the blocks and communication operations for data exchanges between different blocks; a grouping step of performing a grouping between the interdependent computation and communication operations; and a simulation performing step of performing an operation included in each group using the blocks according to whether or not the level of interdependency between the computation and communication operations is resolved. | 06-05-2014 |
Patent application number | Description | Published |
20080319157 | METHOD FOR PRODUCING NORBORNENE MONOMER COMPOSITION, NORBORNENE POLYMER PREPARED THEREFROM, OPTICAL FILM COMPRISING THE NORBORNENE POLYMER, AND METHOD FOR PRODUCING THE NORBORNENE POLYMER - Disclosed is a method for producing a norbornene monomer composition, a norbornene polymer produced using the norbornene monomer composition, an optical film including the norbornene polymer, and a method for producing the norbornene polymer. The method includes reacting a reaction solution that contains cyclopentadiene, dicyclopentadiene, or a mixture of cyclopentadiene and dicyclopentadiene, an acetate compound, and a solvent so that a content of an exo isomer is 50 mol % or more. Variables such as a reaction temperature, a reaction time, a molar ratio between reactants, and addition of a solvent are controlled so that the exo isomer is contained in content of 50 mol % or more. Accordingly, it is possible to industrially produce an acetate norbornene addition polymer by using the acetate norbornene monomer composition containing the exo isomer in content of 50 mol % or more. | 12-25-2008 |
20110245069 | CATALYST SYSTEM FOR PREPARING CYCLIC OLEFIN ADDITION POLYMER, CYCLIC OLEFIN ADDITION POLYMER PREPARED BY USING THE CATALYST SYSTSEM AND METHOD FOR PREPARING THE SAME - The present invention relates to a catalyst system for preparing a cyclic olefin addition polymer, a method for preparing the catalyst system and a cyclic olefin addition polymer prepared by the method, and more particularly to the method comprising the steps of contacting some content of norbornene-based monomer having a specific polar functional group with a catalyst system comprising a) a Group X transition metal compound; b) a compound comprising a neutral Group XV electron donor ligand having a cone angle of at least 160°; and c) a salt capable of offering an anion that can be weakly coordinated to the transition metal of the a) the Group X transition metal compound. | 10-06-2011 |
Patent application number | Description | Published |
20110055541 | METHOD AND APPARATUS FOR BOOTING HIBERNATION IN A PORTABLE TERMINAL - A method and apparatus for hibernation booting in a mobile terminal supporting two processors are provided. In the hibernation booting method, when power is turned on, a master processor performs hibernation booting. A slave processor performs normal booting under control of the master processor. The master processor and the slave processor determine data needing synchronizing, and perform synchronization depending on whether the data needing synchronizing have been changed. | 03-03-2011 |
20120096256 | MOBILE DEVICE AND METHOD FOR SUPPORTING HIBERNATION FUNCTION - A method and apparatus for supporting a hibernation function in a mobile device are provided. In the method, the mobile device detects a wakeup event in a hibernation mode and, in response to the wakeup event, loads a snapshot image into a volatile memory from a snapshot image region of a nonvolatile memory. After the loading of the snapshot image, the mobile device determines whether there is a system status has been modified. If the system status has not been modified, the mobile device finishes a system boot. If the system status has been modified, the mobile device performs data synchronization and then finishes the system boot. | 04-19-2012 |
20130290746 | SYSTEM, APPARATUS, AND METHOD OF PERFORMING CHARGING OPERATION IN HOST MODE - A system, an apparatus, and a method of performing a charging operation in a host mode, which can perform a charging operation in a host mode of a terminal includes a terminal for simultaneously receiving a function of performing communication with a peripheral device and a charging function from an external accessory connected in the host mode. The external accessory simultaneously provides the charging function while performing the communication with the peripheral device to the terminal in a client mode. | 10-31-2013 |
20140070165 | LIGHT EMITTING DEVICE - The disclosed light emitting device includes an intermediate layer interposed between the light emitting semiconductor structure and the substrate. The light emitting semiconductor structure includes a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an active layer interposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, wherein the active layer has a multi quantum well structure including at least one period of a pair structure of a quantum barrier layer including Al | 03-13-2014 |
20140084317 | ULTRAVIOLET LIGHT EMITTING DEVICE - Disclosed is a light emitting device including an active layer emitting light with a wavelength band of 200 nm to 405 nm, and a light-transmitting layer disposed on the active layer, the light-transmitting layer having a lower part facing the active layer, wherein at least one of side and upper parts of the light-transmitting layer has a surface-processed pattern portion. | 03-27-2014 |
20140344563 | MOBILE DEVICE AND METHOD FOR SUPPORTING HIBERNATION FUNCTION - A method and an apparatus for supporting a hibernation function in a mobile device are provided. The method includes receiving an input at an electronic device, loading, using one or more processors, a snapshot image for the electronic device in response to the input, comparing at least one portion of the snapshot image with data indicating a state of the electronic device, and updating the snapshot image using the data, based at least in part on a determination that the state of the electronic device has been changed. | 11-20-2014 |
20140351458 | APPARATUS AND METHOD OF RECOGNIZING EXTERNAL DEVICE IN A COMMUNICATION SYSTEM - An apparatus and a method of recognizing an external device in a portable terminal are provided. The apparatus includes a connector connected to the external device, and a controller configured to transmit a connection message, if the portable terminal is connected to the external device through the connector, the connection message asking whether the external device supports a second connection scheme to the external device by using a first connection scheme, configured to receive a connection response message as a response to the connection message from the external device, configured to determine based on the connection response message whether the external device supports the second connection scheme, and configured to recognize at least one device supporting the second connection scheme in the external device by activating the second connection scheme, if the external device supports the second connection scheme. | 11-27-2014 |
20150063337 | METHOD FOR CONTROLLING TRANSMISSION SPEED AND ELECTRONIC DEVICE THEREOF - A method of operating an electronic device is provided. The method includes communicating data with a wireless network using a wireless communication, connecting to an external electronic device using a wired communication, exchanging data with the external device at a first data throughput using the wired communication while performing the wireless communication, and changing the first data throughput to a second data throughput while performing the wireless communication. | 03-05-2015 |
20150179878 | LIGHT EMITTING DEVICE - The disclosed light emitting device includes an intermediate layer interposed between the light emitting semiconductor structure and the substrate. The light emitting semiconductor structure includes a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an active layer interposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer, wherein the active layer has a multi quantum well structure including at least one period of a pair structure of a quantum barrier layer including Al | 06-25-2015 |
20150214448 | ULTRAVIOLET LIGHT EMITTING DEVICE - Disclosed is a light emitting device including an active layer emitting light with a wavelength band of 200 nm to 405 nm, and a light-transmitting layer disposed on the active layer, the light-transmitting layer having a lower part facing the active layer, wherein at least one of side and upper parts of the light-transmitting layer has a surface-processed pattern portion. | 07-30-2015 |
Patent application number | Description | Published |
20090278189 | SEMICONDUCTOR DEVICE WITH RESISTOR AND METHOD OF FABRICATING SAME - A semiconductor device includes a cell array region disposed on a semiconductor substrate and comprising a first cell gate pattern, a cell semiconductor pattern disposed on the first cell gate pattern, and a second cell gate pattern disposed on the cell semiconductor pattern. The semiconductor device also includes a peripheral circuit region disposed on the semiconductor substrate and comprising a peripheral gate pattern, and a resistor disposed in the peripheral circuit region at level above the semiconductor substrate similar to that of the cell semiconductor pattern. | 11-12-2009 |
20100258947 | Nonvolatile memory devices - Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays. | 10-14-2010 |
20110291172 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate doped with a first conductive type dopant, a plurality of stacked structures arranged side by side on the substrate and extending in a first direction, each of the stacked structures including gate electrodes spaced apart from each other, the plurality of stacked structures including a pair of stacked structures spaced apart from each other at a first interval in a second direction perpendicular to the first direction, and a pick-up region extending in the first direction in the substrate between the pair of stacked structures and doped with the first conductive type dopant. | 12-01-2011 |
20120098050 | Three-Dimensional Semiconductor Devices - Three-dimensional semiconductor devices may be provided. The devices may include a stack-structure including gate patterns and an insulation pattern. The stack-structure may further include a first portion and a second portion, and the second portion of the stack-structure may have a narrower width than the first portion. The devices may also include an active pattern that penetrates the stack-structure. The devices may further include a common source region adjacent the stack-structure. The devices may additionally include a strapping contact plug on the common source region. | 04-26-2012 |
20120228712 | NONVOLATILE MEMORY DEVICES - Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays. | 09-13-2012 |
20150076587 | NONVOLATILE MEMORY DEVICES HAVING A THREE DIMENSIONAL STRUCTURE - Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays. | 03-19-2015 |
20150147858 | METHODS OF MANUFACTURING NON-VOLATILE MEMORY DEVICES - A non-volatile memory device includes a substrate including an active region and a field region, selection transistors and cell transistors on the active region, bit line contacts on the bridge portions, and shared bit lines electrically connected to the bit line contacts. The active region includes string portions and bridge portions. The string portions extend in a first direction and are arranged in a second direction substantially perpendicular to the first direction, and the bridge portions connect at least two adjacent string portions. Each bridge portion has a length in the first direction equal to or longer than about twice a width of each bit line contact in the first direction. | 05-28-2015 |