Patent application number | Description | Published |
20080218959 | Combo internal and external storage system - A combo internal and external storage system which comprising: an enclosure portion, having a plurality of openings on it's real wall and a hollow space for containing the storage device which further comprises a first power interface and a first data interface; and a first PCB, being disposed in the hollow space and further comprising a first connector, a second power interface, a second data interface, a second connector and a power connector; wherein the first connector is used to connect to the first power interface and first data interface of the storage device, the second data interface and second data interface are used to connect to a power interface and data interface of the cradle portion, and the second connector and power connector are used to connect to the computer or equipment by the cable. | 09-11-2008 |
20100205454 | CIPHER DATA BOX - A cipher data box comprises: a housing; a printed circuit board; a first connector; a second connector; a controller, having a unique first identification code; a key seat; and a key, having a unique second identification code; therefore, when the key is inserted into the key seat and the first identification code is same as the second identification code, the storage device can be normally accessed, and the data therein will be encrypted/decrypted. Furthermore, for further enhancing the security function of the storage device, a plurality of cipher data boxes of the present invention can be cascade each other. | 08-12-2010 |
Patent application number | Description | Published |
20120314499 | INTELLIGENT SHIFTING OF READ PASS VOLTAGES FOR NON-VOLATILE STORAGE - A first read pass voltage is determined and optimized for cycled memory. One or more starting read pass voltages are determined for one or more dies. The system dynamically calculates a current read pass voltage based on the number of program/erase erase cycles, the first read pass voltage and the respective starting read pass voltage. Data is read from one or more non-volatile storage elements using the calculated current read pass voltage. | 12-13-2012 |
20140365836 | Device and Method for Resolving an LM Flag Issue - The reliability with which data can be read from a storage medium, such as flash memory storage medium, is enhanced by updating an upper limit of a reading threshold voltage window for a respective portion of the storage medium. For each memory cell in the respective portion of the storage medium, a memory controller is configured to perform a plurality of sensing operations and obtain results from the plurality of sensing operations, where the plurality of sensing operations includes sensing operations using a predefined range of offsets from a previously established reading threshold voltage. The memory controller is further configured to determine the updated upper limit of the reading threshold voltage window based on the-results from the plurality of sensing operations, and store the updated upper limit of the reading threshold voltage window for the respective portion of the storage medium. | 12-11-2014 |
20160093390 | Read With Look-Back Combined With Programming With Asymmetric Boosting In Memory - A read operation compensates for program disturb when distinguishing between an erased-state and a lowest programmed data state, where the program disturb is a function of the data state of an adjacent, previously-programmed memory cell on a common charge-trapping layer. The read operation occurs in connection with a programming operation which avoids program disturb of the programmed data states by using asymmetric pass voltages. Before reading the memory cells on a selected word line (WLn), the memory cells on the adjacent, previously-programmed word line (WLn−1) are read. The read operation for WLn uses multiple read voltages—one for each data state on WLn−1, and one of the read results is selected based on the data state of the adjacent memory cell. Other read operations distinguish between each pair of adjacent programmed data states using a read voltage which is independent of the data state of the adjacent memory cell. | 03-31-2016 |
Patent application number | Description | Published |
20120225191 | Apparatus and Process for Atomic Layer Deposition - Provided are atomic layer deposition apparatus and methods including a gas distribution plate comprising at least one gas injector unit. Each gas injector unit comprises a plurality of elongate gas injectors including at least two first reactive gas injectors and at least one second reactive gas injector, the at least two first reactive gas injectors surrounding the at least one second reactive gas injector. Also provided are atomic layer deposition apparatuses and methods including a gas distribution plate with a plurality of gas injector units. | 09-06-2012 |
20120225192 | Apparatus And Process For Atomic Layer Deposition - Provided are atomic layer deposition apparatus and methods including a gas distribution plate comprising at least one gas injector unit. Each gas injector unit comprises a plurality of elongate gas injectors including at least two first reactive gas injectors and at least one second reactive gas injector, the at least two first reactive gas injectors surrounding the at least one second reactive gas injector. Also provided are atomic layer deposition apparatuses and methods including a gas distribution plate with a plurality of gas injector units. | 09-06-2012 |
20120269967 | Hot Wire Atomic Layer Deposition Apparatus And Methods Of Use - Provided are gas distribution plates for atomic layer deposition apparatus including a hot wire or hot wire unit which can be heated to excite gaseous species while processing a substrate. Methods of processing substrates using a hot wire to excite gaseous precursor species are also described. | 10-25-2012 |
20130143415 | Multi-Component Film Deposition - Provided are atomic layer deposition apparatus and methods including a gas distribution plate comprising a plurality of elongate gas ports including at least one first reactive gas port in fluid communication with a first reactive gas and at least one second reactive gas port in fluid communication with a gas manifold. The gas manifold is in fluid communication with at least a second reactive gas different from the first reactive gas and a purge gas. Also provided are atomic layer deposition apparatus and methods including linear energy sources in one or more of region before the gas distribution plate and a region after the gas distribution plate. | 06-06-2013 |
20130164445 | Self-Contained Heating Element - Provided are assemblies comprising an elongate enclosure comprising a material resistant to thermal expansion at temperatures experienced in a processing chamber. At least one heating element extends along a longitudinal axis of the elongate enclosure through an open interior region allowing a flow of gases to pass the heating element in a direction substantially perpendicular to the longitudinal axis. Methods of processing substrates using a heating element to excite gaseous precursor species are also described. | 06-27-2013 |
20150048739 | Elongated Capacitively Coupled Plasma Source For High Temperature Low Pressure Environments - A modular plasma source assembly for use with a processing chamber is described. The assembly includes an RF hot electrode with an end dielectric and a sliding ground connection positioned adjacent the sides of the electrode. A seal foil connects the sliding ground connection to the housing to provide a grounded sliding ground connection separated from the hot electrode by the end dielectric. A coaxial feed line passes through a conduit into the RF hot electrode isolated from the processing environment so that the coaxial RF feed line is at atmospheric pressure while the plasma processing region is at reduced pressure. | 02-19-2015 |
20150368798 | Apparatus And Process Containment For Spatially Separated Atomic Layer Deposition - Provided are atomic layer deposition apparatus and methods including a gas distribution plate comprising a plurality of elongate gas ports with gas curtains extending along the outer length of the gas distribution plate. Also provided are atomic layer deposition apparatuses and methods including a gas distribution plate with a plurality of elongate gas ports with gas curtains. | 12-24-2015 |
20160068958 | Lamp Heater For Atomic Layer Deposition - Apparatus and methods for processing a plurality of semiconductor wafers on a susceptor assembly so that the temperature across the susceptor assembly is uniform are described. A plurality of linear lamps are positioned and controlled in zones to provide uniform heating. | 03-10-2016 |
20160097122 | TOP LAMP MODULE FOR CAROUSEL DEPOSITION CHAMBER - A heating module for use in a substrate processing chamber. The heating module having a housing with a heat source therein. The heating module can be part of a gas distribution assembly positioned above a susceptor assembly to heat the top surface of the susceptor and wafers directly. The heating module can have constant or variable power output. Processing chambers and methods of processing a wafer using the heating module are described. | 04-07-2016 |
Patent application number | Description | Published |
20120215706 | Methods And Systems For Providing A Recognition User Interface For An Enterprise Social Network - A method for providing a recognition user interface for an enterprise social network including users associated with an entity. The method can include receiving a recognition request to award recognition to a second user of the enterprise social network. The recognition request can include identification information associated with the first user. In response to receiving the request, a profile associated with the second user can be accessed from one or more databases associated with the enterprise social network. A total recognition parameter in the profile associated with the second user can be updated. The updated total recognition parameter associated with the second user and the identification information associated with the first user can be saved in the one or more databases. | 08-23-2012 |
20120215707 | Methods And Systems For Providing A Recognition User Interface For An Enterprise Social Network - A method for providing a recognition user interface for an enterprise social network including users associated with an entity. The method can include receiving a request for a recognition leader board of users of the enterprise social network. The recognition leader board can be based on users of the enterprise social network awarding recognition to other users of the enterprise social network. In response to the request, recognition leader board information can be obtained. The recognition leader board information can comprise an ordered list of users based on an amount of recognition each user has been awarded. The recognition leader board information can be transmitted to the user system associated with the user for display. | 08-23-2012 |
20140013400 | COMPUTER IMPLEMENTED METHODS AND APPARATUS FOR MANAGING PERMISSION SETS AND VALIDATING USER ASSIGNMENTS - Disclosed are methods, apparatus, systems, and computer-readable storage media for modifying permission sets and validating permission set assignments to users. In some implementations, a computing device receives a request to create a permission set containing one or more permissions and assign the permission set to a first user. The first user is associated with a first user constraint that defines a first group of permissions available to the first user. The computing device may determine that the permission set to be assigned to the first user does not violate the first user constraint, and may assign the permission set to the first user. | 01-09-2014 |
20140173553 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR CREATING AN APPLICATION WITHIN A SYSTEM - In accordance with embodiments, there are provided mechanisms and methods for creating an application within a system. These mechanisms and methods for creating an application within a system can enable improved application diversity and productivity, enhanced customer experience, increased user flexibility, etc. | 06-19-2014 |
Patent application number | Description | Published |
20140129807 | APPROACH FOR EFFICIENT ARITHMETIC OPERATIONS - A system and method are described for providing hints to a processing unit that subsequent operations are likely. Responsively, the processing unit takes steps to prepare for the likely subsequent operations. Where the hints are more likely than not to be correct, the processing unit operates more efficiently. For example, in an embodiment, the processing unit consumes less power. In another embodiment, subsequent operations are performed more quickly because the processing unit is prepared to efficiently handle the subsequent operations. | 05-08-2014 |
20140143564 | APPROACH TO POWER REDUCTION IN FLOATING-POINT OPERATIONS - An approach is provided for enabling power reduction in floating-point operations. In one example, a system receives floating-point numbers of a fused multiply-add instruction. The system determines the fused multiply-add instruction does not require compliance with a standard of precision for floating-point numbers. The system generates gating signals for an integrated circuit that is configured to perform operations of the fused multiply-add instruction. The system then sends the gating signals to the integrated circuit to turn off a plurality of logic gates included in the integrated circuit. | 05-22-2014 |
20150089202 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING MULTI-CYCLE REGISTER FILE BYPASS - A system, method, and computer program product are provided for implementing a multi-cycle register file bypass mechanism. The method includes the steps of receiving a set of control bits, combining the set of control bits with a set of valid bits associated with previously issued instructions, and enabling a bypass path for each thread based on the set of control bits and the set of valid bits. Each valid bit in the set of valid bits indicates whether execution of an instruction of the previously issued instructions was enabled for a thread in a thread block. | 03-26-2015 |
Patent application number | Description | Published |
20140028578 | TOUCH GESTURE WITH VISIBLE POINT OF INTERACTION ON A TOUCH SCREEN - A computer-implemented method is disclosed. The method includes: detecting at least two touches on a touch screen; determining a touch area corresponding to at least two of the touches; determining a location on the touch screen in proximity to, but at least partially outside of the touch areas; and displaying a point of interaction at the determined location on the touch screen. | 01-30-2014 |
20140138221 | ALUMINUM OXIDE CONTROL MECHANISM - A control mechanism comprises a housing defining an interior and an exterior, an aperture formed in the housing and extending from the interior to the exterior thereof, an actuator on the interior of the housing, proximate the control aperture, and a control member positionable within the aperture to operate the actuator. The control member comprises a first surface exposed to the exterior of the housing, a second surface proximate the actuator within the housing, and a body portion extending therebetween, the body portion being formed of a substantially single crystal aluminum oxide material. A bias member is configured to bias the body portion of the control member toward an inner surface of the housing, such that the control member is retained within the aperture in operation of the actuator. | 05-22-2014 |
20140139978 | LAMINATED ALUMINUM OXIDE COVER COMPONENT - A cover glass for an electronic display comprises a plurality of layers of sapphire material, each of the layers having a substantially single crystal plane orientation, with adjacent layers having different substantially single crystal plane orientations. One or more interface layers are defined between adjacent layers of the sapphire material, with the adjacent layers of sapphire material bonded together at the one or more interface layers. A display window is defined in the cover glass, and configured for viewing a viewable area of the electronic display through the plurality of layers of the sapphire material bonded together at the one or more interface layers. | 05-22-2014 |
20140140558 | ACTIVE PROTECTION FOR ACOUSTIC DEVICE - A device comprises a housing, an acoustic component coupled to an exterior of the device through an acoustic passage in the housing, and an actuated mechanism operable to close the acoustic passage between the acoustic component and the housing. The actuated mechanism is operable to close the acoustic passage in response to a control signal, where the control signal is indicative of a pressure differential transmittable from the exterior of the device through the acoustic passage to the acoustic component. | 05-22-2014 |
20140192459 | CERAMIC INSERT CONTROL MECHANISM - A control mechanism for an electronic device comprises a cover glass having an aperture defined therein. The aperture extends from an interior to an exterior of the device. A control member is positioned within the aperture, coupled to an actuator. The control member comprises a ceramic insert having a contact surface exposed to the exterior of the housing, operable to actuate the actuator in response to a force on the contact surface. A bearing member is molded about the insert. The bearing member has a hardness less than that of the ceramic insert, and less than that of the cover glass. | 07-10-2014 |
20140192467 | ION IMPLANT INDICIA FOR COVER GLASS OR DISPLAY COMPONENT - An aluminum oxide ceramic is formed into a sapphire component for an electronic device. Indicia are embedded into at least one major surface of the component, for example by ion implantation, where ions are fixed into a subsurface pattern layer. The subsurface pattern layer defines the indicia by altering an optical or chromatic property of the aluminum oxide material, so that the indicia are visible from an external surface of the component. | 07-10-2014 |
20140193606 | SAPPHIRE COMPONENT WITH RESIDUAL COMPRESSIVE STRESS - A method comprises shaping an aluminum oxide ceramic material into a component for an electronic device. The component has first and second major surfaces. A selected region of one or both of the first and second major surfaces is heated to an annealing temperature. The selected region is then cooled below the annealing temperature, so that residual compressive stress is generated in the selected region. | 07-10-2014 |
20140334077 | CERAMIC COVER FOR ELECTRONIC DEVICE HOUSING - An electronic device having an enclosure formed from at least one ceramic cover and a peripheral structure adjacent the periphery of the ceramic cover is disclosed. The peripheral structure can be secured adjacent to the ceramic cover with an attachment member. The ceramic cover can include a recess to receive the attachment member. The peripheral structure can be molded adjacent the ceramic cover so that a gapless interface can be formed between the peripheral structure and the periphery of the ceramic cover. | 11-13-2014 |
20150163382 | COVER GLASS ARRANGEMENT FOR AN ELECTRONIC DEVICE - An electronic device can include a camera and a cover glass arrangement disposed over the camera. The cover glass arrangement includes a thinner region or cover glass that is positioned over a light-receiving region of the camera. Additionally, the thinner region or cover glass can be disposed over the light-receiving region and at least parts of one or more non-light receiving regions of the camera. | 06-11-2015 |
Patent application number | Description | Published |
20130053098 | MOUNTING AND CONFORMAL COATING SUPPORT STRUCTURE TO FLEX ASSEMBLY TO PREVENT TRACE AND COMPONENT CRACKING - A compact proximity sensor for use in a portable computing device is described. In particular various embodiments of a proximity sensor which fits in an extremely small portion of a cellular phone, and accurately determine the presence of a user's head in close proximity to a surface of the cellular phone. In particular, a high yield assembly process for installing the compact proximity sensor is described. | 02-28-2013 |
20140219646 | Electronic Device With Camera Flash Structures - An electronic device may contain a camera, a camera flash, and a display in a housing. The camera flash or the display may provide illumination while capturing images with camera. The camera flash may be formed from light guiding structures that receive camera flash light from a light source. The camera flash may be located under a speaker port mesh. A speaker port may contain a camera and a camera flash. Light guiding structures may have a ring shape with an opening. A speaker port, camera, or button may be located within the opening. A button may have an opaque portion in which a transparent light guiding structure for a camera flash is embedded. Camera flash structures may produce camera flash light to capture images and can serve as a status indicator to indicate when a message is received or other state change is detected during operation. | 08-07-2014 |
20150216024 | Electronic Devices Having Electrostatic Discharge Paths - An electronic device may have a display and other electrical components that are sensitive to electrostatic charge. A button may pass through an opening in a layer of the display. A metal trim may surround the button. The housing may have an opening with a clear lens surrounded by a metal trim. To prevent damage from electrostatic discharge, an electrostatic discharge path may be formed in the device that includes a metal trim surrounding a component such as a button member or camera lens, metal traces on the inner surface of a display layer or a housing, a grounded metal housing structure, and a spring or other conductive structure that couples the metal traces to the grounded metal housing structure. Displays may be provided with electrostatic discharge paths that route electrostatic charge to grounded metal housing structures. | 07-30-2015 |
20150255853 | Electronic Device With Display Frame Antenna - An electronic device has a display mounted in a housing using a plastic display frame. The display has an active area and an inactive area. A display cover layer may have polymer coating layers in the inactive area. The display frame may lie under the inactive area. A patterned metal coating layer may be formed on the display frame. The patterned metal coating layer may have portions that form adhesion promotion structures for promoting adhesion between the frame and the adhesive. The patterned metal coating layer may also have portions that form antenna structures. The antenna structures may be used to transmit and receive radio-frequency signals and may be used as adhesion promotion structures. Adhesive may be interposed between the polymer coating layers and the metal coating layer on the display frame to attach the display cover layer and the display to the display frame. | 09-10-2015 |
20160028931 | COVER GLASS ARRANGEMENT FOR AN ELECTRONIC DEVICE - An electronic device can include a camera and a cover glass arrangement disposed over the camera. The cover glass arrangement includes a thinner region or cover glass that is positioned over a light-receiving region of the camera. Additionally, the thinner region or cover glass can be disposed over the light-receiving region and at least parts of one or more non-light receiving regions of the camera. | 01-28-2016 |
20160037658 | ALUMINUM OXIDE CONTROL MECHANISM - A control mechanism comprises a housing defining an interior and an exterior, an aperture formed in the housing and extending from the interior to the exterior thereof, an actuator on the interior of the housing, proximate the control aperture, and a control member positionable within the aperture to operate the actuator. The control member comprises a first surface exposed to the exterior of the housing, a second surface proximate the actuator within the housing, and a body portion extending therebetween, the body portion being formed of a substantially single crystal aluminum oxide material. A bias member is configured to bias the body portion of the control member toward an inner surface of the housing, such that the control member is retained within the aperture in operation of the actuator. | 02-04-2016 |
Patent application number | Description | Published |
20100073070 | Low Voltage High-Output-Driving CMOS Voltage Reference With Temperature Compensation - A bandgap reference voltage generator has a first stage that generates a first current that is complementary-to-absolute-temperature (Ictat) and a second stage that generates a current that is proportional-to-absolute-temperature (Iptat). The Ictat and Iptat currents are both forced through a summing resistor to generate a voltage that is relatively independent of temperature, since the Ictat and Iptat currents cancel out each other's temperature dependencies. A PMOS output transistor drives current to an output load to maintain the load at the reference voltage. An op amp drives the gate of the PMOS output transistor and has inputs connected to emitters of PNP transistors in the second stage. A series of resistors generate the reference voltage between the PMOS output transistor and ground and drives bases of the PNP transistors and includes the summing resistor. Parasitic PNP transistors in an all-CMOS process are used. The generator operates with a 1-volt power supply. | 03-25-2010 |
20100148727 | Single-Power-Transistor Battery-Charging Circuit Using Voltage-Boosted Clock - A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor. | 06-17-2010 |
20100164770 | MULTI-STAGE COMPARATOR WITH OFFSET CANCELING CAPACITOR ACROSS SECONDARY DIFFERENTIAL INPUTS FOR HIGH-SPEED LOW-GAIN COMPARE AND HIGH-GAIN AUTO-ZEROING - An Analog-to-Digital Converter (ADC) has a Successive-Approximation-Register (SAR) driving a digital-to-analog converter (DAC) that generates an analog voltage compared to an input voltage by a series of stages. The last stage feeds a compare signal to the SAR. Each stage has a dual-input differential amplifier that operates as a unity gain op amp during an auto-zeroing phase and as a high-speed low-gain amplifier during an amplifying phase. The dual-input differential amplifier has two pairs of differential inputs. A secondary pair has an offset-storing capacitor across it, and connects to the output pair through feedback switches during auto-zeroing. A primary pair connects to stage inputs through input switches during the amplifying phase. Since two pairs of differential inputs are provided to the dual-input differential amplifier, the offset capacitor is completely isolated from the input pair. The current sink in the dual-input differential amplifier is adjusted higher during the amplifying period. | 07-01-2010 |
20100315748 | ESD Protection using a Capacitivly-Coupled Clamp for Protecting Low-Voltage Core Transistors from High-Voltage Outputs - An electro-static-discharge (ESD) protection circuit protects core transistors. An internal node to the gate of an n-channel output transistor connects to the drain of an n-channel gate-grounding transistor to ground. The gate of the gate-grounding transistor is a coupled-gate node that is coupled by an ESD coupling capacitor to the output and to ground by an n-channel disabling transistor and a leaker resistor. The gate of the n-channel disabling transistor is connected to power and disables the ESD protection circuit when powered. An ESD pulse applied to the output is coupled through the ESD coupling capacitor to pulse high the coupled-gate node and turn on the gate-grounding transistor to ground the gate of the n-channel output transistor, which breaks down to shunt ESD current. The ESD pulse is prevented from coupling through a parasitic Miller capacitor of the n-channel output transistor by the gate-grounding transistor. | 12-16-2010 |
20110216559 | Constant-Current Control Module using Inverter Filter Multiplier for Off-line Current-Mode Primary-Side Sense Isolated Flyback Converter - A fly-back AC-DC power converter has a constant-current control loop that senses the primary output current in a transformer to control the secondary output without an expensive opto-isolator. A primary-side control circuit can use either a Quasi-Resonant (QR) or a Pulse-Width-Modulation (PWM) control loop to switch primary current through the transformer on and off. A feedback voltage is compared to a primary-side voltage sensed from the primary current loop to turn the switch on and off. A multiplier loop generates the feedback voltage using a multiplier. A level-shift inverter and a low-pass filter act as the multiplier by multiplying an off duty cycle of the switch by the feedback voltage to generate a filtered voltage. A high-gain error amp compares the filtered voltage to a reference voltage to generate the feedback voltage. The multiplier produces a simple relationship between the secondary current and the reference voltage, yielding simplified current control. | 09-08-2011 |
20110267008 | Single-Power-Transistor Battery-Charging Circuit Using Voltage-Boosted Clock - A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor. | 11-03-2011 |
20120126736 | Bootstrapped High-Side Driver Control Without Static DC Current for Driving a Motor Bridge Circuit - A motor driver circuit for driving the gate node of a high-side driver transistor to a boosted voltage from a charge pump draws little or no static current from the charge pump. The gate node is pulled to the boosted voltage by a p-channel pullup-control transistor that is driven by p-channel transistors that are pumped by capacitors that cut off current flow to ground from the charge pump. An n-channel output-shorting transistor shorts the gate node to the output when the high-side driver is turned off. A coupling capacitor initializes the shorting transistor for each output transition. A p-channel output-sensing transistor generates a feedback to a second stage that drives the coupling capacitor. P-channel diode transistors and an n-channel equalizing transistor control the voltage on the coupling capacitor. | 05-24-2012 |
20120126901 | PROGRAMMABLE ELECTRO-MAGNETIC-INTERFERENCE (EMI) REDUCTION WITH ENHANCED NOISE IMMUNITY AND PROCESS TOLERANCE - A frequency dithering circuit reduces emissions that cause Electro-Magnetic Interference (EMI) by spreading the spectrum of a clock. The clock sequences a counter that drives a digital count value to a digital-to-analog converter (DAC). The DAC outputs a sawtooth wave with a wide voltage swing. A subtractor scales down the voltage swing to produce a reduced-swing sawtooth wave which is used as an upper limit voltage. Comparators trigger a set-reset latch to toggle the clock when current pumps charge and discharge a capacitor beyond voltage limits. Since the upper limit voltage is the reduced sawtooth wave from the subtractor, the amount of time to charge the capacitor varies, dithering the period of the clock. The degree of dithering can be adjusted by programming the feedback resistance in the subtractor. The subtractor reduces the sensitivity of dithering to errors in the DAC, allowing for an inexpensive, less precise DAC. | 05-24-2012 |
Patent application number | Description | Published |
20090134923 | ZERO-DELAY BUFFER WITH COMMON-MODE EQUALIZER FOR INPUT AND FEEDBACK DIFFERENTIAL CLOCKS INTO A PHASE-LOCKED LOOP (PLL) - A zero-delay clock generator has a phase-locked loop (PLL) that generates a feedback clock and receives a reference clocks. All clocks are differential and have a common-mode voltage. The common-mode voltage of an externally-generated reference clock can vary from the common-mode voltage of the internally-generated feedback clock. Differences in common-mode voltage of the reference clock and feedback clock cause delay variations resulting in static phase offsets of generated clocks. A common-mode sense and equalizer senses the common-mode voltages of the buffered reference and feedback clocks, and generates control voltages. The control voltages adjust the common-mode voltage and delay of differential buffers that receive the reference and feedback clocks. The control voltages adjust the differential buffers to match the common-mode voltages of the buffered reference and feedback clocks. The buffered clocks are then applied to a phase and frequency detector of the PLL. | 05-28-2009 |
20100164625 | Slew-Rate-Enhanced Error Amp with Adaptive Transconductance and Single Dominant Pole Shared by Main and Auxiliary Amps - An error amplifier can be used to control a power regulator transistor. The error amplifier has a main amplifier, a pull-up auxiliary amplifier, and a pull-down auxiliary amplifier that all drive an output. A compensating capacitor on the output sets a single dominant pole for all amplifiers, increasing stability. High slew rates are provided by increased slew current from the auxiliary amplifiers that turn on when the differential input has an absolute voltage difference larger than an intentional offset. The intentional offset is introduced into the auxiliary amplifiers by adjusting a p-channel to n-channel transistor ratio in a leg of the auxiliary amplifiers. A source degenerated resistor in the main amplifier reduces supply headroom and increases linearity by connecting sources of two differential transistors that receive the differential input. Cascode transistors increase gain and output impedance. Reliability is increased as no positive feedback is used in the amplifiers. | 07-01-2010 |
20100164761 | DUAL-USE COMPARATOR/OP AMP FOR USE AS BOTH A SUCCESSIVE-APPROXIMATION ADC AND DAC - A re-configurable circuit acts as an Analog-to-Digital Converter (ADC) and as a digital-to-analog converter (DAC). An array of binary-weighted capacitors stores an analog input. Switches connect different capacitors in the array to fixed voltages that cause charge-sharing with a terminal capacitor. The voltage of the terminal capacitor is compared by a re-configurable comparator stage for each different combination of the capacitors. The comparison results are analyzed to determine the closest digital value for the analog input. In DAC mode, the array capacitors are switched based on an input digital value. The switched capacitors connect to a charge-sharing line to generate an analog voltage that is applied to the re-configurable comparator stage. A differential amplifier generates a buffered analog voltage that is fed back to the other input of the re-configurable comparator stage for unity gain. The gain of the re-configurable comparator stage adjusts for ADC and DAC modes. | 07-01-2010 |
20110163799 | Bi-directional Trimming Methods and Circuits for a Precise Band-Gap Reference - A bandgap reference circuit has trimming-up resistors and trimming-down resistors for bi-directional trimming. PNP transistors have base and collectors grounded and emitters connected to parallel resistors. A difference resistor drives an inverting input of an op amp that drives a transistor that generates the bandgap reference voltage Vbg. A sensing resistor connects Vbg to a splitting node that connects to the non-inverting input through a first parallel resistor. The splitting node also connects through a second parallel resistor to the inverting input. Fuses or switches enable the trimming-up and trimming-down resistors. The trimming-up resistors are in series with the sensing resistor and the trimming-down resistors are in series with an output resistor that connects Vbg to reference voltage Vref. The circuit can be designed for a more typical process since bi-directional trimming allows Vref to be raised or lowered. Many circuits need no trimming when targeted for the typical process. | 07-07-2011 |
20110221938 | Optical Black-Level Cancellation for Optical Sensors Using Open-Loop Sample Calibration Amplifier - A Optical Black Pixel (OBP) cancellation circuit corrects offsets in sensors in a CCD/CMOS image sensor when reading dark pixels such at the periphery. A pixel voltage is switched to a sampling capacitor during two phases of the same pixel pulse. Sampling capacitors and feedback capacitors connect to differential inputs of an amplifier. An accumulating capacitor accumulates voltage differences and generates a common-mode voltage that is fed back to another sampling capacitor that stores an amplifier offset. The sampling capacitor and accumulating capacitor and their associated switches form a discrete-time first-order low-pass filter that filters the pixel voltage during the first phase. In the second phase the amplifier acts as a unity-gain amplifier to output an average of the pixel voltage differences generated during an OBP time when blackened or covered pixels are read from the image sensor. | 09-15-2011 |
20130049628 | Current-Switching LED Driver Using DAC to Ramp Bypass Currents to Accelerate Switching Speed and Reduce Ripple - A light-emitting diode (LED) driver provides faster rise and fall times for LED current to reduce image sticking and other interference. A standard DC-DC converter provides a sum current that is slowly ramped up and down by a bypass current digital-to-analog converter (DAC). A digital value to the bypass current DAC is ramped up or down before an LED current is turned on or off. When the LED current is turned on, current is shifted from a bypass path to a path through the LED, maintaining a constant sum current from the DC-DC converter. When a different LED is turned on, current is shifted from one LED's path to the other LED's path. Separate LED current DAC's in each LED path and in the bypass path can share the sum current with digital precision. Using a single DAC for the sum current and switches in each path reduces cost. | 02-28-2013 |
20130235903 | CMOS Temperature Sensor with Sensitivity Set by Current-Mirror and Resistor Ratios without Limiting DC Bias - An on-chip temperature sensor circuit can be implemented in a standard complementary metal-oxide-semiconductor (CMOS) process using PNP transistors. A pair of transistors have collector currents that are sensitive to voltage, both directly and due to saturation currents. A scaling resistor connects to the emitter of one transistor and its voltage compared to the other transistor's emitter voltage by an error amplifier that generates a bias voltage to current sources that are proportional to absolute temperature since the saturation current sensitivity is subtracted out. The current is mirrored to sink current through a multiplier resistor from an output. An amplifier connected across the multiplier resistor compares a reference voltage to set the DC bias independent of temperature sensitivity. The temperature sensitivity is proportional to the ratio of the multiplier resistor and the scaling resistor, and is multiplied by a mirroring factor. A differential output may also be provided. | 09-12-2013 |
20140104909 | Diode-Less Full-Wave Rectifier for Low-Power On-Chip AC-DC Conversion - A bridge rectifier operates on low A.C. input voltages such as received by a Radio-Frequency Identification (RFID) device. Voltage drops due to bridge diodes are avoided. Four p-channel transistors are arranged in a transistor bridge across the A.C. inputs to produce an internal power voltage. Another four diode-connected transistors form a start-up diode bridge that generates a comparator power voltage and a reference ground. The start-up diode bridge operates even during initial start-up before the comparator and boost drivers operate. A comparator receives the A.C. input and controls timing of voltage boost drivers that alternately drive gates of the four p-channel transistors in the transistor bridge with voltages boosted higher than the peak A.C. voltage. Substrates are connected to the power voltage on the power-voltage half of the bridge and to the A.C. inputs on the ground half of the bridge to fully shut off transistors, preventing reverse current flow. | 04-17-2014 |
20140104910 | Self-Starting Transistor-Only Full-Wave Rectifier for On-Chip AC-DC Conversion - A transistor-based full-wave bridge rectifier is suitable for low A.C. input voltages such as received by a Radio-Frequency Identification (RFID) device. Voltage drops due to bridge diodes are avoided. Four p-channel transistors are arranged in a bridge across the A.C. inputs to produce an internal power voltage. A comparator receives the A.C. input and controls timing of voltage boost drivers that alternately drive gates of the four p-channel transistors with voltages boosted higher than the peak A.C. voltage. Four diode-connected transistors are connected in parallel with the four p-channel bridge transistors to conduct during initial start-up before the comparator and boost drivers operate. Substrates are connected to the power voltage on the power-voltage half of the bridge and to the A.C. inputs on the ground half of the bridge to fully shut off transistors, preventing reverse current flow. The transistor bridge can be integrated onto system chips. | 04-17-2014 |
20140362887 | Differential Temperature Sensor with Sensitivity Set by Current-Mirror and Resistor Ratios without Limiting DC Bias - A differential on-chip temperature sensor circuit can be implemented in a standard complementary metal-oxide-semiconductor (CMOS) process using PNP transistors. A pair of transistors have collector currents that are sensitive to voltage, both directly and due to saturation currents. A scaling resistor connects to the emitter of one transistor and its voltage compared to the other transistor's emitter voltage by an error amplifier that generates a bias voltage to current sources that are proportional to absolute temperature since the saturation current sensitivity is subtracted out. The current is mirrored to sink current through a multiplier resistor from an output. An amplifier connected across the multiplier resistor compares a reference voltage to set the DC bias independent of temperature sensitivity. The temperature sensitivity is proportional to the ratio of the multiplier resistor and the scaling resistor, and is multiplied by a mirroring factor. A differential output is provided. | 12-11-2014 |
20150380959 | Serial Multi-Battery Charger with Independent Simultaneous Charge and Discharge - A serial battery charger has a battery matrix with switches that are configured by a microcontroller that reads voltages between batteries to determine if each battery is fully-charged, charging, or absent. A switch configuration allows charging and discharging currents to flow simultaneously, and allows discharging current but blocks charging current from fully-charged batteries to prevent over-charging. The charging current flows through all charging batteries in series while the discharging current flows from all fully-charged and charging batteries in series. Blocking and bypass switches route the charging current to all charging batteries in series, but bypass all fully-charged and absent batteries. The blocking and bypass switches route the discharging current serially through all fully-charged and charging batteries in the battery matrix while avoiding absent batteries. The switches are controlled by the switch configuration from the microcontroller. Larger battery matrixes have row and column lines that are connected by connecting switches. | 12-31-2015 |
20150381054 | LED Driver with Small Output Ripple Without Requiring a High-Voltage Primary-Side Electrolytic Capacitor - A power converter reduces output ripple without using an electrolytic primary-side capacitor that can reduce product lifetime. Primary-Side Regulation (PSR) using an auxiliary winding provides a regulated secondary voltage with some low-frequency ripple on a secondary winding of a transformer. A smaller secondary capacitor that is not an electrolytic capacitor filters the output of the secondary side. A bang-bang controller controls the secondary side current to reduce current ripple despite voltage ripple. The bang-bang controller has a series resistor and inductor in series with a load such as an LED. A voltage drop across the series resistor increases when a switch turns on. This increasing voltage drop toggles the switch off once an upper limit voltage is reached. The voltage drop then decreases as inductor current is shunted by a diode, until the voltage drop reaches a lower limit voltage and the switch toggles on again. | 12-31-2015 |
Patent application number | Description | Published |
20110022623 | SYSTEM AND METHOD FOR INFLUENCING A POSITION ON A SEARCH RESULT LIST GENERATED BY A COMPUTER NETWORK SEARCH ENGINE - A system and method for enabling information providers using a computer network such as the Internet to influence a position for a search listing within a search result list generated by an Internet search engine. The system and method of the present invention provides a database having accounts for the network information providers. Each account contains at least one search listing having at least three components: a description, a search term comprising one or more keywords, and a bid amount. The network information provider may add, delete, or modify a search listing after logging into his or her account via an authentication process. The network information provider influences the position for a search listing through a continuous online competitive bidding process. The bidding process occurs when the network information provider enters a new bid amount, which is preferably a money amount, for a search listing. The system then compares this bid amount with all other bid amounts for the same search term, and generates a rank value for all search listings having that search term. The rank value generated by the bidding process determines where the network information providers listing will appear on the search results list page that is generated in response to a query of the search term by a searcher located at a client computer on the computer network. A higher bid by a network information provider will result in a higher rank value and a more advantageous placement. | 01-27-2011 |
20130346190 | SYSTEM AND METHOD FOR INFLUENCING A POSITION ON A SEARCH RESULT LIST GENERATED BY A COMPUTER NETWORK SEARCH ENGINE - The present application is related to systems and methods for enabling information providers to influence a position for a search listing within a search result list generated by an Internet search engine. The systems and methods may provide accounts for the network information providers. Each account may contain a search listing having at least three components: a description, a search term comprising one or more keywords, and a bid amount. The network information provider may add, delete, or modify a search listing to influence the position for a search listing within a corresponding search result list. The systems and methods may send a notification to an external destination upon occurrence of a predetermined event, such as the change of position in the search listing. | 12-26-2013 |