Patent application number | Description | Published |
20090157880 | MANAGEMENT SYSTEM FOR QUALITY OF SERVICE IN HOME NETWORK - There is provided a QoS (quality of service) management system in a home network. When a QoS service is provided in the home network consisting of hosts and bridges, a user provides a user identifier and authentication information and the QoS management system verifies the user identifier and authentication information when managing a user policy and providing a service, to provide a consistent and stable policy within the home network, to prevent a collision among different policies, and to prevent the home network resources from being used by an illegal user. | 06-18-2009 |
20100135308 | INTEGRATED GATEWAY APPARATUS AND COMMUNICATIONS METHOD - An integrated gateway apparatus includes a policy storage for storing therein a first information on message filtering and switching policies for messages received from heterogeneous devices in lower networks via network interfaces; a device management unit for extracting a second information on the messages, the devices and the network interfaces; a layer-basis filter unit for performing, based on the first and the second information, the message filtering and switching on the messages on a layer basis; and an integrated switch management unit for providing the first information to the layer-basis filter unit and controlling the layer-basis filtering unit. The layer-basis filter unit includes a switch filter unit, a route filter unit and a gateway filter unit for performing the message filtering and switching in a MAC layer, in a network layer and a transport layer and in an application layer, respectively. | 06-03-2010 |
20100138550 | SHIP-BORNE DEVICE MANAGING METHOD - A ship-borne device managing method includes allocating IP address information to a device when a device configuration information request message is received from the device through a network in a ship system; performing an overlapping test of checking whether the allocated IP address information is currently used in the device; allocating service session information necessary for provision of an application service regarding the device in case where the overlapping test determines that the allocated IP address information is not currently used by the device; and generating a device configuration information response message based on the allocated IP address information and service session information and transmitting the device configuration information response message to the device. The device configuration information request message may include information regarding the device in the form of text or binary. | 06-03-2010 |
20100161161 | APPARATUS FOR INTEGRALLY MANAGING SHIP DEVICE AND METHOD THEREOF - An apparatus for integrally managing a ship includes a device manager for integrally managing different types of local ship devices in the ship by using a standardized protocol message; a local device manager for managing local ship devices in a legacy environment on the basis of an independent local protocol; and an inter-working framework (IWF) for performing translation of a protocol for compatibility between the standardized protocol and the independent local protocol to manage the different types of local ship devices between the device manager and the local device manager. The device manager receives a remote control instruction for remotely maintaining and repairing the local ship device from a remote server connected through a wired/wireless communication network. | 06-24-2010 |
20110038369 | COMMUNICATION METHOD AND APPARATUS BASED ON USER DATAGRAM PROTOCOL - A communication method based on user datagram protocol (UDP) in a transmitter includes: segmenting a message provided thereto into packets of a predetermined size; allocating a serial number to each of the segmented packets; storing the segmented packets in a packet buffer to transmit the packets to a receiver in order of the allocated serial numbers; and waiting for a control message indicating packet receipt completion from the receiver. The communication method based on UDP in a receiver includes: receiving packets segmented by a predetermined size in order of serial numbers from a transmitter; and when the received segmented packets are message packets and there is no missing packet, assembling the segmented packets in order of the serial numbers to complete a message. | 02-17-2011 |
20120166559 | VESSEL AND LAND MESSENGER SERVICE APPARATUS AND METHOD USING VESSEL MAINTENANCE SERVICE - A vessel messenger service apparatus includes: a vessel messenger service unit for providing messenger service between vessel, converting a local message from a vessel client into a global message to be transmitted to a land client, converting a message generated from the land client into a local message and providing the converted local message to the vessel client; and a vessel maintenance service unit for providing a remote vessel maintenance service and a messenger service between the vessel client and the land client by interworking with a unified vessel maintenance service unit on land. The apparatus further includes a database managing unit for managing information for the vessel client and the land client. | 06-28-2012 |
20140129701 | APPARATUS FOR MANAGING SHIP NETWORK - An apparatus for stably controlling and managing a ship network, which is capable of analyzing traffic characteristics of various marine devices having different properties in the ship network covering the various marine devices and switch equipments, allocating suitably network resources to the marine devices depending on the analyzed traffic characteristics, and managing exceptional situations by monitoring the generation of the situations. | 05-08-2014 |
20140304385 | METHOD FOR PROVIDING INTERWORKING SERVICE IN HOME NETWORK - A method provides an interworking service in a home network. In view of the above, the present invention provides a method for providing an interworking service in a home network, in which servers and adaptors existing in a home network can identify with each other and servers or adaptors are not doubly connected to a device. | 10-09-2014 |
Patent application number | Description | Published |
20100228932 | METHOD OF TRANSFERRING AND ALIGNING OF INPUT DATA AND MEMORY DEVICE USING THE SAME - A method of transferring input data is disclosed. In one embodiment, during a burst having a burst length of N, the method comprises transferring to a memory device data for each of a plurality of unit intervals (UIs) of the burst through a plurality of terminals, wherein each of the transfers includes D bits of input data and at least some of the input data is to be written to the memory device. The method further comprises transferring to the memory device mask data during the burst as part of the input data, the mask data occupying at least two UIs, and transferring to the memory device content data during the burst as part of the input data, wherein the mask data transferred during each of the at least two UIs has the same value. | 09-09-2010 |
20120112799 | TRANSMITTER HAVING SOURCE FOLLOWER VOLTAGE REGULATOR - A transmitter suitable for signal driving of a semiconductor device includes a driving power voltage generator and an output driver. The driving power voltage generator includes an NMOS transistor having a drain connected with a first voltage supply terminal, a gate connected to receive a second voltage lower than a voltage of the first voltage supply terminal, and a source outputting an output driving voltage and configured to perform source follower voltage regulating. | 05-10-2012 |
20120113732 | PSEUDO-OPEN DRAIN TYPE OUTPUT DRIVER HAVING DE-EMPHASIS FUNCTION, SEMICONDUCTOR MEMORY DEVICE, AND CONTROL METHOD THEREOF - A semiconductor memory device includes a memory cell array, an output driver having a pseudo-open drain (POD) structure and providing read data from the memory cell array in a de-emphasis mode, and control logic controlling the output driver in response to a read command to activate the de-emphasis mode. The control logic activates the de-emphasis mode only during an output period during which the read data is output by the output driver. | 05-10-2012 |
20130223156 | NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A program method is provided for a nonvolatile memory device, including a substrate and multiple memory cells formed in a pocket well in the substrate. The program method includes supplying a program voltage to a selected word line during a program execution period of a program loop, supplying a verification voltage to the selected word line during a verification period of the program loop, and supplying a negative voltage to the pocket well as a well bias voltage during the verification period. | 08-29-2013 |
Patent application number | Description | Published |
20090100285 | Internal Clock Signal Generating Circuits Including Frequency Division and Phase Control and Related Methods, Systems, and Devices - An integrated circuit device may include a main clock signal input pad configured to receive a main clock signal having a main clock frequency, a high speed clock signal input pad configured to receive a high speed clock signal having a high speed clock frequency greater than the main clock frequency, a frequency divider, and a phase controller. The frequency divider may be configured to generate a plurality of preliminary internal clock signals responsive to the high speed clock signal wherein each of the preliminary internal clock signals has the same main clock frequency and a different phase. The phase controller may be configured to select one of the preliminary internal clock signals having a phase most closely matched with a phase of the main clock signal, and to translate the preliminary internal clock signals to internal clock signals so that the preliminary internal clock signal having the phase most closely matched with the phase of the main clock signal is translated as a primary internal clock signal, so that the internal clock signals have the main clock frequency. Related methods, systems, and devices are also discussed. | 04-16-2009 |
20090154256 | Integrated Circuit Memory Devices Including Delayed Clock Inputs for Input/Output Buffers and Related Systems and Methods - A memory system may include an integrated circuit memory device and a memory controller coupled to the integrated circuit memory device. The integrated circuit memory device may include a memory cell array having a plurality of memory cells, a clock generator configured to generate a clock signal, a plurality of data input/output buffers, and a delay circuit. The plurality of data input/output buffers may be coupled between respective data input/output pads and the memory cell array, and each of the data input/output buffers may be configured to communicate data with the memory cell array responsive to the clock signal with the clock signal being applied to a clock input of each of the input/output buffers. The delay circuit may be coupled between the clock generator and a first one of the data input/output buffers so that the clock signal is delayed by different amounts at clock inputs of the first data input/output buffer and a second one of the data input/output buffers. Moreover, the memory controller may be configured to perform data training. Related methods and memory devices are also discussed. | 06-18-2009 |
20090179700 | AC Coupling Circuits Including Resistive Feedback and Related Methods and Devices - An integrated circuit device may include an amplifier having an amplifier input configured to receive an input signal with the amplifier being configured to provide an amplifier output signal at an amplifier output responsive to the input signal received at the amplifier input. A capacitor may be coupled to the amplifier output, and a buffer may be coupled to the capacitor so that the capacitor is coupled in series between the amplifier output and an input of the buffer with an output of the buffer being coupled to a buffered signal terminal. A variable resistive feedback circuit may be coupled between the input and output of the buffer with the variable resistive feed back circuit providing a variable resistance between the input and output of the buffer. A feedback resistance controller may be coupled to the variable resistive feedback circuit with the feedback resistance controller being configured to select a first resistance for the variable resistive feedback circuit for a first frequency of the input signal and to select a second resistance for the variable resistive feedback circuit for a second frequency of the input signal different than the first frequency with the first and second resistances being different. | 07-16-2009 |