Patent application number | Description | Published |
20120044398 | CMOS SENSOR WITH LOW PARTITION NOISE AND LOW DISTURBANCE BETWEEN ADJACENT ROW CONTROL SIGNALS IN A PIXEL ARRAY - A CMOS image sensor includes a pixel array including a plurality of unit pixels with individual rows of unit pixels being coupled to respective row control signal lines, and a buffer including plural row control signal drivers. Each driver is coupled to a respective one of the row control signal lines and is configured to provide a row control signal pulse to a respective row control signal line in response to an input pulse when the row control signal line is in an active state and to bias the row control signal line at a ground voltage when the respective row control signal line is in an inactive state. Each driver has a first drive capability when the row control signal line is in the active state and a second drive capability greater than the first drive capability when the row control signal line is in an inactive state. | 02-23-2012 |
20120098975 | COLOR IMAGE SENSOR ARRAY WITH COLOR CROSSTALK TEST PATTERNS - An integrated circuit comprises a semiconductor substrate and a color image sensor array on the substrate. The color image sensor array has a first configuration of color pixels for collecting color image data, and at least one crosstalk test pattern on the substrate proximate the color image sensor array. The crosstalk test pattern includes a plurality of color sensing pixels arranged for making color crosstalk measurements. The test pattern configuration is different from the first configuration. | 04-26-2012 |
20130113958 | COLOR IMAGE SENSOR ARRAY WITH COLOR CROSSTALK TEST PATTERNS - An integrated circuit comprises a semiconductor substrate and a color image sensor array on the substrate. The color image sensor array has a first configuration of color pixels for collecting color image data, and at least one crosstalk test pattern on the substrate proximate the color image sensor array. The crosstalk test pattern includes a plurality of color sensing pixels arranged for making color crosstalk measurements. The test pattern configuration is different from the first configuration. | 05-09-2013 |
20130228671 | CMOS SENSOR ARRAY - A CMOS sensor includes a pixel configured to output a voltage based on incident light received by the pixel. A first circuit is coupled to the pixel and is configured to determine a reset voltage of the pixel. A second circuit is coupled to the first circuit and is configured to select a gain level based on the reset voltage of the pixel. A gain circuit is coupled to the second circuit and is configured to set a voltage level of the gain selected by the second circuit. | 09-05-2013 |
20130271626 | METHOD OF REDUCING COLUMN FIXED PATTERN NOISE - A method of reducing column fixed pattern noise including calibrating a readout circuit, wherein the readout circuit is electrically connected to at least one programmable gain amplifier and an analog-to-digital converter. Calibrating the readout circuit includes electrically disconnecting the readout circuit from a pixel output and electrically connecting a pixel reset input of the readout circuit to a pixel output signal input of the readout circuit. Calibrating the readout circuit further includes comparing a measured output of the readout circuit to a predetermined value and storing the comparison result in a non-transitory computer readable medium. The method further includes operating the readout circuit, the operating the readout circuit includes receiving a pixel sample signal and outputting a calibrated output based on an operating output and the stored comparison result. | 10-17-2013 |
20140042303 | CMOS SENSOR WITH LOW PARTITION NOISE AND LOW DISTURBANCE BETWEEN ADJACENT ROW CONTROL SIGNALS IN A PIXEL ARRAY - A CMOS image sensor includes a pixel array including a plurality of unit pixels with individual rows of unit pixels being coupled to respective row control signal lines, and a buffer including plural row control signal drivers. Each driver is coupled to a respective one of the row control signal lines and is configured to provide a row control signal pulse to a respective row control signal line in response to an input pulse when the row control signal line is in an active state and to bias the row control signal line at a ground voltage when the respective row control signal line is in an inactive state. Each driver has a first drive capability when the row control signal line is in the active state and a second drive capability greater than the first drive capability when the row control signal line is in an inactive state. | 02-13-2014 |
20140077057 | 3D-STACKED BACKSIDE ILLUMINATED IMAGE SENSOR AND METHOD OF MAKING THE SAME - A stacked image sensor and method for making the same are provided. The stacked image sensor includes an upper chip with a pixel array thereon. The second chip includes a plurality of column circuits and row circuits associated with the columns and rows of the pixel array and disposed in respective column circuit and row circuit regions that are arranged in multiple groups. Inter-chip bonding pads are formed on each of the chips. The inter-chip bonding pads on the second chip are arranged linearly and are contained within the column circuit regions and row circuit regions in one embodiment. In other embodiments, the inter-chip bonding pads are staggered with respect to each other. In some embodiments, the rows and columns of the pixel array include multiple signal lines and the corresponding column circuit regions and row circuit regions also include multiple inter-chip bonding pads. | 03-20-2014 |
20140184316 | BIAS CONTROL - One or more techniques or systems for bias control are provided herein. In some embodiments, the bias control relates to biasing of a column of one or more pixels for an image sensor. In some embodiments, an associated circuit includes a reset transistor, a source-follower transistor, a first transfer transistor, a first bias transistor, a second bias transistor, and a switch connected to the second bias transistor. In some embodiments, the first bias transistor and the second bias transistor bias a column of pixels at a first time. In some embodiments, the second bias transistor is turned off, thus removing a second bias at a second time. In this way, performance of the image sensor is improved, at least because the second bias transistor enables faster settling time when active, and a wide pixel operation range when switched off. | 07-03-2014 |
20140217263 | IMAGE SENSOR CONFIGURED TO REDUCE BLOOMING DURING IDLE PERIOD - Among other things, techniques and systems are provided for identifying when a pixel of an image sensor is in an idle period. A flag is utilized to differentiate when the pixel is in an idle period and when the pixel is in an integration period. When the flag indicates that the pixel is in an idle period, a blooming operation is performed on the pixel to reduce an amount of electrical charge that has accumulated at the pixel or to mitigate electrical charge from accumulating at the pixel. In this way, the blooming operation reduces a probability that the photosensitive sensor becomes saturated during an idle period of the pixel, and thus reduces the likelihood of electrical charge from a pixel that is not intended contribute to an image from spilling over and potentially contaminating a pixel that is intended to contribute to the image. | 08-07-2014 |
20140217265 | CMOS SENSOR ARRAY - A CMOS sensor includes a pixel configured to output a voltage based on incident light received by the pixel. Circuitry is coupled to the pixel and is configured to determine a reset voltage of the pixel and to select a gain level based on the reset voltage of the pixel. A gain circuit is coupled to the circuitry and is configured to set a voltage level of the gain selected by the circuitry. | 08-07-2014 |
20140252202 | COLUMN ANALOG-TO-DIGITAL CONVERTER FOR CMOS SENSOR - A system and method is disclosed for an imaging device and/or an analog to digital converter which converts an analog input signal to a digital data signal using a comparator which compares the analog input signal to a first ramped reference signal to determine an operating point and then uses the same comparator to compare the analog input signal to a second ramped reference signal multiple times about the determined operating point. | 09-11-2014 |
20140266831 | LOW GLITCH CURRENT DIGITAL-TO-ANALOG CONVERTER - The present disclosure relates to a method and architecture to minimize a transient glitch within a current digital-to-analog converter (DAC) comprising an array of identical current unit cells. The current DAC is configured with individual column decoders for even and odd rows of current unit cells, thus allowing for independent control of adjacent rows. The even row and odd row column decoders further comprise thermal decoders with coupled timing encoding which establishes synergy between an adjacent pair of rows. As current units cells within an active row are activated across the row by a counting up of a first column decoder, the current units cells within a next row adjacent the active row are returned to an initial state of the active row by counting down in a second column decoder. Other devices and methods are also disclosed. | 09-18-2014 |
20140266991 | Systems and Methods to Mitigate Transient Current for Sensors - A sensor system includes a pixel array, column units and a compensation circuit. The pixel array is configured to provide pixel column data. The column units are configured to generate an offset data out signal from the pixel column data. The offset data out signal includes digital offsets. The compensation circuit is configured to remove the digital offsets from the offset data out signal. The compensation circuit is also configured to generate a data out signal. | 09-18-2014 |
20140347535 | APPARATUS WITH CALIBRATED READOUT CIRCUIT - An apparatus comprises a readout circuit configured to be disconnected from a pixel output, and to connect a pixel reset signal received by the readout circuit to a pixel output signal received by the readout circuit. The apparatus also comprises at least one programmable gain amplifier coupled with the readout circuit. The apparatus further comprises an analog-to-digital converter coupled with the programmable gain amplifier. The readout circuit is configured to be calibrated based on a comparison of a measured output of the readout circuit to a predetermined value, the predetermined value being equal to (2 | 11-27-2014 |