Kuo, Hsin-Chu
Chang-Fu Kuo, Hsin-Chu TW
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20110116578 | Mobile Communication System with Integrated GPS Receiver - A receiver includes a mixer, a poly phase filter, a channel select filter, an analog-to-digital converter and a HI/LO side reject selection unit. The mixer downconverts a signal to generate an in-phase signal and a quadrature signal. The poly phase filter for generates differential IF signals based on the in-phase signal and the quadrature signal. The channel select filter filters out unwanted channel signals from the differential IF signals. The analog-to-digital converter converts the filtered signal into a digital output signal. The HI/LO side reject selection unit is coupled between the mixer and the poly phase filter and capable of rejecting image signals while the mixer is at a high side frequency or at a low side frequency. | 05-19-2011 |
Che-Cheng Kuo, Hsin-Chu TW
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20120044160 | Touch Panel and Peripheral Circuit Thereof - A touch panel and a peripheral circuit thereof are provided. Each bonding pad of the peripheral circuit includes a first conductive layer, a first protective layer, a second conductive layer, and a second protective layer sequentially arranged on a substrate from bottom to top. A covered area of the second conductive layer provided by the second protective layer is increased to cover a portion of the second conductive layer located above a junction area between the first protective layer and a terminal part of the first conductive layer, thereby increasing the reliability of the bonding pads. | 02-23-2012 |
Chen-Cheng Kuo, Hsin-Chu TW
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20160079192 | Metal Routing Architecture for Integrated Circuits - A device includes a substrate, a metal pad over the substrate, and a metal trace electrically disconnected from the metal pad. The metal pad and the metal trace are level with each other. A passivation layer includes a portion overlapping an edge portion of the metal pad. A metal pillar is overlying the metal pad, and is electrically connected to the metal pad. The metal trace has a portion overlapped by the metal pillar. | 03-17-2016 |
Chia-Hao Kuo, Hsin-Chu TW
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20140168138 | TOUCH PANEL AND TOUCH DISPLAY PANEL - A touch panel includes first sensing pads, first bridge lines, second sensing pads, adjusting electrodes, second bridge lines and third bridge lines. The first sensing pad has a first opening. The first sensing pads and the first bridge lines are arranged alternately along a first direction and electrically connected to each other. The second sensing pads and the second bridge lines are arranged alternately along a second direction and electrically connected to each other. The adjusting electrodes are disposed in the first openings and the second openings, and the adjusting electrodes are electrically disconnected from the first sensing pads and the second sensing pads. Adjacent adjusting electrodes are electrically connected through the third bridge line. The first sensing pads, the second sensing pads and the adjusting electrodes are made of a same patterned conductive layer. | 06-19-2014 |
Chia-Wei Kuo, Hsin-Chu TW
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20140104547 | PIXEL STRUCTURE OF TRANSPARENT LIQUID CRYSTAL DISPLAY PANEL - A pixel structure of transparent LCD panel includes a pixel, a pixel electrode and liquid crystal molecules. The pixel consists of a first alignment region and a second alignment region having different aligning directions. The pixel electrode includes a main electrode disposed between the first alignment region and the second alignment region, and branch electrodes. The main electrode is a bar-shaped electrode. A portion of the branch electrodes are connected to one side of the main electrode and extending along a first direction to the first alignment region, another portion of the branch electrodes are connected to the other side of the main electrode and extending along a second direction to the second alignment region. The first direction and the second direction are opposite and parallel, the an included angle between the first direction and the gate line is between 45±10 degrees. | 04-17-2014 |
20140369072 | Transparent Display Apparatus - A transparent display apparatus is provided. The display apparatus includes a plurality of white sub-pixels and a plurality of color sub-pixels that are mixedly arranged. The display apparatus also includes a control module for controlling the white sub-pixels and the color sub-pixels. When the display apparatus is in a transparent mode, the control module reduces or stops light emitting from the color sub-pixels and allows at least a part of ambient light behind the white sub-pixels to emit from the white sub-pixels to achieve the see-through effect. When the display apparatus is in a display mode, the control module adjusts at least one of the white or color sub-pixels to ensure that light from the white sub-pixels is far less than light from the color sub-pixels. | 12-18-2014 |
20150192727 | DISPLAY APPARATUS - A display apparatus includes a display panel, a light guide plate, at least one light source and at least one reflective body. The light guide plate is disposed below the display panel. The light guide plate has a light-incident surface, a light-emitting surface, a rear surface, a plurality of concave microstructures and a plurality of reflective bodies. The rear surface is located farther away from the display panel than the light-emitting surface is. The light-incident surface is connected to the light-emitting surface and the rear surface. The concave microstructures are located on the rear surface. The reflective bodies are respectively located in the concave microstructures. The light source is disposed opposite to the light-incident surface. | 07-09-2015 |
Chien-Chih Kuo, Hsin-Chu TW
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20090282374 | Dummy Pattern Design for Reducing Device Performance Drift - A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region having a first edge and a second edge perpendicular to each other; and adding stress-blocking dummy diffusion regions throughout the chip, which includes adding a first stress-blocking dummy diffusion region adjacent and substantially parallel to the first edge of the dummy-forbidden region; and adding a second stress-blocking dummy diffusion region adjacent and substantially parallel to the second edge of the dummy-forbidden region. The method further includes, after the step of adding the stress-blocking dummy diffusion regions throughout the chip, adding general dummy diffusion regions into remaining spacings of the chip. | 11-12-2009 |
20110204449 | Dummy Pattern Design for Reducing Device Performance Drift - A method of forming an integrated circuit structure on a chip includes extracting an active pattern including a diffusion region; enlarging the active pattern to form a dummy-forbidden region having a first edge and a second edge perpendicular to each other; and adding stress-blocking dummy diffusion regions throughout the chip, which includes adding a first stress-blocking dummy diffusion region adjacent and substantially parallel to the first edge of the dummy-forbidden region; and adding a second stress-blocking dummy diffusion region adjacent and substantially parallel to the second edge of the dummy-forbidden region. The method further includes, after the step of adding the stress-blocking dummy diffusion regions throughout the chip, adding general dummy diffusion regions into remaining spacings of the chip. | 08-25-2011 |
20160055817 | PANEL DRIVING CIRCUIT, BOOSTER CIRCUIT FOR LIQUID CRYSTAL PIXEL DATA AND DRIVING METHOD THEREOF - A booster circuit for liquid crystal pixel data includes first, second and third signal control switches and a first storage capacitor. The first signal control switch is ON through a driving of a first control pulse and electrically coupled to a data voltage. The second signal control switch is ON through a driving of the first control pulse and electrically coupled to a reference voltage. The third signal control switch is ON through a driving of a second control pulse and electrically coupled to the data voltage. The first storage capacitor includes two terminals. The first storage capacitor has its first terminal electrically coupled to the reference voltage through the second signal control switch and electrically coupled to the data voltage through the third signal control switch and its second terminal electrically coupled to the data voltage through the first signal control switch and for providing an output voltage. | 02-25-2016 |
Chih-Che Kuo, Hsin-Chu TW
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20120313978 | DRIVING METHOD USING PHASE DIFFERENCE TO CONTROL LUMINANCE OF FIELD EMISSION STRUCTURE AND DISPLAY APPARATUS USING THE SAME - A driving method for a field emission structure including at least a pixel, each including a first emitter, a second emitter, a first electrode utilized to control the first emitter, and a second electrode utilized to control the second emitter, includes: receiving a first control signal and a second control signal; and controlling the first emitter and the second emitter according to the first control signal and the second control signal, wherein when the first control signal and the second control signal have a first phase difference, electrons emitted by the first emitter and the second emitter have a first intensity, and when the first control signal and the second control signal have a second phase difference different from the first phase difference, electrons emitted by the first emitter and the second emitter have a second intensity different from the first intensity. | 12-13-2012 |
20150015536 | TOUCH-SCREEN SYSTEM AND DISPLAY PANEL WITH TOUCH-SENSING FUNCTION - A touch-screen system including a stylus, a display panel and a touch module is disclosed herein. The stylus includes a magnetic component. The touch-sensing module is disposed within the display panel. The touch-sensing module includes a plurality of sensing units distributed at different locations as an array over the display panel. Each of the sensing units includes a Hall induction plate for sensing a magnetic field established by the magnetic component and forming an induction output voltage. The touch module detects a touch position of the stylus according to the induction output voltages from the sensing units. | 01-15-2015 |
Chi-Liang Kuo, Hsin-Chu TW
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20140273434 | METHOD OF FABRICATING COPPER DAMASCENE - A method of fabricating a semiconductor device includes forming a non-conductive layer over a semiconductor substrate. A low-k dielectric layer is formed over the non-conductive layer. The low-k dielectric layer is etched and stopped at the non-conductive layer to form an opening. A plasma treatment is performed on the substrate to convert the non-conductive layer within the opening into a conductive layer. The opening is filled with a copper-containing material in an electroless copper bottom up fill process to form a copper-containing plug. The copper-containing plug is planarized so that the top of the copper-containing plug is co-planar with the top of the low-k dielectric layer. The substrate is heated to form a self-forming barrier layer on the sidewalls of the copper-containing plug. | 09-18-2014 |
20150132947 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device may include: forming an opening in a dielectric layer, the opening exposing a non-conductive layer disposed over a semiconductor substrate; forming a self-assembled monolayer (SAM) within the opening and over the non-conductive layer; forming a catalytic layer within the opening and over the SAM; filling the opening having the SAM and the catalytic layer with a conductive material to form a plug; and forming a barrier layer on sidewalls of the plug. | 05-14-2015 |
Chun-Hung Kuo, Hsin-Chu TW
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20090278779 | LCD DEVICE BASED ON DUAL SOURCE DRIVERS WITH DATA WRITING SYNCHRONOUS CONTROL MECHANISM AND RELATED DRIVING METHOD - An LCD device having dual source drivers and related driving method are disclosed for performing data signal driving operation by making use of a data writing synchronous control mechanism. The operation of the data writing synchronous control mechanism includes furnishing all image data signals to both the first and second source drivers, latching odd and even image data signals by the first and second source drivers respectively, performing a signal processing process on the odd image data signals for generating a first set of analog data signals by the first source driver, performing a signal processing process on the even image data signals for generating a second set of analog data signals by the second source driver, writing the first set of analog data signals into a plurality of first pixel units, and writing the second set of analog data signals into a plurality of second pixel units. | 11-12-2009 |
20100164850 | Liquid Display Panel Driving Method - A liquid display panel driving method to drive a plurality of pixels of a liquid display panel in a frame period comprising a plurality of data input intervals is provided. Each pixel comprises first and second capacitors coupled to a first and second common electrode respectively. The liquid display panel driving method comprises the steps of: keeping the second common electrode at the same voltage level; modifying the voltage of the first common electrode of each pixel along a row of scan line to perform a first pre-charge before the data input interval; turning on the pixels to make each pixel receive the data voltage from the data lines during the data input interval; and turning off the pixels and modifying the voltage of the first common electrode to further set the voltage of each of the pixels to a target level after the data input interval. | 07-01-2010 |
20110090196 | LIQUID CRYSTAL DISPLAY HAVING PIXEL DATA SELF-RETAINING FUNCTIONALITY AND OPERATION METHOD THEREOF - A liquid crystal display having pixel data self-retaining functionality includes a gate line for delivering a gate signal, a data line for delivering a data signal, a control unit for providing a first control signal and a second control signal, a data switch, a voltage-control inverter, a liquid crystal capacitor, and a pass transistor. The data switch is utilized for inputting the data signal to become a first data signal according to the gate signal. The voltage-control inverter is utilized for inverting the first data signal to generate a second data signal furnished to the liquid crystal capacitor according to the enable operation of the first control signal. The pass transistor is used for passing the second data signal to become the first data signal or for passing the first data signal to become the second data signal according to the second control signal. | 04-21-2011 |
20120113070 | GATE DRIVER CIRCUIT AND ARRANGEMENT METHOD OF THE SAME - An arrangement method, applied to a plurality of gate driver modules coupled in series and arranged on two sides of a panel, includes steps of: placing a first gate driver module on a first side of the panel; placing a gate driver set on a second side of the panel; and placing a fourth gate driver module on the first side of the panel. The gate driver set includes a second gate driver module and a third gate driver module serially connected. The output terminal of the first gate driver module is electrically coupled to the second gate driver module and the output terminal of the third gate driver module is electrically coupled to the fourth gate driver module. A gate driver circuit and an arrangement method applied to a plurality of shift register sets coupled in series and arranged on two sides of a panel are also disclosed. | 05-10-2012 |
20120133392 | MULTIPLEX GATE DRIVING CIRCUIT - A multiplex gate driving circuit includes plural driving modules. In comparison with the prior art, each driving stage of the driving module has less number of transistors. From the first to the seventh example, each driving stage is implemented by only four transistors. In the eighth example and the ninth example, each driving stage is implemented by only two transistors. In other words, the driving stage of the multiplex gate driving circuit has less number of transistors, thereby reducing the layout area of the invisible zone of the LCD panel. | 05-31-2012 |
20140160096 | DISPLAY HAVING SHARED DRAIN STRUCTURE - A display includes a source driver, a demultiplexer, a first data line, a second data line, a first pixel and a second pixel. The demultiplexer includes a first pixel signal transmission unit and a second pixel signal transmission unit. The first pixel signal transmission unit includes a first sub-pixel signal transmission unit, a second sub-pixel signal transmission unit and a third sub-pixel signal transmission unit. The first sub-pixel signal transmission unit and the second sub-pixel signal transmission unit share a drain. A second pixel signal transmission unit next to the first pixel signal transmission unit includes a fourth sub-pixel signal transmission unit, a fifth sub-pixel signal transmission unit and a sixth sub-pixel signal transmission unit. The fourth sub-pixel signal transmission unit and the fifth sub-pixel signal transmission unit share another drain. | 06-12-2014 |
20140210699 | LCD DEVICE BASED ON DUAL SOURCE DRIVERS WITH DATA WRITING SYNCHRONOUS CONTROL MECHANISM AND RELATED DRIVING METHOD - An LCD device having dual source drivers and related driving method are disclosed for performing data signal driving operation by making use of a data writing synchronous control mechanism. The operation of the data writing synchronous control mechanism includes furnishing all image data signals to both the first and second source drivers, latching odd and even image data signals by the first and second source drivers respectively, performing a signal processing process on the odd image data signals for generating a first set of analog data signals by the first source driver, performing a signal processing process on the even image data signals for generating a second set of analog data signals by the second source driver, writing the first set of analog data signals into a plurality of first pixel units, and writing the second set of analog data signals into a plurality of second pixel units. | 07-31-2014 |
Chun-Ku Kuo, Hsin-Chu TW
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20120062250 | CAPACITIVE TOUCH SENSOR AND CAPACITIVE TOUCH APPARATUS - An exemplary capacitive touch sensor includes a first wire-like electrode and a second wire-like electrode. The first wire-like electrode includes at least a first main wire and multiple first sub-wires, the first main wire continuously extends along a first direction, and the first sub-wires are electrically connected with the first main wire. The second wire-like electrode includes at least a second main wire, and the second main wire continuously extends along a second direction different from the first direction. Moreover, the first wire-like electrode and the second wire-like electrode are electrically insulated from each other and each is made of an opaque conductive material. The second main line is arranged crossing over the first main wire. Furthermore, a capacitive touch apparatus using the above-mentioned capacitive touch sensor is provided. | 03-15-2012 |
20120169647 | CAPACITIVE TOUCH DISPLAY PANEL - A capacitive touch display panel includes a display panel, an outer substrate, and a capacitive touch device. The capacitive touch device is disposed between the outer substrate and the display panel. The capacitive touch device includes a plurality of first transparent electrodes, at least one transparent bridge line, a plurality of second transparent electrodes, at least one non-transparent bridge line, and at least one patterned low reflective layer. The patterned low reflective layer is disposed on an opposite side of the non-transparent bridge line with respect to the display panel. The patterned low reflective layer and the non-transparent bridge line are overlapped to each other in a vertical projective direction. | 07-05-2012 |
Chun-Liang Kuo, Hsin-Chu TW
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20120025712 | BACKLIGHT MODULE OF LIQUID CRYSTAL DISPLAY DEVICE - The disclosure provides a backlight module applied to a liquid crystal display device. The backlight module includes: a control circuit for outputting a driving signal according to an analog adjustment signal or a digital adjustment signal; a driving circuit for outputting a lamp voltage according to the driving signal; a fluorescent lamp set, including a plurality of lamps, for receiving the lamp voltage and thereby generating a lamp current; a lamp feedback circuit c for outputting a feedback signal according to the lamp voltage; and a dynamic protection circuit, for dynamically adjusting a protection command signal according to the analog dimming signal or the digital dimming signal, comparing the protection command signal and the feedback signal and thereby outputting a comparing result signal to the control circuit. | 02-02-2012 |
Chun-Lung Kuo, Hsin-Chu TW
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20140176112 | LOW VOLTAGE BANDGAP REFERENCE CIRCUIT - A low voltage bandgap reference circuit includes a positive temperature coefficient circuit unit, a negative temperature coefficient circuit unit and a load unit, wherein the positive temperature coefficient circuit unit comprises a first differential operational amplifier, a first, second and third transistor, a first resistor, a first and second diode, and the negative temperature coefficient circuit unit includes a second differential operational amplifier, a fourth, fifth and sixth transistor, a second resistor and a third diode. The low voltage bandgap reference circuit provides a current having a positive temperature coefficient characteristics and a current having a negative temperature coefficient characteristics to flow through the load unit, whereby generate a stable reference voltage thereon, which the stable reference voltage is less affected by the temperature. Therefore, it avoids the problems of the low voltage bandgap reference circuit can not be activated at low voltage. | 06-26-2014 |
20140337547 | HIGH SPEED DATA TRANSMISSION STRUCTURE - A high-speed data transmission structure includes first and second electronic units and an input/output bus. The input/output bus is electrically connected to the first and second electronic units, and includes a clock signal line and N data lines, where N is an even integer. The data lines are divided into first and second data signal line groups, each provided with the same number of data lines. In a transmit mode, the first electronic unit generates and transmits a clock signal to the clock data line, and generates output signals at each clock period of the clock signal. The output signals consist of N/2 data signals lasting for two clock periods of the clock signal, and the first and second data signal line groups alternatively receive the output signals. The second electronic unit simultaneously performs a receive mode to fetch and latch the data signals according to the clock signal. | 11-13-2014 |
Han-Ching Kuo, Hsin-Chu TW
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20140083504 | SOLAR APPARATUS AND MOUNTING SYSTEM THEREOF - A solar apparatus includes a solar cell, a frame including a main body and a hollow rib, a pair of first support racks, and a pair of second support racks. The main body surrounds the edge of the solar cell. The hollow rib protrudes over the circumference of the main body. The first support racks are located on a first side of the frame, and each of the first support racks includes a first engaging clamp for coupling to the hollow rib of the frame. The second support racks are located on a second side of the frame facing away from the first side, and each of the second support racks includes a second engaging clamp for coupling to the hollow rib of the frame. | 03-27-2014 |
Han-Ping Kuo, Hsin-Chu TW
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20090278813 | Touch Panel - The present invention provides a touch panel used in a display device. The touch panel of the present invention is configured to display images and to receive as well as to process instructions inputted by user's touches. A display substrate partially overlaps with an image driving circuit substrate of the touch panel. A touch sensing circuit is disposed on the inner side of the display substrate. A touch sensing processor is disposed on the inner side of a touch sensing circuit and is also electrically coupled to the touch sensing circuit. Consequently, the thickness of the touch panel as well as the overall thickness of the display device is reduced. | 11-12-2009 |
20100277665 | Display Device with Multiple Display Modules - A display device including a first prism sheet, a second prism sheet disposed side by side with the first prism sheet, a first display module, and a second display module is provided. The first display module is disposed beneath the first prism and has a first display surface. At least a portion of the first display surface close to the second prism sheet is inclined toward the second prism sheet and forms a first angle with respect to the first prism sheet. The second display module is disposed beneath the second prism sheet and has a second display surface. At least a portion of the second display surface closed to the first prism sheet is inclined toward the first prism sheet and forms a first angle with respect to the second prism sheet. | 11-04-2010 |
20130010411 | Display Module and Manufacturing Method Thereof - A display module includes a first housing, a second housing, a display panel, and a glue. The first housing is disposed on the second housing and has a metal sidewall. A first gap exists between the metal sidewall and a sidewall of the first housing. The display panel is disposed on the first housing and has a side surface facing the sidewall, wherein a second gap exists between the side surface and the inner surface. The glue fills the second gap. A manufacturing method of the display module includes disposing the second housing on the first housing and forming the first gap; providing the glue on the inner face of the sidewall and above the first gap; making the display panel push and graze the glue; disposing the display panel on the first housing and forming the second gap, wherein the glue fills the second gap. | 01-10-2013 |
20130263488 | DISPLAY DEVICE AND ASSEMBLY METHOD THEREOF - A display device includes a frame, an adhesive tape, a curing adhesive and a display panel. The frame has a top surface, an inner surface and an outer surface. The top surface is connected between the inner surface and the outer surface. The top surface has a first adhesive region and a second adhesive region which are adjacent to each other. The first adhesive region is located between the inner surface and the second adhesive region. The adhesive tape is adhered to the first adhesive region. The display panel is adhered to the top surface of the frame by the adhesive tape. The curing adhesive is adhered to at least one side surface of the display panel, the second adhesive region and the adhesive tape. A display device assembly method is also provided. | 10-10-2013 |
20140111975 | Light Guide Plate and Backlight Module and Display Module Using the Same - A light guide plate includes a plate body and a supporting unit. The plate body has a light-exiting face and a lateral side, wherein the supporting unit is disposed along the lateral side. The supporting unit has a top surface and an outer lateral surface, the top surface is above the light-exiting face, the lateral surface protrudes from an end surface of the lateral side of the plate body, wherein a portion of the end surface away from the light-exiting face is exposed to form a recess. A backlight module includes the light guide plate mentioned above and a back plate, wherein the light guide plate is disposed on the back plate. A periphery of the back plate has a side wall formed thereon and extending into the recess. A display device includes the light guide plate mentioned above and a display panel, wherein the display panel is disposed on the light guide plate and is supported by the top surface. | 04-24-2014 |
20140307185 | Touch Panel - The present invention provides a touch panel used in a display device. The touch panel of the present invention is configured to display images and to receive as well as to process instructions inputted by user's touches. A display substrate partially overlaps with an image driving circuit substrate of the touch panel. A touch sensing circuit is disposed on the inner side of the display substrate. A touch sensing processor is disposed on the inner side of a touch sensing circuit and is also electrically coupled to the touch sensing circuit. Consequently, the thickness of the touch panel as well as the overall thickness of the display device is reduced. | 10-16-2014 |
20150055372 | Thin Type Display Module - A display module including a backlight module and a display panel is provided. The backlight module includes a light guide plate and a light source module. The light guide plate has a light incident surface, a light-exiting surface, a light-guiding inclined surface, a bottom surface, and a lateral surface, wherein the light-guiding inclined surface is connected to the light incident surface and the light-exiting surface; the light incident surface, the light-guiding inclined surface, and a portion of the bottom surface constitute a wedge portion while the light-exiting surface, the lateral surface, and other portions of the bottom surface constitute a plate portion. The light source module is disposed at the light incident surface and emits light into the wedge portion. The display panel is disposed on the light guide plate and has a side. The side of the display panel has a projection disposed in the light-guiding inclined surface or the plate portion. | 02-26-2015 |
20150174882 | Display Module and Manufacturing Method Thereof - A display module includes a first housing, a second housing, a display panel, and a glue. The first housing is disposed on the second housing and has a metal sidewall. A first gap exists between the metal sidewall and a sidewall of the first housing. The display panel is disposed on the first housing and has a side surface facing the sidewall, wherein a second gap exists between the side surface and the inner surface. The glue fills the second gap. A manufacturing method of the display module includes disposing the second housing on the first housing and forming the first gap; providing the glue on the inner face of the sidewall and above the first gap; making the display panel push and graze the glue; disposing the display panel on the first housing and forming the second gap, wherein the glue fills the second gap. | 06-25-2015 |
Hao-Jan Kuo, Hsin-Chu TW
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20100103345 | Backlight module and liquid crystal display - A backlight module includes at least one point light source and a light guide plate. The light guide plate includes a light emitting surface, a bottom surface, a light incident surface, a first side surface, a second side surface, a first microstructure, and a second microstructure. The bottom surface is opposite to the light emitting surface, the light incident surface connects the light emitting surface and the bottom surface, the point light source is disposed adjacent to the light incident surface, and the first microstructure is formed on the light incident surface. The first side surface is opposite to the light incident surface and connects the light emitting surface and the bottom surface, and the second side surface connects the light emitting surface, the bottom surface, the light incident surface, and the first side surface. The second microstructure is formed on the second side surface. | 04-29-2010 |
Hsi-Yu Kuo, Hsin-Chu TW
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20120168906 | ESD Protection Device with Tunable Design Windows - An electrostatic discharge (ESD) device includes a high-voltage well (HVW) region of a first conductivity type; a first heavily doped region of a second conductivity type opposite the first conductivity type over the HVW region; and a doped region of the first conductivity type contacting the first heavily doped region and the HVW region. The doped region is under the first heavily doped region and over the HVW region. The doped region has a first impurity concentration higher than a second impurity concentration of the HVW region and lower than a third impurity concentration of the first heavily doped region. The ESD device further includes a second heavily doped region of the second conductivity type over the HVW region; and a third heavily doped region of the first conductivity type over and contacting the HVW region. | 07-05-2012 |
20140339603 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes: a substrate; a first region over the substrate; a second region laterally adjacent to the first region; a third region disposed laterally adjacent to the second region on a side of the second region opposite the first region; a fourth region disposed within a portion of the first region proximate the second region; a fifth region disposed within a portion of the second region proximate the first region, wherein the fourth region and the fifth region are separated by a first isolation area; a sixth region disposed within a portion of the third region proximate the second region; and a seventh region disposed within the second region and below the fifth region. | 11-20-2014 |
20140339676 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes: a substrate; a first region over the substrate, the first region comprising a first n type material; a second region over the substrate and laterally adjacent to the first region, the second region comprising a first p type material; a third region disposed within the second region and laterally separated from the first region, the third region comprising a second n type material; a fourth region disposed atop the third region, the fourth region comprising a second p type material; a fifth region disposed within the first region and laterally separated from the second region, the fifth region comprising a third p type material; and a sixth region disposed atop the fifth region, the sixth region comprising a third n type material. | 11-20-2014 |
Hung-Jui Kuo, Hsin-Chu TW
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20110089560 | Non-Uniform Alignment of Wafer Bumps with Substrate Solders - An integrated circuit structure includes a work piece selected from the group consisting of a semiconductor chip and a package substrate. The work piece includes a plurality of under bump metallurgies (UBMs) distributed on a major surface of the work piece; and a plurality of metal bumps, with each of the plurality of metal bumps directly over, and electrically connected to, one of the plurality of UBMs. The plurality of UBMs and the plurality of metal bumps are allocated with an overlay offset, with at least some of the plurality of UBMs being misaligned with the respective overlying ones of the plurality of metal bumps. | 04-21-2011 |
20120009777 | UBM Etching Methods - A method of forming a device includes forming an under-bump metallurgy (UBM) layer including a barrier layer and a seed layer over the barrier layer; and forming a mask over the UBM layer. The mask covers a first portion of the UBM layer, and a second portion of the UBM layer is exposed through an opening in the mask. The first portion of the UBM layer includes a barrier layer portion and a seed layer portion. A metal bump is formed in the opening and on the second portion of the UBM layer. The mask is then removed. A wet etch is performed to remove the seed layer portion. A dry etch is performed to remove the barrier layer portion. | 01-12-2012 |
20120064712 | Method for Reducing UBM Undercut in Metal Bump Structures - A method of forming a device includes providing a wafer including a substrate; and forming an under-bump metallurgy (UBM) layer including a barrier layer overlying the substrate and a seed layer overlying the barrier layer. A metal bump is formed directly over a first portion of the UBM layer, wherein a second portion of the UBM layer is not covered by the metal bump. The second portion of the UBM layer includes a seed layer portion and a barrier layer portion. A first etch is performed to remove the seed layer portion, followed by a first rinse step performed on the wafer. A second etch is performed to remove the barrier layer portion, followed by a second rinse step performed on the wafer. At least a first switch time from the first etch to the first rinse step and a second switch time from the second etch to the second rinse step is less than about 1 second. | 03-15-2012 |
20120319270 | Wafer Level Chip Scale Package with Reduced Stress on Solder Balls - A structure includes a metal pad over a semiconductor substrate, a passivation layer having a portion over the metal pad, and a first polyimide layer over the passivation layer, wherein the first polyimide layer has a first thickness and a first Young's modulus. A post-passivation interconnect (PPI) includes a first portion over the first polyimide layer, and a second portion extending into the passivation layer and the first polyimide layer. The PPI is electrically coupled to the metal pad. A second polyimide layer is over the PPI. The second polyimide layer has a second thickness and a second Young's modulus. At least one of a thickness ratio and a Young's modulus ratio is greater than 1.0, wherein the thickness ratio is the ratio of the first thickness to the second thickness, and the Young's modulus ratio is the ratio of the second Young's modulus to the first Young's modulus. | 12-20-2012 |
20130012014 | UBM Etching Methods for Eliminating Undercut - A method includes forming an under-bump metallurgy (UBM) layer overlying a substrate, and forming a mask overlying the UBM layer. The mask covers a first portion of the UBM layer, and a second portion of the UBM layer is exposed through an opening in the mask. A metal bump is formed in the opening and on the second portion of the UBM layer. The mask is then removed. A laser removal is performed to remove a part of the first portion of the UBM layer and to form an UBM. | 01-10-2013 |
20130026644 | Photoactive Compound Gradient Photoresist - A system and method for forming photoresists over semiconductor substrates is provided. An embodiment comprises a photoresist with a concentration gradient. The concentration gradient may be formed by using a series of dry film photoresists, wherein each separate dry film photoresist has a different concentration. The separate dry film photoresists may be formed separately and then placed onto the semiconductor substrate before being patterned. Once patterned, openings through the photoresist may have a tapered sidewall, allowing for a better coverage of the seed layer and a more uniform process to form conductive materials through the photoresist. | 01-31-2013 |
20130127059 | Adjusting Sizes of Connectors of Package Components - A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component. | 05-23-2013 |
20130175705 | Stress Compensation Layer for 3D Packaging - A stress compensation for use in packaging, and a method of forming, is provided. The stress compensation layer is placed on an opposing side of a substrate from an integrated circuit die. The stress compensation layer is designed to counteract at least some of the stress exerted structures on the die side of the substrate, such as stresses exerted by a molding compound that at least partially encapsulates the first integrated circuit die. A package may also be electrically coupled to the substrate. | 07-11-2013 |
20130236994 | Non-Uniform Alignment of Wafer Bumps with Substrate Solders - An integrated circuit structure includes a work piece selected from the group consisting of a semiconductor chip and a package substrate. The work piece includes a plurality of under bump metallurgies (UBMs) distributed on a major surface of the work piece; and a plurality of metal bumps, with each of the plurality of metal bumps directly over, and electrically connected to, one of the plurality of UBMs. The plurality of UBMs and the plurality of metal bumps are allocated with an overlay offset, with at least some of the plurality of UBMs being misaligned with the respective overlying ones of the plurality of metal bumps. | 09-12-2013 |
20130276837 | Cleaning Methods and Compositions - Methods and chemical solvents used for cleaning residues on metal contacts during a semiconductor device packaging process are disclosed. A chemical solvent for cleaning a residue formed on a metal contact may comprise a reactive inorganic component and a reactive organic component. The method may comprise spraying a semiconductor device with a chemical solvent at a first pressure, and spraying the semiconductor device with the chemical solvent at a second pressure less than the first pressure. | 10-24-2013 |
20140008785 | Package Redistribution Layer Structure and Method of Forming Same - A package-on-package (PoP) device comprises a bottom package on a substrate and a first set of conductive elements coupling the bottom package and the substrate. The PoP device further comprises a top package over the bottom package and a redistribution layer coupling the top package to the substrate. A method of forming a PoP device comprises coupling a first package to a substrate; and forming a redistribution layer over the first package and a top surface of the substrate. The method further comprises coupling a second package to the redistribution layer, wherein the redistribution layer couples the second package to the substrate. | 01-09-2014 |
20140015122 | Method of Forming Post Passivation Interconnects - A method of forming post passivation interconnects comprises forming a passivation layer over a substrate, wherein a metal pad is embedded in the passivation layer, depositing a first dielectric layer on the passivation layer, applying a first patterning process to the first dielectric layer to form a first opening, forming a first seed layer over the first opening, filling the first opening with a conductive material, depositing a second dielectric layer on the first dielectric layer, applying a second patterning process to the second dielectric layer to form a second opening, forming an under bump metallization structure over the second opening and mounting an interconnect bump over the under bump metallization structure. | 01-16-2014 |
20140061923 | STRUCTURE TO INCREASE RESISTANCE TO ELECTROMIGRATION - A semiconductor device includes a recess in a polymer layer between two adjacent metal lines and over passivation layer or anti-electromigration layers on redistribution metal lines to increase the resistance to electromigration. | 03-06-2014 |
20140117563 | Photoactive Compound Gradient Photoresist - A system and method for forming photoresists over semiconductor substrates is provided. An embodiment comprises a photoresist with a concentration gradient. The concentration gradient may be formed by using a series of dry film photoresists, wherein each separate dry film photoresist has a different concentration. The separate dry film photoresists may be formed separately and then placed onto the semiconductor substrate before being patterned. Once patterned, openings through the photoresist may have a tapered sidewall, allowing for a better coverage of the seed layer and a more uniform process to form conductive materials through the photoresist. | 05-01-2014 |
20140252594 | Package Structures and Methods for Forming the Same - A packaging structure and a method of forming a packaging structure are provided. The packaging structure, such as an interposer, is formed by optionally bonding two carrier substrates together and simultaneously processing two carrier substrates. The processing includes forming a sacrificial layer over the carrier substrates. Openings are formed in the sacrificial layers and pillars are formed in the openings. Substrates are attached to the sacrificial layer. Redistribution lines may be formed on an opposing side of the substrates and vias may be formed to provide electrical contacts to the pillars. A debond process may be performed to separate the carrier substrates. Integrated circuit dies may be attached to one side of the redistribution lines and the sacrificial layer is removed. | 09-11-2014 |
20140256126 | Electrical Connectors and Methods for Forming the Same - A method includes coating a photo resist over an Under-Bump Metallurgy (UBM) layer and exposing the photo resist. In the step of exposing, a light amount reaching a bottom of the photo resist is less than about 5 percent of a light amount reaching a top surface of the photo resist. The method further includes developing the photo resist to form an opening in the photo resist. A portion of the UBM layer is exposed through the opening. The opening has a bottom lateral dimension greater than a top lateral dimension. An electrical connector is formed in the opening, wherein the electrical connector is non-reflowable. | 09-11-2014 |
20140264824 | Methods and Apparatus of Packaging Semiconductor Devices - Methods and apparatus are disclosed which reduce the stress concentration at the redistribution layers (RDLs) of a package device. A package device may comprise a seed layer above a passivation layer, covering an opening of the passivation layer, and covering and in contact with a contact pad. A RDL is formed above the passivation layer, above and in contact with the seed layer, covering the opening of the passivation layer, and electrically connected to the contact pad through the seed layer. The RDL has an end portion with a surface that is smooth without a right angle. The surface of the end portion of the RDL may have an obtuse angle, or a curved surface. | 09-18-2014 |
20140264863 | Conductive Line System and Process - A system and method for providing a conductive line is provided. In an embodiment the conductive line is formed by forming two passivation layers, wherein each passivation layer is independently patterned. Once formed, a seed layer is deposited into the two passivation layers, and a conductive material is deposited to fill and overfill the patterns within the two passivation layers. A planarization process such as a chemical mechanical polish may then be utilized in order to remove excess conductive material and form the conductive lines within the two passivation layers. | 09-18-2014 |
20140308764 | Adjusting Sizes of Connectors of Package Components - A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component. | 10-16-2014 |
20150061127 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a substrate, and a plurality of contact pads disposed over the substrate. The contact pads are arranged in a ball grid array (BGA), and the BGA includes a plurality of corners. A metal dam is disposed around each of the plurality of corners of the BGA. | 03-05-2015 |
20150187695 | Staggered Via Redistribution Layer (RDL) for a Package - An embodiment staggered via redistribution layer (RDL) for a package includes a first polymer layer supported by a metal via. The first polymer layer has a first polymer via. A first redistribution layer is disposed on the first polymer layer and within the first polymer via. The first redistribution layer is electrically coupled to the metal via. A second polymer layer is disposed on the first redistribution layer. The second polymer layer has a second polymer via laterally offset from the first polymer via. A second redistribution layer is disposed on the second polymer layer and within the second polymer via. The second redistribution layer is electrically coupled to the first redistribution layer. | 07-02-2015 |
20150243531 | Via Structure For Packaging And A Method Of Forming - A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps. | 08-27-2015 |
20150243616 | PACKAGES WITH SOLDER BALL REVEALED THROUGH LASER - An integrated circuit structure includes a substrate, a PPI over the substrate, a solder region over and electrically coupled to a portion of the PPI, and a molding compound molding a lower portion of the solder region therein. A top surface of the molding compound is level with or lower than a maximum-diameter plane, wherein the maximum-diameter plane is parallel to a major surface of the substrate, and the maximum-diameter of the solder region is in the maximum-diameter plane. | 08-27-2015 |
20150262948 | Methods and Apparatus of Packaging Semiconductor Devices - Methods and apparatus are disclosed which reduce the stress concentration at the redistribution layers (RDLs) of a package device. A package device may comprise a seed layer above a passivation layer, covering an opening of the passivation layer, and covering and in contact with a contact pad. A RDL is formed above the passivation layer, above and in contact with the seed layer, covering the opening of the passivation layer, and electrically connected to the contact pad through the seed layer. The RDL has an end portion with a surface that is smooth without a right angle. The surface of the end portion of the RDL may have an obtuse angle, or a curved surface. | 09-17-2015 |
20150279776 | Integrated Structure in Wafer Level Package - An embodiment device package includes a die having a conductive pillar and a molding compound extending along sidewalls of the die. The molding compound at least partially covers a top surface of the die. The device package further includes a conductive via extending through the molding compound and a redistribution layer (RDL) over the molding compound. The RDL and the molding compound have a continuous interface extending from the conductive via to a point over the die. | 10-01-2015 |
20150311132 | SCRIBE LINE STRUCTURE AND METHOD OF FORMING SAME - An embodiment device includes a die, a molding compound extending along sidewalls of the die, and a first polymer layer over the die and the molding compound. The first polymer layer has a first lateral dimension. The device further includes a second polymer layer over the first polymer layer. The second polymer layer has a second lateral dimension, where the second lateral dimension is less than the first lateral dimension. | 10-29-2015 |
20150347663 | Adjusting Sizes of Connectors of Package Components - A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component. | 12-03-2015 |
20150364369 | Conductive Line System and Process - A system and method for providing a conductive line is provided. In an embodiment the conductive line is formed by forming two passivation layers, wherein each passivation layer is independently patterned. Once formed, a seed layer is deposited into the two passivation layers, and a conductive material is deposited to fill and overfill the patterns within the two passivation layers. A planarization process such as a chemical mechanical polish may then be utilized in order to remove excess conductive material and form the conductive lines within the two passivation layers. | 12-17-2015 |
20150380334 | Advanced Structure for Info Wafer Warpage Reduction - A package (e.g., a wafer level package (WLP)) including one or more redistribution layers to fan out the contact pads of the one or more dies within an integrated circuit structure. An example package includes a die having a contact pad exposed at a frontside thereof. The package also includes a redistribution layer disposed over the frontside of the die. The redistribution layer includes metallization extending through a nano-composite material, which may be formed from a dielectric material with a nano-filler material disposed therein. The metallization is electrically coupled to the contact pad of the die. By incorporating the nano-composite material in the redistribution layer, the coefficient of thermal expansion (CTE) of the redistribution layer more closely matches the CTE of the die, which prevents or eliminates undesirable warpage of the redistribution layers. | 12-31-2015 |
20150380350 | Staggered Via Redistribution Layer (RDL) for a Package and a Method for Forming the Same - An embodiment staggered via redistribution layer (RDL) for a package includes a first polymer layer supported by a metal via. The first polymer layer has a first polymer via. A first redistribution layer is disposed on the first polymer layer and within the first polymer via. The first redistribution layer is electrically coupled to the metal via. A second polymer layer is disposed on the first redistribution layer. The second polymer layer has a second polymer via laterally offset from the first polymer via. A second redistribution layer is disposed on the second polymer layer and within the second polymer via. The second redistribution layer is electrically coupled to the first redistribution layer. | 12-31-2015 |
20160079190 | Package with UBM and Methods of Forming - Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, and an external connector on the connector support metallization. The redistribution structure includes a dielectric layer disposed distally from the encapsulant and the integrated circuit die. The connector support metallization has a first portion on a surface of the dielectric layer and has a second portion extending in an opening through the dielectric layer. The first portion of the connector support metallization has a sloped sidewall extending in a direction away from the surface of the dielectric layer. | 03-17-2016 |
20160086900 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a substrate, and a plurality of contact pads disposed over the substrate. The contact pads may be arranged in a ball grid array (BGA), and the may include a plurality of corners. A metal dam is disposed around each of the plurality of corners, such as corners of the BGA. | 03-24-2016 |
Hung-Yi Kuo, Hsin-Chu TW
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20150380351 | Capacitor in Post-Passivation Structures and Methods of Forming the Same - A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer. | 12-31-2015 |
Min-Chien Kuo, Hsin-Chu TW
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20130228212 | COMPONENT FOR FASTENING WIRE IN SOLAR MODULE AND SOLAR MODULE USING THE SAME - A component for fastening wires in a solar module is disclosed. The component includes a fastener and an adhesive layer. The fastener includes a substrate, two hooks disposed on the substrate, and two bases. Two cavities are formed between the hooks and the substrate for receiving the wires. Each hook has an opening, and the bases connect to the substrate and are disposed corresponding to the openings. A surface of each of the bases facing away from the cavity is inclined relative to the substrate, and a surface of each of the bases facing the cavity is substantially vertical to the surface. The adhesive layer is disposed on a surface of the substrate which is opposite to the hooks. A solar module using the component is also disclosed. | 09-05-2013 |
20130264884 | ALTERNATING CURRENT PHOTOVOLTAIC MODULE AND METHOD FOR MANAGING ELECTRICITY THEREIN - An alternating current photovoltaic module includes a photovoltaic cell module, an inverter, and an electricity storing component. The inverter includes an electricity transforming unit and a micro control unit. The photovoltaic cell module operates to transform luminous energy into electricity. The electricity transforming unit operates to transform electricity. In addition, the micro control unit operates to control the inverter to deliver the electricity which is generated by photovoltaic cell module and transformed by the electricity transforming unit to the electricity storing component for storing the electricity. The micro control unit also operates to control the electricity storing component for providing the stored electricity in the electricity storing component. | 10-10-2013 |
20140021792 | SOLAR POWER SYSTEM AND COMMUNICATION APPARATUS - A solar power system includes at least one alternating-current module and a communication apparatus. Each alternating-current module includes a solar panel and an alternating-current inverter. The communication apparatus connects to the alternating-current module and controls stand-alone power-generating operations on the alternating-current module. The communication includes a module connector and a control circuit. The module connector is configured for connecting with the alternating-current module. The alternating-current module can be parallel-connected on a household power grid selectively. The communication apparatus can transmit a stand-alone power-generating command to the alternating-current module. The alternating-current inverter may cancel an anti-islanding protection procedure thereon according to the stand-alone power-generating command. | 01-23-2014 |
20140182663 | PHOTOVOLTAIC PANEL SYSTEM, PHOTOVOLTAIC PANEL FASTENING DEVICE, AND METHOD OF INSTALLING PHOTOVOLTAIC PANEL SYSTEM - A photovoltaic panel fastening device includes a loading pedestal, a first supporting plate and a second supporting plate. The loading pedestal includes a plurality of side plates and a bottom plate. The side plates are respectively connected to two opposite sides above the bottom plate, and construct a loading recess. The side plates respectively include an opening. The first supporting plate is connected underneath the bottom plate. The second supporting plate is connected underneath the bottom plate and is connected to one of the side plates. | 07-03-2014 |
20140366931 | BRACKET AND PHOTOVOLTAIC APPARATUS HAVING THE SAME - A Photovoltaic apparatus includes a photovoltaic panel, a frame, a bracket and a T-shaped electrical junction. The frame is defined with a receiving space therein. The photovoltaic panel is disposed in the receiving space. The bracket couples on the frame, and the bracket includes a connection portion and a hanging portion. The T-shaped electrical junction is electrically connected to the photovoltaic panel and two external devices. The connection portion fixes the bracket on the frame, and the hanging portion supports the T-shaped electrical junction. | 12-18-2014 |
20150028682 | SOLAR ENERGY GENERATION SYSTEM, MEASUREMENT MODULE AND POSITIONING METHOD - A solar energy generation system a measurement module and a positioning method are disclosed herein. The positioning method is adaptable to a power generation system having AC generation modules. Each of the AC generation modules generates an output current and is electrically connected to each other in a power-supply network. The positioning method includes the following operations: (a) measuring AC currents or node voltages generated by the AC generation modules at different positions in the power-supply network to obtain current parameters or voltage parameters; and (b) determining a sequence of relative positions of the AC generation modules by calculating the current parameters or the voltage parameters. | 01-29-2015 |
20150085210 | In-Cell Touch Liquid Crystal Display Module and Manufacturing Method For The Same - An in-cell touch liquid crystal display module includes a first glass substrate, a metal film disposed on the first glass substrate, a liquid crystal layer disposed on the metal film, a second glass substrate disposed on the liquid crystal layer, a conductive layer disposed on the second glass substrate for generating a sensing signal in response to a touch of the conductive layer, a flexible circuit board comprising a plurality of wires coupling the conductive layer, for transmitting the sensing signal, a conductive adhesive for adhering and fastening the flexible circuit board on the second glass substrate, and an insulating adhesive disposed on an periphery of the first glass substrate, for adhering the flexible circuit board on the first glass substrate. | 03-26-2015 |
Ming-Feng Kuo, Hsin-Chu TW
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20100290252 | LIGHT GUIDE PLATE AND BACKLIGHT MODULE - A light guide plate capable of guiding a light beam from a light emitting device and a backlight module using the light guide plate are provided. The light guide plate includes a light-transmissive substrate and optical structures. The light-transmissive substrate has a first surface, an opposite second surface, and an incident surface connecting the first and the second surface. The light beam enters the light-transmissive substrate through the incident surface and is emitted out of the light-transmissive substrate through the first surface. The optical structures are disposed on the second surface. Each optical structure has a first total internal reflection (TIR) surface, a second TIR surface, and a third TIR surface. The second TIR surface connects the first and third TIR surfaces. Part of the light beam from the incident surface is totally internally reflected by any adjacent two of the first, second, and third TIR surfaces in sequence. | 11-18-2010 |
20120275190 | LIGHT GUIDE PLATE AND LIGHT SOURCE MODULE - A light guide plate (LGP) includes a first surface, a second surface, at least one light incident surface, and a plurality of micro-structure sets. The second surface is opposite to the first surface. The light incident surface connects the first surface to the second surface. The micro-structure sets are separately disposed on the second surface, and the micro-structure sets are not continuous in any direction parallel to the first surface. Each of the micro-structure sets includes at least one protrusive structure that protrudes from the second surface and at least one recessive structure that is recessed in the second surface. A light source module is also provided. | 11-01-2012 |
20130201721 | LIGHT SOURCE MODULE - A light source module including a light guide plate, a light-collecting structure and a light emitting device is provided. The light guide plate has a first light emitting surface, a bottom surface, a first light incident surface connecting with the bottom surface and the first light emitting surface, and an optical microstructure unit. The optical microstructure unit includes at least two optical microstructures. Each optical microstructure has a recessing part and a protruding part on the bottom surface. The light-collecting structure has a second light emitting surface connecting with the first light incident surface, a second light incident surface and a reflecting surface connecting with the second light emitting surface and the second light incident surface. A sectional line obtained by sectioning the reflecting surface along a first reference plane includes a first parabola. The reference plane is parallel to the first light emitting surface. | 08-08-2013 |
20130235608 | LIGHT SOURCE MODULE - A light source module includes an optical unit, which includes a light-emitting device, a light-guiding device and a light-converging structure. The light-guiding device has a light incident end, a light emitting end, a first curved surface connecting the light incident end and the light emitting end, and a side surface. The light-emitting device is disposed beside the light incident end. The section of the first curved surface by the side surface is a first curve. The section of the first curved surface by the reference plane perpendicular to the side surface is a second curve. The light-converging structure is disposed between the light-emitting device and the light incident end and has a first arc-convex surface and two second convex surfaces, in which the first arc-convex surface and the second convex surfaces are arranged along a direction parallel to the side-surface. | 09-12-2013 |
20130286679 | LIGHT GUIDE PLATE AND BACKLIGHT MODULE USING THE SAME - A backlight module includes a light guide plate (LGP), a light source, and at least one prism sheet. The LGP includes a light emitting surface, a bottom surface, a light incident surface, and a plurality of first microstructures on the bottom surface. Each of the first microstructure is a recessed structure and includes a first surface and a second surface. An included angle between the first surface and the bottom surface ranges from 15 degrees to 27 degrees. An included angle between the second surface and the bottom surface ranges from 50 degrees to 90 degrees. The light source provides a light beam, and an included angle between a light emitting direction of the light beam emitted from the light emitting surface of the LGP and a normal direction of the light emitting surface is greater than 30 degrees. The prism sheet is disposed above the light emitting surface. | 10-31-2013 |
20140071674 | LIGHT EMITTING APPARATUS AND LENS - A light emitting apparatus, including at least one lens, at least one light emitting element, and a light emitting section, is provided. The lens includes a first curving surface and a second curving surface opposite to the first curving surface. The light emitting element is adapted for emitting a light beam and is disposed on a side of the second curving surface. The light emitting section has a central area and is disposed on a side of the first curving surface, wherein the light beam emitted from the light emitting element is transmitted out of the light emitting apparatus through the second curving surface, the first curving surface, and the light emitting section in sequence. An optical axis of the second curving surface is close to the central area with respect to an optical axis of the first curving surface. A lens is provided as well. | 03-13-2014 |
20140085919 | VEHICLE ILLUMINATION APPARATUS - A vehicle illumination apparatus includes at least one illumination light source and at least one light guiding lens. The illumination light source is capable of providing an illumination beam. The light guiding lens includes a first light transmissive surface, a second light transmissive surface opposite to and smaller than the first light transmissive surface, an inner surrounding surface, and an outer surrounding surface. The first light transmissive surface is capable of projecting the illumination beam out of the light guiding lens. The inner surrounding surface and the second light transmissive surface are connected to each other and define a containing space configured to accommodate the illumination light source. The outer surrounding surface is connected to the inner surrounding surface and the first light transmissive surface. Besides, the outer surrounding surface has at least one light condensing region and at least one light diverging region. | 03-27-2014 |
Minghui Kuo, Hsin-Chu TW
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20120020520 | METHOD AND APPARATUS FOR DETECTING MOTION OF IMAGE IN OPTICAL NAVIGATOR - A system and method for determining a motion vector uses both a main block from an image and at least one ancillary block relating to the main block from the image. The main block and ancillary block are then tracked from image to image to provide a motion vector. The use of a composite tracking unit allows for more accurate correlation and identification of a motion vector. | 01-26-2012 |
Ming-Hui Kuo, Hsin-Chu TW
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20130082926 | IMAGE DISPLAY - There is provided an image display including a first light source, a second light source and a modulation unit. The first light source has a plurality of first point lights arranged to form a first shape for generating a predetermined spectrum signal. The second light source has a plurality of second point lights arranged to form a second shape for generating a predetermined spectrum signal. The modulation unit is for simultaneously modulating the first point lights of the first light source with a first predetermined modulation frequency and for simultaneously modulating the second point lights of the second light source with a second predetermined modulation frequency to generate a modulated predetermined spectrum. | 04-04-2013 |
Ming-Ying Kuo, Hsin-Chu TW
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20080297963 | ADJUSTABLE OVER CURRENT PROTECTION CIRCUIT WITH LOW POWER LOSS - Disclosed is an adjustable over current protection circuit which advances the timing of enabling an over current protection mechanism according to an input voltage, therefore the delay problem resulting from the non-instant response of the over current protection circuit is compensated with a low power loss. The over current protection circuit includes a voltage divider, a voltage-to-current converting circuit, an adjusting circuit and a comparing circuit. The voltage divider divides an input voltage to generate an adjusted input voltage, and the adjusted input voltage is converted into an adjusted input current by the voltage-to-current converting circuit. The adjusting circuit then adjusts a current sensing voltage according to the adjusted input current to generate an adjusted current sensing voltage. Finally, the comparing circuit compares the adjusted current sensing voltage with a predetermined over current protection reference voltage to selectively enable the over current protection mechanism according to a comparison result. | 12-04-2008 |
20110057520 | Power Management Integrated Circuit and Power Management Method - The power management integrated circuit has a startup circuit, a switch controller and a standby controller. Powered by a power source, the startup circuit provides electric power to an operational power source during a startup period. The switch controller controls a power switch to store or release energy in an energy conversion unit. Powered by the power source, the standby controller receives a standby signal. When the standby signal is asserted, the standby controller disables the startup circuit and the switch controller, thereby startup circuit not providing electric power to the operational power source and the switch controller continuously turning off the power switch. | 03-10-2011 |
20120161634 | Light Emitting Module Driving Circuit and Related Method - A light emitting module driver circuit utilized for driving a light emitting module includes a voltage dividing module, a short circuit detection module, and a driving module. A method of performing short circuit protection in the light emitting module driver circuit includes disabling the driving module during a dimming off cycle of the light emitting module driver circuit, enabling the voltage dividing module during the dimming off cycle, dividing a voltage of the light emitting module to generate a divided voltage during the dimming off cycle, and generating a short circuit protection signal according to the divided voltage during the dimming off cycle. | 06-28-2012 |
20130307606 | SUPER HIGH VOLTAGE DEVICE AND METHOD FOR OPERATING A SUPER HIGH VOLTAGE DEVICE - A super high voltage device includes a first gate, a second gate, a drain, a first source, a second source, and a third source. The first gate is used for receiving a first control signal generated from a pulse width modulation controller. The second gate is used for receiving a second control signal generated from the pulse width modulation controller. The drain is used for receiving an input voltage. First current flowing from the drain to the first source varies with the first control signal and the input voltage. The second control signal is used for controlling turning-on and turning-off of second current flowing from the drain to the second source and third current flowing from the drain to the third source. The third source is proportional to the second current. | 11-21-2013 |
Pei-Ching Kuo, Hsin-Chu TW
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20150348872 | Dummy Structure for Chip-on-Wafer-on-Substrate - Apparatus, and methods of manufacture thereof, in which metal is deposited into openings, thus forming a plurality of metal pads, a plurality of through-silicon-vias (TSVs), a plurality of metal lines, a plurality of first dummy structures, and a plurality of second dummy structures. Ones of the plurality of first dummy structures each have a first width that is at least about three times greater than a second width of each of the plurality of metal lines, and ones of the plurality of second dummy structures each have a third width that is at least about five times greater than the second width of each of the plurality of metal lines. | 12-03-2015 |
Pen-Ning Kuo, Hsin-Chu TW
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20150136946 | OPTICAL TOUCH APPARATUS AND TOUCH METHOD THEREOF - An optical touch apparatus and a touch method thereof are provided. A plurality of light sensing units are disposed between a first scanning light source and a second scanning light source, wherein the light sensing units, the first scanning light source and the second scanning light source are disposed at a same side of a touch surface. A touch position of an input tool is determined according to an intensity of a scattered light generated by an input tool and sensed by the light sensing units and generated when a first scanning beam and a second scanning beam scan the input tool. | 05-21-2015 |
20160034106 | TOUCH APPARATUS AND TOUCH SENSING METHOD THEREOF - A touch apparatus and a touch sensing method thereof are provided. Touch information generated according to received scanning beams is returned by a touch tool, and coordinates of the touch tool on a touch area is calculated according to the returned touch information. | 02-04-2016 |
Ping-Sheng Kuo, Hsin-Chu TW
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20120268442 | ELECTROPHORETIC DISPLAY APPARATUS AND IMAGE-UPDATING METHOD THEREOF - An electrophoretic display apparatus and an image-updating method thereof are provided. The electrophoretic display apparatus comprises a display panel and a source driver. The display panel comprises a plurality of pixels and a plurality of source lines, and each pixel electrode is electrically coupled to an AC common voltage through a corresponding capacitor. The capacitor comprises a plurality of charged particles. The source driver comprises a first data-latching circuit and a second data-latching circuit. Each of the data-latching circuits comprises a transistor, a capacitor and an inverter. The first data-latching circuit receives image data and a data shift-register output pulse. The second data-latching circuit is electrically coupled between an output terminal of the first data-latching circuit and a source line and is used for receiving a data output pulse. | 10-25-2012 |
Po-Chin Kuo, Hsin-Chu TW
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20130154002 | FinFETs with Multiple Threshold Voltages - A device includes a substrate, a semiconductor fin over the substrate, and a gate dielectric layer on a top surface and sidewalls of the semiconductor fin. A gate electrode is spaced apart from the semiconductor fin by the gate dielectric layer. The gate electrode includes a top portion over and aligned to the semiconductor fin, and a sidewall portion on a sidewall portion of the dielectric layer. The top portion of the gate electrode has a first work function, and the sidewall portion of the gate electrode has a second work function different from the first work function. | 06-20-2013 |
20140167187 | N Metal for FinFET - An N work function metal for a gate stack of a field effect transistor (FinFET) and method of forming the same are provided. An embodiment FinFET includes a fin supported by a semiconductor substrate, the fin extending between a source and a drain and having a channel region, and a gate stack formed over the channel region of the fin, the gate stack including an N work function metal layer comprising an oxidation layer on opposing sides of a tantalum aluminide carbide (TaAlC) layer. | 06-19-2014 |
20140377944 | FinFETs with Multiple Threshold Voltages - A device includes a substrate, a semiconductor fin over the substrate, and a gate dielectric layer on a top surface and sidewalls of the semiconductor fin. A gate electrode is spaced apart from the semiconductor fin by the gate dielectric layer. The gate electrode includes a top portion over and aligned to the semiconductor fin, and a sidewall portion on a sidewall portion of the dielectric layer. The top portion of the gate electrode has a first work function, and the sidewall portion of the gate electrode has a second work function different from the first work function. | 12-25-2014 |
20150200100 | N Metal for FinFET and Methods of Forming - An N work function metal for a gate stack of a field effect transistor (FinFET) and method of forming the same are provided. An embodiment FinFET includes a fin supported by a semiconductor substrate, the fin extending between a source and a drain and having a channel region, and a gate stack formed over the channel region of the fin, the gate stack including an N work function metal layer comprising an oxidation layer on opposing sides of a tantalum aluminide carbide (TaAlC) layer. | 07-16-2015 |
20150349080 | FinFETs with Multiple Threshold Voltages - A device includes a substrate, a semiconductor fin over the substrate, and a gate dielectric layer on a top surface and sidewalls of the semiconductor fin. A gate electrode is spaced apart from the semiconductor fin by the gate dielectric layer. The gate electrode includes a top portion over and aligned to the semiconductor fin, and a sidewall portion on a sidewall portion of the dielectric layer. The top portion of the gate electrode has a first work function, and the sidewall portion of the gate electrode has a second work function different from the first work function. | 12-03-2015 |
Po-Yu Kuo, Hsin-Chu TW
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20140092068 | OPTICAL TOUCH PANEL AND BRIGHTNESS CONTROL METHOD THEREOF - An optical touch panel includes a light source unit and a processing unit, wherein the processing unit is for executing a brightness control method. The brightness control method includes steps below. The light source unit emits at a first intensity in a touch control mode. Responding to a switching condition, the touch panel is switched into a scan mode, and the light source unit emits at a second intensity in the scan mode. | 04-03-2014 |
Shih-Chieh Kuo, Hsin-Chu TW
Patent application number | Description | Published |
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20110090199 | Display Panel Driving Circuit, Display Panel, and Driving Method thereof - By following properties that there is coupled noise, which is coupled from a display panel, within at least one common voltage used on the display panel, the at least one common voltage is fed-back into a pixel electrode driving module, and driving voltages are generated accordingly, so that the generated driving voltages carry noises closes to coupled noises of the display panel. As a result, while the driving voltages carrying noises from the at least one common voltage, the pixel electrode driving module is capable of driving a corresponding pixel electrode with a stable voltage difference, and thereby capable of relieving horizontal crosstalk and raising a display quality of the display panel. | 04-21-2011 |
20120062526 | DRIVING CIRCUIT OF A LIQUID CRYSTAL DEVICE AND RELATED DRIVING METHOD - A driving circuit of an LCD device and related driving method is provided. The driving circuit includes a thermal sensor and a power IC. The thermal sensor is configured to detect the operational temperature of the LCD device, thereby generating a corresponding thermal signal. The power IC is configured to provide a plurality of clock signals for driving a gate driver of the LCD device, and adjust the effective pulse widths of the plurality of clock signals according to the thermal signal. | 03-15-2012 |
20120105512 | METHOD FOR CONTROLLING GATE SIGNALS AND DEVICE THEREOF - A method for controlling gate signals of a liquid crystal display (LCD), including generating gate signal with a modulated pulse width according to the gate signal with a default pulse width; when the LCD is booting up, outputting the gate signal with the modulated pulse width; and when a backlight module of the LCD is turned on, switching the gate signal with the modulated pulse width to the gate signal with the default pulse width. This way, the pulse width of the gate signal is increased after the LCD is boot up and before the backlight module is turned on, enabling the LCD to be boot properly in low temperature, without the need to raise the voltage level of the gate signal. | 05-03-2012 |
20130063414 | Display and Power Supply Control Method of a Display - A display includes a display panel, a pixel driving unit and a power supply for supplying power to the pixel driving unit. The display panel includes a plurality of pixels arranged in a matrix manner. The pixel driving unit is used for driving the pixels. The power supply includes an input power source, an output capacitor for providing an output voltage, and a control unit for controlling the input power source, such that in a frame period, the input power source charges the output capacitor during the non-refreshing duration of the pixels by the input power source and stops charging the output capacitor during the refreshing duration of the pixels. | 03-14-2013 |
20140104260 | DRIVING DEVICE AND DISPLAY DEVICE AND METHOD FOR DRIVING DISPLAY PANEL - A driving device is configured for driving a display panel and includes a data driver, a plurality of switches, and an image determiner. The switch is electrically coupled between data lines of a first data line group. The data driver is configured to output data signals to the data lines of the first data line group. The data signals transferred by the data lines of the first data line group include a plurality of pulse transitions while the display panel displays an image. The image determiner is configured to determine the image displayed by the display panel and output a driving signal based on a determined result for activating a corresponding switch such that the data lines of the first data line group can perform charge sharing therebetween. Furthermore, a method for driving a display panel is disclosed herein. | 04-17-2014 |
Shih-Wei Kuo, Hsin-Chu TW
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20140210724 | CONTROL SYSTEM, MOUSE AND CONTROL METHOD THEREOF - A control system, a mouse and a control method thereof are provided. The control system comprises a dongle and the mouse. The dongle is wiredly connected to a host and has a first light source for emitting a first light. The mouse is wirelessly connected to the dongle and has a transmitter, a second light source for emitting a second light, an optical sensor and a processor. The optical sensor senses the first light at a first time interval to generate a first sensing signal and then also, senses the second light at a second time interval to generate a second sensing signal. The processor generates a first control signal and a second control signal according to the first sensing signal and the second sensing signal, respectively, and transmits them to the dongle via the transmitter so that the host receives the first and second control signals via the dongle. | 07-31-2014 |
20140313132 | MOTION DETECTING DEVICE AND THE METHOD FOR DYNAMICALLY ADJUSTING IMAGE SENSING AREA THEREOF - A motion detecting device and the method for dynamically adjusting image sensing area is disclosed. The motion detecting device includes a light source, an image capture unit and a processing unit. The image capture unit is used to capture reference image according to fixed sampling period. The processing unit is used to calculate exposure reference value of the light source and image characteristic value of reference image. The processing unit according to the exposure reference value and the image characteristic value to determine whether the surface is in first rough coefficient range or second rough coefficient range. If rough coefficient of the surface is in the first rough coefficient range, the processing unit defines first search radius or second search radius to increase or decrease the image sensing area. Otherwise, the processing unit defines third search radius or fourth search radius to increase or decrease the image sensing area. | 10-23-2014 |
Shyh-Bin Kuo, Hsin-Chu TW
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20140362064 | Active Array Substrate, Driving Method Thereof, and Liquid Crystal Display Panel Using the Same - The invention discloses an active array substrate, a driving method thereof, and an LCD using the same. The active array substrate includes a substrate, a plurality of first scan lines and second scan lines alternately disposed on the substrate, a plurality of first data lines and second data lines alternately disposed on the substrate, a plurality of first, second, and third sub-pixel electrodes, and a plurality of switches. The plurality of first scan lines and second scan lines intersect the plurality of first data lines and second data lines. Each of the second sub-pixel electrodes and one of the first sub-pixel electrodes are located at opposite sides of one of the second data lines. Each of the third sub-pixel electrodes and one of the first sub-pixel electrodes are located at opposite sides of one of the first data lines. | 12-11-2014 |
Tao-Hung Kuo, Hsin-Chu TW
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20130003025 | PROJECTION APPARATUS - A projection apparatus includes an optical engine base, a light source, a light valve, a lens module, and a fan. The light source is disposed at the optical engine base for emitting an illumination beam. The light valve is disposed at the optical engine base for converting the illumination beam into an image beam. The lens module is disposed at the optical engine base and includes a lens barrel and a lens assembly disposed in the lens barrel for converting the image beam into a projection beam. The fan is disposed at the optical engine base, and adjacent to the lens module. The fan is used for providing an air flow to cool the lens module. | 01-03-2013 |
20130271844 | PROJECTION APPARATUS - A projection apparatus including an image source, an imaging module and a beam splitting module is provided. The image source provides an image beam. The imaging module is disposed on a transmission path of the image beam and has an aperture stop. The beam splitting module is disposed on the transmission path of the image beam and located on or near the aperture stop. The beam splitting module includes a plurality of aperture stop sub-regions, and the beam splitting module separates a plurality of image sub-beams of the image beam irradiating these different aperture stop sub-regions. These image sub-beams respectively propagate towards different directions after travelling to these aperture stop sub-regions. | 10-17-2013 |
20140092483 | PROJECING LENS AND OPTICAL ENGINE - A projection lens disposed between an enlarged side and a reduced side is provided. The projection lens includes a first lens, a second lens, a third lens, a fourth lens, a fifth lens and a sixth lens, which are sequentially arranged from the enlarged side to the reduced side. Refractive powers of the first lens, the second lens, the third lens, the fourth lens, the fifth lens and the sixth lens are respectively negative, positive, positive, negative, positive and positive. A focal length of the third lens is greater than or equal to 20 mm and is less than or equal to 200 mm. An optical engine is also provided. | 04-03-2014 |
Tin-Hao Kuo, Hsin-Chu TW
Patent application number | Description | Published |
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20110193220 | Pillar Structure having a Non-Planar Surface for Semiconductor Devices - A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer. | 08-11-2011 |
20120012985 | Substrate Stand-Offs for Semiconductor Devices - Substrate stand-offs for use with semiconductor devices are provided. Active pillars and dummy pillars are formed on a first substrate such that the dummy pillars may have a height greater than a height of the active pillars. The dummy pillars act as stand-offs when joining the first substrate to a second substrate, thereby creating greater uniformity. In an embodiment, the dummy pillars may be formed simultaneously as the active pillars by forming a patterned mask having openings with a smaller width for the dummy pillars than for the active pillars. When an electro-plating process of the like is used to form the dummy and active pillars, the smaller width of the dummy pillar openings in the patterned mask causes the dummy pillars to have a greater height than the active pillars. | 01-19-2012 |
20120199966 | Elongated Bump Structure for Semiconductor Devices - An elongated bump structure for semiconductor devices is provided. An uppermost protective layer has an opening formed therethrough. A pillar is formed within the opening and extending over at least a portion of the uppermost protective layer. The portion extending over the uppermost protective layer exhibits a generally elongated shape. In an embodiment, the position of the opening relative to the portion of the bump structure extending over the uppermost protective layer is such that a ratio of a distance from an edge of the opening to an edge of the bump is greater than or equal to about 0.2. In another embodiment, the position of the opening is offset relative to center of the bump. | 08-09-2012 |
20120217632 | Extending Metal Traces in Bump-on-Trace Structures - A device includes a work piece, and a metal trace on a surface of the work piece. A Bump-on-Trace (BOT) is formed at the surface of the work piece. The BOT structure includes a metal bump, and a solder bump bonding the metal bump to a portion of the metal trace. The metal trace includes a metal trace extension not covered by the solder bump. | 08-30-2012 |
20120329264 | Reflow System and Method for Conductive Connections - A system and method for forming conductive connections is disclosed. An embodiment comprises forming conductive material on to contacts of a semiconductor substrate. The semiconductor substrate is then inverter such that the conductive material is beneath the semiconductor substrate, and the conductive material is reflowed to form a conductive bump. The reflow is performed using gravity in order to form a more uniform shape for the conductive bump. | 12-27-2012 |
20130009303 | Connecting Function Chips To A Package To Form Package-On-Package - A package-on-package (PoP) comprises a substrate with a plurality of substrate traces, a first function chip on top of the substrate connected to the substrate by a plurality of bond-on-trace connections, and a second function chip on top of the first function chip, directly connected to the substrate. Another package-on-package (PoP) comprises: a substrate with a plurality of substrate traces, a first function chip on top of the substrate connected to the substrate by a plurality of solder mask defined (SMD) connections formed on SMD bonding pads connected to solder bumps, and a second function chip on top of the first function chip, directly connected to the substrate by a plurality of bond-on-trace connections. | 01-10-2013 |
20130043583 | Dummy Flip Chip Bumps for Reducing Stress - A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer. | 02-21-2013 |
20130056869 | PILLAR STRUCTURE HAVING A NON-PLANAR SURFACE FOR SEMICONDUCTOR DEVICES - A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer. | 03-07-2013 |
20130062741 | Semiconductor Devices and Methods of Manufacturing and Packaging Thereof - Semiconductor devices and methods of manufacturing and packaging thereof are disclosed. In one embodiment, a semiconductor device includes an integrated circuit and a plurality of copper pillars coupled to a surface of the integrated circuit. The plurality of copper pillars has an elongated shape. At least 50% of the plurality of copper pillars is arranged in a substantially centripetal orientation. | 03-14-2013 |
20130147030 | Landing Areas of Bonding Structures - A device includes a first and a second package component. A metal trace is disposed on a surface of the first package component. The metal trace has a lengthwise direction. The metal trace includes a portion having an edge, wherein the edge is not parallel to the lengthwise direction of the metal trace. The second package component includes a metal pillar, wherein the second package component is disposed over the first package component. A solder region bonds the metal pillar to the metal trace, wherein the solder region contacts a top surface and the edge of the portion of the metal trace. | 06-13-2013 |
20130256874 | Elongated Bumps in Integrated Circuit Devices - A device includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. The passivation layer has a first opening overlapping the metal pad, wherein the first opening has a first lateral dimension measured in a direction parallel to a major surface of the substrate. A polymer layer is over the passivation layer and covering the edge portions of the metal pad. The polymer layer has a second opening overlapping the metal pad. The second opening has a second lateral dimension measured in the direction. The first lateral dimension is greater than the second lateral dimension by more than about 7 μm. A Under-Bump metallurgy (UBM) includes a first portion in the second opening, and a second portion overlying portions of the polymer layer. | 10-03-2013 |
20130270682 | Methods and Apparatus for Package on Package Devices with Reversed Stud Bump Through Via Interconnections - Methods and apparatus for package on package structures having stud bump through via interconnections. A structure includes an interconnect layer having a plurality of through via assemblies each including at least one stud bump are formed on conductive pads; and encapsulant surrounding the through via assembly, a first redistribution layer formed over a surface of the encapsulant and coupled to the through via assemblies and carrying connectors, and a second redistribution layer over interconnect layer at the other end of the through via assemblies, the through via assemblies extending vertically through the interconnect layer. In an embodiment the interconnect layer is mounted using the connectors to a lower package substrate to form a package on package structure. A first integrated circuit device may be mounted on the second redistribution layer of the interconnect layer. Methods for forming the interconnect layer and the package on package structures are disclosed. | 10-17-2013 |
20130270693 | Trace Layout Method in Bump-on-Trace Structures - A method and device for preventing the bridging of adjacent metal traces in a bump-on-trace structure. An embodiment comprises determining the coefficient of thermal expansion (CTE) and process parameters of the package components. The design parameters are then analyzed and the design parameters may be modified based on the CTE and process parameters of the package components. | 10-17-2013 |
20130270699 | Conical-Shaped or Tier-Shaped Pillar Connections - A pillar structure for a substrate is provided. The pillar structure may have one or more tiers, where each tier may have a conical shape or a spherical shape. In an embodiment, the pillar structure is used in a bump-on-trace (BOT) configuration. The pillar structures may have circular shape or an elongated shape in a plan view. The substrate may be coupled to another substrate. In an embodiment, the another substrate may have raised conductive traces onto which the pillar structure may be coupled. | 10-17-2013 |
20130292827 | Pillar Structure having a Non-Planar Surface for Semiconductor Devices - A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer. | 11-07-2013 |
20130320572 | Isolation Rings for Packages and the Method of Forming the Same - A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is disposed under the first package component and molded to the first and the second package components, wherein the molding material and the first package component form an interface. An isolation region includes a first edge, wherein the first edge of the isolation region contacts a first edge of the first package component and a first edge of the molding material. The isolation has a bottom lower than the interface. | 12-05-2013 |
20140077358 | Bump Structure and Method of Forming Same - An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent. | 03-20-2014 |
20140077359 | Ladder Bump Structures and Methods of Making Same - An embodiment ladder bump structure includes an under bump metallurgy (UBM) feature supported by a substrate, a copper pillar mounted on the UBM feature, the copper pillar having a tapering curved profile, which has a larger bottom critical dimension (CD) than a top critical dimension (CD) in an embodiment, a metal cap mounted on the copper pillar, and a solder feature mounted on the metal cap. | 03-20-2014 |
20140077360 | Interconnection Structure and Method of Forming Same - An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal ladder bump mounted on the under bump metallurgy feature, the metal ladder bump having a first tapering profile, and a substrate trace mounted on a substrate, the substrate trace having a second tapering profile and coupled to the metal ladder bump through direct metal-to-metal bonding. An embodiment chip-to-chip structure may be fabricated in a similar fashion. | 03-20-2014 |
20140077365 | Metal Bump and Method of Manufacturing Same - An embodiment bump structure includes a contact element formed on a substrate, a passivation layer overlying the substrate, the passivation layer having a passivation opening exposing the contact element a polyimide layer overlying the passivation layer, the polyimide layer having a polyimide opening exposing the contact element an under bump metallurgy (UMB) feature electrically coupled to the contact element, the under bump metallurgy feature having a UBM width, and a copper pillar on the under bump metallurgy feature, a distal end of the copper pillar having a pillar width, the UBM width greater than the pillar width. | 03-20-2014 |
20140159232 | Apparatus and Method for Three Dimensional Integrated Circuits - A structure comprises a substrate comprising a plurality of traces on top of the substrate, a plurality of connectors formed on a top surface of a semiconductor die, wherein the semiconductor die is formed on the substrate and coupled to the substrate through the plurality of connectors and a dummy metal structure formed at a corner of a top surface of the substrate, wherein the dummy metal structure has two discontinuous sections. | 06-12-2014 |
20140167253 | Semiconductor Devices, Methods of Manufacture Thereof, and Packaged Semiconductor Devices - Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. In one embodiment, a semiconductor device includes a substrate and conductive traces disposed over the substrate. Each of the conductive traces has a bottom region proximate the substrate and a top region opposite the bottom region. The top region has a first width and the bottom region has a second width. The second width is greater than the first width. | 06-19-2014 |
20140179062 | Isolation Rings for Packages and the Method of Forming the Same - A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is disposed under the first package component and molded to the first and the second package components, wherein the molding material and the first package component form an interface. An isolation region includes a first edge, wherein the first edge of the isolation region contacts a first edge of the first package component and a first edge of the molding material. The isolation has a bottom lower than the interface. | 06-26-2014 |
20140186591 | Solder Mask Shape for BOT Laminate Packages - A device is provided. The device may comprise an integrated circuit package. The integrated circuit package may comprise a first layer and a solder mask. The first layer may comprise a top surface wherein the solder mask is disposed on the top surface of the first layer. The solder mask may comprise a vertical edge. The vertical edge may form an angle between the top surface of the first layer and the vertical edge of not less than 90 degrees. The angle may be not less than 120 degrees or not less than 150 degrees. | 07-03-2014 |
20140252600 | Treating Copper Surfaces for Packaging - A die has a top surface, and a metal pillar having a portion protruding over the top surface of the die. A sidewall of the metal pillar has nano-wires. The die is bonded to a package substrate. An underfill is filled into the gap between the die and the package substrate. | 09-11-2014 |
20140252614 | Surface Treatment Method and Apparatus for Semiconductor Packaging - A surface treatment and an apparatus for semiconductor packaging are provided. In an embodiment, a surface of a conductive layer is treated to create a roughened surface. In one example, nanowires are formed on a surface of the conductive layer. In the case of a copper conductive layer, the nanowires may include a CuO layer. In another example, a complex compound is formed on a surface of the conductive layer. The complex compound may be formed using, for example, thiol and trimethyl phosphite. | 09-11-2014 |
20140291838 | Design Scheme for Connector Site Spacing and Resulting Structures - A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 μm. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 μm. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 μm. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad. | 10-02-2014 |
20140302669 | Pillar Structure having a Non-Planar Surface for Semiconductor Devices - A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer. | 10-09-2014 |
20140346673 | Methods and Apparatus for bump-on-trace Chip Packaging - Methods and apparatuses for a attaching a first substrate to a second substrate are provided. In some embodiments, a first substrate has a protective layer, such as a solder mask, around a die attach area, at which a second substrate is attached. A keep-out region (e.g., an area between the second substrate and the protective layer) is a region around the second substrate in which the protective layer is not formed or removed. The keep-out region is sized such that a sufficient gap exists between the second substrate and the protective layer to place an underfill between the first substrate and the second substrate while reducing or preventing voids and while allowing traces in the keep-out region to be covered by the underfill. | 11-27-2014 |
20150072476 | Methods and Apparatus for Package on Package Devices with Reversed Stud Bump Through Via Interconnections - Methods and apparatus for package on package structures having stud bump through via interconnections. A structure includes an interconnect layer having a plurality of through via assemblies each including at least one stud bump are formed on conductive pads; and encapsulant surrounding the through via assembly, a first redistribution layer formed over a surface of the encapsulant and coupled to the through via assemblies and carrying connectors, and a second redistribution layer over interconnect layer at the other end of the through via assemblies, the through via assemblies extending vertically through the interconnect layer. In an embodiment the interconnect layer is mounted using the connectors to a lower package substrate to form a package on package structure. A first integrated circuit device may be mounted on the second redistribution layer of the interconnect layer. Methods for forming the interconnect layer and the package on package structures are disclosed. | 03-12-2015 |
20150104903 | Treating Copper Surfaces for Packaging - A die has a top surface, and a metal pillar having a portion protruding over the top surface of the die. A sidewall of the metal pillar has nano-wires. The die is bonded to a package substrate. An underfill is filled into the gap between the die and the package substrate. | 04-16-2015 |
20150130050 | Substrate Design with Balanced Metal and Solder Resist Density - A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer overlying the middle layer, and a bottom metal layer underlying the middle layer. All metal layers overlying the middle layer have a first total metal density that is equal to a sum of all densities of all metal layers over the middle layer. All metal layers underlying the middle layer have a second total metal density that is equal to a sum of all densities of all metal layers under the middle layer. An absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1. | 05-14-2015 |
20150130051 | Bump-on-Trace Structures with High Assembly Yield - A package includes first package component, which further includes a first metal trace at a surface of the first package component, with the first metal trace having a trace width measured in a direction perpendicular to a lengthwise direction of the first metal trace. The first package component further includes a second metal trace at the surface of the first package component. The first metal trace and the second metal trace are parallel to each other. A second package component is overlying the first package component, wherein the second package component includes a metal bump. A solder region bonds the metal bump to the first metal trace, wherein the solder region contacts a top surface and sidewalls of the first portion of the first metal trace. A ratio of a volume of the solder region to the trace width is between about 1,100 μm | 05-14-2015 |
20150187719 | Trace Design for Bump-on-Trace (BOT) Assembly - A bump-on-trace (BOT) interconnection in a package and methods of making the BOT interconnection are provided. An embodiment BOT interconnection comprises a landing trace including a distal end, a conductive pillar extending at least to the distal end of the landing trace; and a solder feature electrically coupling the landing trace and the conductive pillar. In an embodiment, the conductive pillar overhangs the end surface of the landing trace. In another embodiment, the landing trace includes one or more recesses for trapping the solder feature after reflow. Therefore, a wetting area available to the solder feature is increased while permitting the bump pitch of the package to remain small. | 07-02-2015 |
20150194379 | Protrusion Bump Pads for Bond-on-Trace Processing - An embodiment apparatus includes a dielectric layer in a die, a conductive trace in the dielectric layer, and a protrusion bump pad on the conductive trace. The protrusion bump pad at least partially extends over the dielectric layer, and the protrusion bump pad includes a lengthwise axis and a widthwise axis. A ratio of a first dimension of the lengthwise axis to a second dimension of the widthwise axis is about 0.8 to about 1.2 | 07-09-2015 |
20150262882 | Isolation Rings for Packages and the Method of Forming the Same - A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is disposed under the first package component and molded to the first and the second package components, wherein the molding material and the first package component form an interface. An isolation region includes a first edge, wherein the first edge of the isolation region contacts a first edge of the first package component and a first edge of the molding material. The isolation has a bottom lower than the interface. | 09-17-2015 |
20150325542 | CONDUCTIVE CONTACTS HAVING VARYING WIDTHS AND METHOD OF MANUFACTURING SAME - A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation opening exposing the contact element. The bump structure also includes a polyimide layer overlying the passivation layer and an under bump metallurgy (UBM) feature electrically coupled to the contact element. The polyimide layer has a polyimide opening exposing the contact element, and the under bump metallurgy feature has a UBM width. The bump structure further includes a copper pillar on the under bump metallurgy feature. A distal end of the copper pillar has a pillar width, and the UBM width is greater than the pillar width. | 11-12-2015 |
20150357301 | Bump Structure and Method of Forming Same - An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent. | 12-10-2015 |
20150380332 | Substrate Design with Balanced Metal and Solder Resist Density - A package includes a package substrate, which includes a middle layer selected from the group consisting of a core and a middle metal layer, a top metal layer overlying the middle layer, and a bottom metal layer underlying the middle layer. All metal layers overlying the middle layer have a first total metal density that is equal to a sum of all densities of all metal layers over the middle layer. All metal layers underlying the middle layer have a second total metal density that is equal to a sum of all densities of all metal layers under the middle layer. An absolute value of a difference between the first total metal density and the second total metal density is lower than about 0.1. | 12-31-2015 |
20160035591 | Methods and Apparatus for bump-on-trace Chip Packaging - Methods and apparatuses for a attaching a first substrate to a second substrate are provided. In some embodiments, a first substrate has a protective layer, such as a solder mask, around a die attach area, at which a second substrate is attached. A keep-out region (e.g., an area between the second substrate and the protective layer) is a region around the second substrate in which the protective layer is not formed or removed. The keep-out region is sized such that a sufficient gap exists between the second substrate and the protective layer to place an underfill between the first substrate and the second substrate while reducing or preventing voids and while allowing traces in the keep-out region to be covered by the underfill. | 02-04-2016 |
20160071812 | Design Scheme for Connector Site Spacing and Resulting Structures - A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 μm. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 μm. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 μm. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad. | 03-10-2016 |
20160086901 | Bump-on-Trace Structures with High Assembly Yield - A package includes first package component, which further includes a first metal trace at a surface of the first package component, with the first metal trace having a trace width measured in a direction perpendicular to a lengthwise direction of the first metal trace. The first package component further includes a second metal trace at the surface of the first package component. The first metal trace and the second metal trace are parallel to each other. A second package component is overlying the first package component, wherein the second package component includes a metal bump. A solder region bonds the metal bump to the first metal trace, wherein the solder region contacts a top surface and sidewalls of the first portion of the first metal trace. A ratio of a volume of the solder region to the trace width is between about 1,100 μm | 03-24-2016 |
Tzu-Shou Kuo, Hsin-Chu TW
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20140176664 | PROJECTION APPARATUS WITH VIDEO CONFERENCE FUNCTION AND METHOD OF PERFORMING VIDEO CONFERENCE USING PROJECTION APPARATUS - A projection apparatus includes a projection module, a network module, a video-audio capturing module, a conference module and a processor. The network module provides a network interface. The video-audio capturing module is configured to capture an image and voice of a local user, and accordingly generates local video-audio data. The conference module provides the video conference function. The processor is electrically connected to the projection module, the network module, the video-audio capturing module and the conference module. When the processor enables the video conference function, the projection apparatus establishes a connection with a remote apparatus through the network interface, in order to receive a remote video-audio data of a remote user from the remote apparatus, and transmit the local video-audio data to the remote apparatus. The projection module projects an image corresponding to the remote video-audio data onto a projection surface. | 06-26-2014 |
20140184725 | TELEPHONE WITH VIDEO FUNCTION AND METHOD OF PERFORMING VIDEO CONFERENCE USING TELEPHONE - A telephone with a video function is provided, including a projection module, a network module, a video-audio capturing module, a conference module and a processor. The network module provides a network interface. The video-audio capturing module is configured to capture an image and voice of a local user, and accordingly generates local video-audio data. The conference module provides the video conference function. The processor is electrically connected to the projection module, the network module, the video-audio capturing module and the conference module. When the processor enables the video conference function of the conference module, the telephone establishes a connection with a remote apparatus through the network interface, in order to receive a remote video-audio data of a remote user from the remote apparatus, and transmit the local video-audio data to the remote apparatus. The projection module projects an image corresponding to the remote video-audio data onto a projection surface. | 07-03-2014 |
Tzu-Yin Kuo, Hsin-Chu TW
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20130049640 | MIRROR ELECTROLUMINESCENT DISPLAY PANEL - A mirror electroluminescent display panel includes an array substrate, a plurality of driving devices, a plurality of electroluminescent devices, and a cover substrate. The driving devices and the electroluminescent devices are disposed on the array substrate. Each electroluminescent device includes a first electrode electrically connected to the corresponding driving device, a light-emitting layer disposed on the first electrode, and a second electrode disposed on the light-emitting layer. The cover substrate and the array substrate are disposed oppositely. The cover substrate has a plurality of transmission regions, and a reflection region disposed between adjacent transmission regions, and each of the transmission regions is corresponding to each of the light-emitting layers, respectively. | 02-28-2013 |
Wei-Hung Kuo, Hsin-Chu TW
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20100066951 | Flexible liquid crystal display panel and method for manufacturing the same - A flexible liquid crystal display panel and method for manufacturing the same are provided. The flexible liquid crystal display panel includes a rigid substrate, a flexible substrate and a liquid crystal layer disposed therebetween. | 03-18-2010 |
20110157071 | CAPACITIVE TOUCH DISPLAY PANEL AND CAPACITIVE TOUCH BOARD - A capacitive touch display panel includes a display panel, a touch sensing unit, and a plurality of floating gate type ESD protection devices. The touch sensing unit includes a plurality of first sensing pads and second sensing pads. Each floating gate type ESD protection device is disposed between two adjacent first sensing pads and between two adjacent second sensing pads. The two adjacent first sensing pads are electrically disconnected from each other, and the two adjacent second sensing pads are electrically disconnected from each other. | 06-30-2011 |
20110157084 | CAPACITIVE TOUCH DISPLAY PANEL AND CAPACITIVE TOUCH BOARD - A capacitive touch display panel includes a display panel, a touch sensing unit, and a plurality of diode ESD protection devices. The touch sensing unit includes a plurality of first sensing pads and second sensing pads. Each diode ESD protection device is disposed between two adjacent first sensing pads and between two adjacent second sensing pads. The two adjacent first sensing pads are electrically disconnected from each other, and the two adjacent second sensing pads are electrically disconnected from each other. | 06-30-2011 |
20110254804 | TOUCH PANEL, TOUCH DISPLAY PANEL AND REPAIRING METHOD THEREOF - A touch display panel contains a display panel and a touch sensing array. The touch sensing array is disposed on the display panel, wherein the touch sensing array includes a plurality of first transparent sensing series, a plurality of second transparent sensing series, and a plurality of conductive repair marks. The first transparent sensing series are arranged along a first direction. Each of the first transparent sensing series includes a plurality of first transparent sensing pads electrically connected with each other; the second transparent sensing series are arranged along a second direction. Each of the second transparent sensing series includes a plurality of second transparent sensing pads electrically connected with each other, and each first transparent sensing pad is isolated from each second transparent sensing pad. The conductive repair marks are disposed corresponding to the first transparent sensing pads or the second transparent sensing pads. | 10-20-2011 |
20120169628 | TOUCH PANEL - A touch panel includes an insulating base, a plurality of first sensing electrodes, a plurality of second sensing electrodes and a plurality of third sensing electrodes. The insulating base has a first surface and a second surface. The first sensing electrodes and the second sensing electrodes are disposed on the first surface of the insulating base, and electrically isolated from each other. The third sensing electrodes are disposed on the second surface of the insulating base, and each third sensing electrode at least partially overlaps a portion of the first sensing electrodes and a portion of the second sensing electrodes. | 07-05-2012 |
20140133046 | DISPLAY DEVICE - A display device includes a substrate, a light shielding layer, at least one fading pattern and a display module. The display module is disposed on the substrate and has a display area. The light shielding layer is disposed on a periphery of the substrate and has a first side and a second side, wherein the first side is opposite to the second side. The at least one fading pattern is disposed on the substrate, is adjacent to at least one side of the first side and the second side of the light shielding layer, and does not overlap the display area of the display module. Each fading pattern includes N light transmissible areas, the N light transmissible areas are adjacent to each other, and transmittances of the N light transmissible areas are different from each other, wherein N is a positive integer larger than one. | 05-15-2014 |
Wu-An Kuo, Hsin-Chu TW
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20100174933 | System and Method for Reducing Processor Power Consumption - A system and method for reducing active power in processors is disclosed. A method embodiment comprises the steps of determining when a particular logic block is inactive, determining the powered state of the particular logic block, isolating the particular logic block from a main processor core, and powering off the particular logic block. When the system needs the particular logic block, the method further comprises reactivating the block. A system embodiment comprises software and a processor coupled to a clock control module, an isolation control module and a header/footer module, operable to isolate a particular logic block and power off a particular logic block, thereby reducing power. Another embodiment comprises a logic module coupled to a clock by a clock gating module, an isolation module for isolating the logic module, a header/footer module for disabling power to the logic module, and a power and clock gating control module for controlling the clock gating module and the header/footer module. | 07-08-2010 |
20100289111 | System and Method for Designing Cell Rows - A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard cell may have a height smaller than the cell row or else may have a height that is larger than the cell row. Vertical fillers and horizontal fillers are utilized to extend and connect the standard cell to adjacent cells without having to redesign the entire cell row. | 11-18-2010 |
20140115553 | System and Method for Designing Cell Rows - A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard cell may have a height smaller than the cell row or else may have a height that is larger than the cell row. Vertical fillers and horizontal fillers are utilized to extend and connect the standard cell to adjacent cells without having to redesign the entire cell row. | 04-24-2014 |
20150213183 | System and Method for Designing Cell Rows - A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard cell may have a height smaller than the cell row or else may have a height that is larger than the cell row. Vertical fillers and horizontal fillers are utilized to extend and connect the standard cell to adjacent cells without having to redesign the entire cell row. | 07-30-2015 |
Yian-Liang Kuo, Hsin-Chu TW
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20100072635 | Protecting Sidewalls of Semiconductor Chips using Insulation Films - A method of forming an integrated circuit structure includes providing a wafer having a first semiconductor chip, a second semiconductor chip, and a scribe line between and adjoining the first semiconductor chip and the second semiconductor chip; forming a notch in the scribe line, wherein the notch has a bottom no higher than a top surface of a semiconductor substrate in the wafer; forming a first insulation film over the wafer, wherein the first insulation film extends into the notch; removing a portion of the first insulation film from a center of the notch, wherein a remaining portion of the first insulation film comprises an edge in the notch; and sawing the wafer to separate the first semiconductor chip and the second semiconductor chip. | 03-25-2010 |
20160086867 | Integrated Circuit Packages and Methods for Forming the Same - A method includes forming an electrical connector over a substrate of a wafer, and molding a polymer layer, with at least a portion of the electrical connector molded in the polymer layer. A first sawing step is performed to form a trench in the polymer layer. After the first sawing step, a second sawing step is performed to saw the wafer into a plurality of dies. | 03-24-2016 |
Ying-Hao Kuo, Hsin-Chu TW
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20140206110 | Etchant and Etching Process - A system and method of etching a semiconductor device are provided. Etching solution is sampled and analyzed by a monitoring unit to determine a concentration of components within the etching solution, such as an oxidant concentration. Then, based upon such measurement, a makeup amount of the components may be added be a makeup unit to the etching solution to control the concentration of the components within the etching system. | 07-24-2014 |
20140206191 | Etchant and Etching Process - A system and method for manufacturing semiconductor devices is provided. An embodiment comprises using an etchant to remove a portion of a substrate to form an opening with a 45° angle with a major surface of the substrate. The etchant comprises a base, a surfactant, and an oxidant. The oxidant may be hydrogen peroxide. | 07-24-2014 |
20140269804 | Package Structure and Methods of Forming Same - A semiconductor device, a package structure, and methods of forming the same are disclosed. An embodiment is a semiconductor device comprising a first optical device over a first substrate, a vertical waveguide on a top surface of the first optical device, and a second substrate over the vertical waveguide. The semiconductor device further comprises a lens capping layer on a top surface of the second substrate, wherein the lens capping layer is aligned with the vertical waveguide, and a second optical device over the lens capping layer. | 09-18-2014 |
20140269805 | Light Coupling Device and Methods of Forming Same - An embodiment is a semiconductor device comprising an optical device over a first substrate, a vertical waveguide on a top surface of the optical device, the vertical waveguide having a first refractive index, and a capping layer over the vertical waveguide, the capping layer configured to be a lens for the vertical waveguide and the capping layer having a second refractive index. | 09-18-2014 |
20140363121 | Integrated Metal Grating - An integrated circuit includes a substrate, a metal grating disposed over the substrate, and a waveguide layer disposed over or under the metal grating. The metal grating is arranged to change a propagation direction of an optical signal and the waveguide layer is arranged to guide the optical signal to a desired direction. | 12-11-2014 |
20150155260 | Temporary Bonding Scheme - A method includes filling a trench formed in a first integrated circuit carrier with temporary bonding material to form a temporary bonding layer. At least one chip is bonded over the temporary bonding layer. | 06-04-2015 |
20150212270 | Package Structure and Methods of Forming Same - A semiconductor device, a package structure, and methods of forming the same are disclosed. An embodiment is a semiconductor device comprising a first optical device over a first substrate, a vertical waveguide on a top surface of the first optical device, and a second substrate over the vertical waveguide. The semiconductor device further comprises a lens capping layer on a top surface of the second substrate, wherein the lens capping layer is aligned with the vertical waveguide, and a second optical device over the lens capping layer. | 07-30-2015 |
20160056086 | Temporary Bonding Scheme - A method includes filling a trench formed in a first integrated circuit carrier with temporary bonding material to form a temporary bonding layer. At least one chip is bonded over the temporary bonding layer. | 02-25-2016 |
Ying-Tse Kuo, Hsin-Chu TW
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20120131275 | NETWORK-ATTACHED STORAGE SYSTEM - The invention discloses a network-attached storage system including an interface module, a plurality of storage devices and a storage module. The interface module is configured to be attached to a network. The interface module is for receiving a transmission protocol information transmitted over the network, and processing the information into storage data and access instructions. The storage module is for receiving the storage data and the access instructions, and controlling, according to the access instructions, access of the storage data to the primary storage devices through a transmission interface. | 05-24-2012 |
Yu-Chieh Kuo, Hsin-Chu TW
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20150108483 | DISPLAY PANEL - A display panel includes a first substrate structure, a second substrate structure and a non-self-luminous display medium layer. The first substrate structure includes a first substrate, a first common electrode, a pixel electrode and a first alignment film. The second substrate structure is disposed opposite to the first substrate structure. The second substrate structure includes a second substrate, a second common electrode and a second alignment film. The non-self-luminous display medium layer is interposed between the first alignment film and the second alignment film. A first capacitance is formed between the first common electrode and the pixel electrode, a second capacitance is formed between the pixel electrode and the second common electrode, and a ratio of the second capacitance to the first capacitance is substantially between 0.7 and 1.3. | 04-23-2015 |
Yung-Liang Kuo, Hsin-Chu TW
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20080272372 | Test structures for stacking dies having through-silicon vias - A semiconductor die including a test structure is provided. The semiconductor die includes a loop-back formed on a surface of the semiconductor die. The loop-back structure includes a first bonding pad on a first surface; and a second bonding pad on the first surface, wherein the first and the second bonding pads are electrically disconnected from integrated circuit devices in the semiconductor die. A conductive feature electrically shorts the first and the second bonding pads. An additional die including an interconnect structure is bonded onto the semiconductor die. The interconnect structure includes a third and a fourth bonding pad bonded to the first and the second bonding pads, respectively. Through-wafer vias in the additional die are further connected to the third and fourth bonding pads. | 11-06-2008 |