Patent application number | Description | Published |
20100008620 | Optical Clock Signal Distribution Using Through-Silicon Vias - An integrated circuit structure includes a semiconductor chip including a front surface and a back surface; a via extending from the back surface of the semiconductor chip into the semiconductor chip, wherein the via is light transparent; and a photon detector in the semiconductor chip and exposed to the via. | 01-14-2010 |
20100140805 | Bump Structure for Stacked Dies - A bump structure that may be used for stacked die configurations is provided. Through-silicon vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-silicon vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-silicon vias. The isolation film is thinned to re-expose the through-silicon vias. Bump pads and redistribution lines are formed on the backside of the semiconductor substrate providing an electrical connection to the through-silicon vias. Another isolation film is deposited and patterned, and a barrier layer is formed to provide contact pads for connecting to an external device, e.g., another die/wafer or circuit board. | 06-10-2010 |
20100276787 | Wafer Backside Structures Having Copper Pillars - An integrated circuit structure includes a semiconductor substrate having a front side and a backside, and a conductive via penetrating the semiconductor substrate. The conductive via includes a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is on the backside of the semiconductor substrate and electrically connected to the back end of the conductive via. A passivation layer is over the RDL, with an opening in the passivation layer, wherein a portion of the RDL is exposed through the opening. A copper pillar has a portion in the opening and electrically connected to the RDL. | 11-04-2010 |
20100330798 | Formation of TSV Backside Interconnects by Modifying Carrier Wafers - An integrated circuit structure includes a semiconductor wafer, which includes a first notch extending from an edge of the semiconductor wafer into the semiconductor wafer. A carrier wafer is mounted onto the semiconductor wafer. The carrier wafer has a second notch overlapping at least a portion of the first notch. A side of the carrier wafer facing the semiconductor wafer forms a sharp angle with an edge of the carrier wafer. The carrier wafer has a resistivity lower than about 1×10 | 12-30-2010 |
20110165776 | Bond Pad Connection to Redistribution Lines Having Tapered Profiles - An integrated circuit structure includes a semiconductor substrate having a front side and a backside. A through-silicon via (TSV) penetrates the semiconductor substrate, wherein the TSV has a back end extending to the backside of the semiconductor substrate. A redistribution line (RDL) is formed over the backside of the semiconductor substrate and connected to the back end of the TSV. A passivation layer is over the RDL with an opening formed in the passivation layer, wherein a portion of a top surface of the RDL and a sidewall of the RDL are exposed through the opening. A metal finish is formed in the opening and contacting the portion of the top surface and the sidewall of the RDL. | 07-07-2011 |
20110299809 | Optical Clock Signal Distribution Using Through-Silicon Vias - An integrated circuit structure includes a semiconductor chip including a front surface and a back surface; a via extending from the back surface of the semiconductor chip into the semiconductor chip, wherein the via is light transparent; and a photon detector in the semiconductor chip and exposed to the via. | 12-08-2011 |
20140130962 | THIN WAFER HANDLING METHOD - A method includes receiving a carrier with a release layer formed thereon. A first adhesive layer is formed on a wafer. A second adhesive layer is formed over the first adhesive layer or over the release layer. The carrier and the wafer are bonded with the release layer, the first adhesive layer, and the second adhesive layer in between the carrier and the wafer. | 05-15-2014 |
20150143324 | Semiconductor Device Design Methods and Conductive Bump Pattern Enhancement Methods - Semiconductor device design methods and conductive bump pattern enhancement methods are disclosed. In some embodiments, a method of designing a semiconductor device includes designing a conductive bump pattern design, and implementing a conductive bump pattern enhancement algorithm on the conductive bump pattern design to create an enhanced conductive bump pattern design. A routing pattern is designed based on the enhanced conductive bump pattern design. A design rule checking (DRC) procedure is performed on the routing pattern. | 05-21-2015 |