Patent application number | Description | Published |
20080252783 | Device for separating synchronous signal and method thereof - In a device for separating a synchronous signal in a video signal, a capacitor receives the video signal to obtain a coupling signal, a level determining circuit receives the coupling signal and compares a voltage level of the coupling signal with a number of reference voltages. The reference voltages define several reference voltage ranges, one of which is a predetermined reference voltage range. The level determining circuit outputs an adjusting signal according to a reference voltage range corresponding to a minimum voltage level of the coupling signal within a predetermined time period. A level adjusting circuit has several current sources for receiving the adjusting signal and thus controls the current sources to adjust a DC level of the coupling signal. A synchronous signal separating circuit separates the synchronous signal from the coupling signal when the minimum voltage level of the coupling signal is substantially within the predetermined reference voltage range. | 10-16-2008 |
20090066367 | INPUT OUTPUT DEVICE FOR MIXED-VOLTAGE TOLERANT - An input output device coupled between a core circuit and a pad and including an output cell, an input cell, and a pre-driver. The output cell includes an output stage and a voltage level converter. The output stage includes a first transistor and a second transistor connected to the first transistor in serial between a first supply voltage and a second voltage. The voltage level converter generates a first gate voltage to the first transistor according to the first voltage and a data signal. When the first supply voltage is increased, the first gate voltage is increased. When the data signal is at a high level, the first transistor is turned on. The input cell includes a pull unit and a first N-type transistor. The pre-driver turns off the first and the second transistors. | 03-12-2009 |
20090108870 | I/O BUFFER CIRCUIT - An output buffer circuit is provided. The output buffer circuit receives a control signal (OE) and a data signal (Dout) from a first core circuit ( | 04-30-2009 |
20090112499 | DEVICE FOR JITTER MEASUREMENT AND METHOD THEREOF - The device for jitter measurement and a method thereof are provided. The device for jitter measure includes a signal retrieving module, a signal amplifying module, an edge detecting module, and a time-to-digital converting module. The signal retrieving module receives a signal-under-test, and retrieves a first pulse signal having a pulse width equal to a period of the signal-under-test. The signal amplifying module amplifies the pulse width of the first pulse signal and thereby generates a second pulse signal. The edge detecting module detects a rising edge and a falling edge of the second pulse signal, and generates a first indication signal and a second indication signal according to the respective detected results. The time-to-digital converting module converts the pulse width of the second pulse signal existed in time domain to a digital signal according to the first indication signal and the second indication signal. | 04-30-2009 |
20100034330 | CLOCK GENERATING DEVICE AND METHOD THEREOF - A clock generating device includes: a frequency divider having an input node coupled to a transmission interface for generating a reference clock signal according to an input data received from the transmission interface; and a clock/data recovery circuit having a data input node coupled to the transmission interface and a reference clock input node coupled to an output node of the frequency divider, for generating an output clock signal according to one of the input data received at the data input node and the reference clock signal received at the reference clock input node. | 02-11-2010 |
20100085089 | PHASE-LOCKED LOOP CIRCUIT - A phase-locked loop circuit for generating an output signal includes a phase frequency detector (PFD), a processing module, and a clock generator. The PFD is implemented for generating a plurality of indicating signals according to a first reference signal and a feedback signal, where the feedback signal is generated according to the output signal. The processing module is coupled to the PFD, and is implemented for generating a control signal according to the indicating signals and a plurality of clock signals, where the clock signals have an identical frequency but different phases. The clock generator is coupled to the processing module, and is implemented for generating the clock signals according to the control signal. The output signal is generated according to a specific clock signal selected from the clock signals. | 04-08-2010 |
20100097117 | Mixed-voltage I/O buffer - A mixed-voltage input/output (I/O) buffer includes an output buffer circuit. The output buffer circuit includes an output stage circuit, a gate-tracking circuit and a floating N-well circuit. The output stage circuit includes stacked pull-up P-type transistors and stacked pull-down N-type transistors, in which a first P-type transistor of the stacked pull-up P-type transistors and a first N-type transistor of the stacked pull-down N-type transistors are coupled to an I/O pad. The gate-tracking circuit controls gate voltage of the first P-type transistor in accordance with a voltage of the I/O pad to prevent leakage current. The floating N-well circuit provides N-well voltages for an N-well of the first P-type transistor and an N-well of a second P-type transistor, controlling gate voltage of the first P-type transistor, of the gate-tracking circuit to prevent leakage current. | 04-22-2010 |