Patent application number | Description | Published |
20110104322 | TEMPLATES USED FOR NANOIMPRINT LITHOGRAPHY AND METHODS FOR FABRICATING THE SAME - Provided are a template used for nanoimprint lithography and a method for fabricating the same. A raised first deposition layer pattern including at least one downwardly sloped side surface is formed on a substrate. A second deposition layer pattern covering the side surface of the raised first deposition layer pattern and progressively decreasing in width downward along the side surface of the raised first deposition layer pattern is formed. A third deposition layer is formed on the entire surface of a structure on which the second deposition layer pattern. A second deposition layer nano pattern between the raised first deposition layer pattern and a planarized third deposition layer is formed by planarizing the third deposition layer to expose upper surfaces of the raised first deposition layer pattern and the second deposition layer pattern. An intaglio nano pattern defined by side surfaces sloped downward from upper surfaces of the raised first deposition layer pattern and the planarized third deposition layer to the surface of the substrate is formed by removing the second deposition layer nano pattern. | 05-05-2011 |
20110136338 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a via hole in a semiconductor substrate, forming an isolation layer on an inner side of the via hole, forming a diffusion barrier layer over an upper portion of the semiconductor substrate and the inner side of the via hole where the isolation layer is formed, arranging a solvent, which contains electrically charged metal particles, on the semiconductor substrate where the diffusion barrier layer is formed, and filling the via hole with the metal particles by moving the metal particles using applied external force. The applied external force said includes a voltage causing an electric current to flow between the semiconductor substrate and the solvent, an electrical field applied between the semiconductor substrate and the solvent, or a magnetic field applied between the semiconductor substrate and the solvent. | 06-09-2011 |
20120056331 | METHODS OF FORMING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICES FORMED BY THE SAME - Provided are a method of forming a semiconductor device including a via and a semiconductor device formed by the same. In the method, by forming an unseeded layer that covers a seed layer disposed on a substrate and at a side wall of a via hole, exposes the seed layer disposed at a bottom of the via hole, and cannot serve as a seed, a plated layer configuring the via is formed upward from the seed layer in a bottom-up growth process, and thus, a void is not formed. Also, an inlet of the via hole is not blocked by using the bottom-up growth process, and thus, an electroplating speed can increase, thereby shortening a time taken in filling the via hole with a metal. | 03-08-2012 |
20120086132 | METHOD OF MANUFACTURING VIA ELECTRODE - Provided is a method of manufacturing a via electrode by which productivity and production yield can be augmented or maximized. The method of the present invention includes: forming a via hole at a substrate; forming a catalyst layer at a sidewall and a bottom of the via hole; and forming a graphene layer in the via hole by exposing the catalyst layer to a solution mixed with graphene particles. | 04-12-2012 |
20120137907 | INTAGLIO PRINTING PLATE INCLUDING SUPPLEMENTARY PATTERN AND METHOD FOR FABRICATING THE SAME - Disclosed is an intaglio printing plate including: a pattern portion where a to-be-printed pattern is located; a non-pattern portion corresponding to a remaining area other than the pattern portion; and a supplementary pattern portion having a repetitive pattern with a predetermined form, wherein at least a part of the pattern portion is divided by a pattern structure that is formed by the supplementary pattern portion. | 06-07-2012 |
20120140350 | PRINTING PLATE AND MIRROR THEREOF - Disclosed are a printing plate and a mirror thereof, the printing plate including: printing portions for transferring an immersed solution, the printing portions being formed flat and arranged at regular intervals on one side of an upper part of the printing plate; and non-printing portions corresponding to a remaining area other than the printing portions, the non-printing portions being formed with at least two concavities and convexities respectively and arranged at regular intervals on the other side of the upper part of the printing plate. | 06-07-2012 |
20120168723 | ELECTRONIC DEVICES INCLUDING GRAPHENE AND METHODS OF FORMING THE SAME - Methods of forming a graphene layer are provided. The method includes sequentially forming a seed layer and a protection layer on a substrate, patterning the protection layer and the seed layer to form a protection pattern and a seed pattern having a first length in a first direction and a second length in a second direction perpendicular to the first direction, and forming a graphene material on at least one of both sidewalls of the seed pattern. The second length is greater than the first length. Related devices are also provided. | 07-05-2012 |
20140077302 | POWER RECTIFYING DEVICES - According to a power rectifying device of embodiments of the inventive concept, a gate electrode, a source region, and a body region are connected in common to a first terminal, and a substrate beside the body region is connected to a second terminal. Thus, the power rectifying device having two terminals is realized. The gate electrode has s spacer-shape. Thus, a width of the gate electrode may be controlled to accurately control a channel length of a channel region of a transistor structure in the power rectifying device. | 03-20-2014 |
20140197449 | SEMICONDUCTOR RECTIFIER DEVICE - Provided is a semiconductor rectifier device. The semiconductor rectifier device may include a substrate doped with a first conductive type, a second electrode provided on a bottom surface of the substrate, an active region and a field region defined on the substrate, a gate provided in the active region, a gate insulating film provided between the gate and the substrate, body regions provided on the substrate adjacent to first and second sides of the gate, facing each other, and doped with a second conductive type dopant different from the first conductive type, and a second conductive type plug region formed on the substrate adjacent to third and fourth sides of the gate, connecting the first and second sides. | 07-17-2014 |