Patent application number | Description | Published |
20090019267 | Method, System, and Apparatus for Dynamic Reconfiguration of Resources - A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware. | 01-15-2009 |
20090024715 | Method, System, and Apparatus for Dynamic Reconfiguration of Resources - A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware. | 01-22-2009 |
20090055600 | Method, System, and Apparatus for Dynamic Reconfiguration of Resources - A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware. | 02-26-2009 |
Patent application number | Description | Published |
20090254712 | ADAPTIVE CACHE ORGANIZATION FOR CHIP MULTIPROCESSORS - A method, chip multiprocessor tile, and a chip multiprocessor with amorphous caching are disclosed. An initial processing core | 10-08-2009 |
20090265472 | Method, System, and Apparatus for System Level Initialization - Multiple initialization techniques for system and component in a point-to-point architecture are discussed. Consequently, the techniques allow for flexible system/socket layer parameters to be tailored to the needs of the platform, such as, desktop, mobile, small server, large server, etc., as well as the component types such as IA32/IPF processors, memory controllers, IO Hubs, etc. Furthermore, the techniques facilitate powering up with the correct set of POC values, hence, it avoids multiple warm resets and improves boot time. In one embodiment, registers to hold new values, such as, Configuration Values Driven during Reset (CVDR), and Configuration Values Captured during Reset (CVCR) may be eliminated. | 10-22-2009 |
20090313435 | Optimizing concurrent accesses in a directory-based coherency protocol - In one embodiment, the present invention includes a directory to aid in maintaining control of a cache coherency protocol. The directory can be coupled to multiple caching agents via an interconnect, and be configured to store a entries associated with cache lines. The directory also includes logic to determine a time delay before the directory can send a concurrent snoop request. Other embodiments are described and claimed. | 12-17-2009 |
20100250861 | FAIRNESS MECHANISM FOR STARVATION PREVENTION IN DIRECTORY-BASED CACHE COHERENCE PROTOCOLS - Methods and apparatus relating to a fairness mechanism for starvation prevention in directory-based cache coherence protocols are described. In one embodiment, negatively-acknowledged (nack'ed) requests from a home agent may be tracked (e.g., using distributed linked-lists). In turn, the tracked requests may be served in a fair order. Other embodiments are also disclosed. | 09-30-2010 |
20110145506 | Replacing Cache Lines In A Cache Memory - In one embodiment, the present invention includes a cache memory including cache lines that each have a tag field including a state portion to store a cache coherency state of data stored in the line and a weight portion to store a weight corresponding to a relative importance of the data. In various implementations, the weight can be based on the cache coherency state and a recency of usage of the data. Other embodiments are described and claimed. | 06-16-2011 |
20110320762 | REGION BASED TECHNIQUE FOR ACCURATELY PREDICTING MEMORY ACCESSES - In one embodiment, the present invention includes a processor comprising a page tracker buffer (PTB), the PTB including a plurality of entries to store an address to a cache page and to store a signature to track an access to each cache line of the cache page, and a PTB handler, the PTB handler to load entries into the PTB and to update the signature. Other embodiments are also described and claimed. | 12-29-2011 |
20130304957 | Method, System, and Apparatus for Dynamic Reconfiguration of Resources - A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware. | 11-14-2013 |
20140254588 | REDUCED WAKE UP DELAY FOR ON-DIE ROUTERS - Techniques for power gating. A first on-die router has an output port to receive data from a switching fabric. The output port is placed in a power-gated state if there is no activity in the output port for a current cycle and no messages are to be received by the output port during a subsequent cycle. A second on-die router has an input port coupled with the output port of the first on-die router. The input port is placed in a power-gated state if an input port buffer is empty and the output port is not active. Power-gating of the input port and the output port are independent of each other. | 09-11-2014 |
Patent application number | Description | Published |
20100309918 | METHOD AND SYSTEM FOR ORDERING POSTED PACKETS AND NON-POSTED PACKETS TRANSFER - A system for ordering packets. The system includes a first memory, e.g., FIFO, storing transition information for posted packets, e.g., 1 when a posted packet transitions from a non-posted packet and 0 otherwise. A second memory stores transition information for non-posted packets, e.g., 1 when a non-posted packet transitions from a posted packet and 0 otherwise. A counter increments responsive to detecting a transition in the first memory and decrements responsive to detecting a transition in the second memory. A controller orders a posted packet for transmission prior to a non-posted packet if a value of the counter is negative and when a transitional value associated with the non-posted packet is 1, and wherein the controller orders either a posted packet or a non-posted packet otherwise. The first and the second memory may be within a same memory component. | 12-09-2010 |
20140181391 | HARDWARE CHIP SELECT TRAINING FOR MEMORY USING WRITE LEVELING MECHANISM - A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a programmable time period. The method then programs a programmable delay line of the chip select with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode wherein placing the memory module in the write leveling mode toggles a state of the chip select. A write leveling procedure is then performed and a response thereto is determined from the memory module. A determination is made whether the memory module is in a pass state or an error state based on the response. | 06-26-2014 |
20140181392 | HARDWARE CHIP SELECT TRAINING FOR MEMORY USING READ COMMANDS - A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a programmable time period. The method then programs a programmable delay line of the chip select with a delay value and performs initialization of the memory module. A read command is then sent to the memory module to toggle a state of the chip select. A number of data strobe signals sent by the memory module in response to the read command are counted. A determination is made whether the memory module is in a pass state or an error state based on a result of the counting. | 06-26-2014 |
20140181429 | MULTI-DIMENSIONAL HARDWARE DATA TRAINING BETWEEN MEMORY CONTROLLER AND MEMORY - A method of training a memory interface between a memory controller and a memory module. The method includes programming a delay line of a data strobe with a delay value and programming a reference voltage with a voltage value. The method then writes a data bit pattern to the memory module wherein the data bit pattern is of a first plurality of unique data bit patterns. The data bit pattern is read back and a result is compared with the data bit pattern. A determination is made whether the memory module is in a pass state or an error state based on the comparing. The steps are repeated with another data bit pattern of the first plurality of data bit patterns. The method is repeated for each combination of the data strobe delay value and the reference voltage value. | 06-26-2014 |
20140181451 | HARDWARE COMMAND TRAINING FOR MEMORY USING WRITE LEVELING MECHANISM - A method of training a command signal for a memory module. The method includes programming a memory controller into a mode wherein a single bit of an address signal is active for a single clock cycle. The method then programs a programmable delay line of the address signal with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode. A write leveling procedure is then performed and a response thereto is determined from the memory module. A determination is made whether the memory module is in a pass state or an error state based on the response. | 06-26-2014 |
20140181452 | HARDWARE COMMAND TRAINING FOR MEMORY USING READ COMMANDS - A method of training command signals for a memory module. The method includes programming a memory controller into a mode wherein a column access strobe is active for a single clock cycle. The method then programs a programmable delay line of the column access strobe with a delay value and performs initialization of the memory module. A read command is then sent to the memory module. A number of data strobe signals sent by the memory module in response to the read command are counted. A determination is made whether the memory module is in a pass state or an error state based on a result of the counting. | 06-26-2014 |
20140189180 | METHOD AND SYSTEM FOR CHANGING BUS DIRECTION IN MEMORY SYSTEMS - A method including sorting read/write commands initiated by a memory controller based upon a destination page within a memory device. The read/write commands having a highest priority level are determined. The commands are then categorized as either page movement commands or data movement commands. The page movement commands or data movement commands are sent to the memory device based upon a signal indicating a current direction of a data bus providing communication between the memory controller and the memory device and further based upon a priority level. | 07-03-2014 |
20140359755 | CONFIGURATOR FOR SECURE FEATURE AND KEY MANAGER - A computing device receives a feature name or key name for an integrated circuit comprising a security manager core and an additional component. At least one of a) the additional component is associated with the key name or b) a feature provided by the additional component is associated with the feature name. The computing device receives a specified number of bits associated with the feature name or the key name, and maps the feature name to a feature address space or the key name to a key interface of the security manager core based at on the specified number of bits. The computing device generates at least one hardware description logic (HDL) module based on the mapping, wherein the at least one HDL module is usable to configure the security manager core for delivery of payloads associated with the feature name or the key name to the additional component. | 12-04-2014 |
20150180652 | MODULAR EXPONENTIATION OPTIMIZATION FOR CRYPTOGRAPHIC SYSTEMS - A processing device, such as logic on an integrated circuit may identify a cryptographic message stored in a first register. The processing device may determine a plurality of components for a second power of the cryptographic message using a plurality of components of the cryptographic message. The processing device may determine the plurality of components for the second power of the cryptographic message without storing the entire second power of the cryptographic message. Further, the processing device may determine a third power of the cryptographic message using modular arithmetic. The processing device may determine the third power by transforming the plurality of components for the second power of the cryptographic message and the plurality of components of the cryptographic message. | 06-25-2015 |
20150312036 | GENERATION AND MANAGEMENT OF MULTIPLE BASE KEYS BASED ON A DEVICE GENERATED KEY - A request to generate a first key may be received. A device generated key that is stored in a memory may be received in response to the request. Furthermore, a first entity identification (ID) that is stored in the memory may be received. The first key may be generated based on the first entity ID and the device generated key that are stored in the memory. | 10-29-2015 |
20150312046 | CORRUPTING A HASH VALUE CORRESPONDING TO A KEY BASED ON A REVOCATION OF THE KEY - A request associated with a revocation of a key may be received. A hash value corresponding to the key that is stored in a memory may be identified. Furthermore, the hash value that is stored in the memory may be corrupted in response to the request associated with the revocation of the key. | 10-29-2015 |
20150326541 | AUDITING AND PERMISSION PROVISIONING MECHANISMS IN A DISTRIBUTED SECURE ASSET-MANAGEMENT INFRASTRUCTURE - The embodiments described herein describe technologies for ticketing systems used in consumption and provisioning of data assets, such as a pre-computed (PCD) asset. A ticket may be a digital file or data that enables enforcement of usage count limits and uniqueness issuance ore sequential issuance of target device parameters. On implementation includes an Appliance device of a cryptographic manager (CM) system that receives a Module and a ticket over a network from a Service device. The Module is an application that securely provisions a data asset to a target device in an operation phase of a manufacturing lifecycle of the target device. The ticket is digital data that grants permission to the Appliance device to execute the Module. The Appliance device verifies the ticket to execute the Module. The Module, when executed, results in a secure construction of a sequence of operations to securely provision the data asset to the target device. | 11-12-2015 |
Patent application number | Description | Published |
20160107287 | POLISHING PADS PRODUCED BY AN ADDITIVE MANUFACTURING PROCESS - Embodiments of the present disclosure relate to advanced polishing pads with tunable chemical, material and structural properties, and new methods of manufacturing the same. According to one or more embodiments of the disclosure, it has been discovered that a polishing pad with improved properties may be produced by an additive manufacturing process, such as a three-dimensional (3D) printing process. Embodiments of the present disclosure thus may provide an advanced polishing pad that has discrete features and geometries, formed from at least two different materials that include functional polymers, functional oligomers, reactive diluents, and curing agents. For example, the advanced polishing pad may be formed from a plurality of polymeric layers, by the automated sequential deposition of at least one resin precursor composition followed by at least one curing step, wherein each layer may represent at least one polymer composition, and/or regions of different compositions. | 04-21-2016 |
20160107295 | POLISHING PADS PRODUCED BY AN ADDITIVE MANUFACTURING PROCESS - Embodiments of the present disclosure relate to advanced polishing pads with tunable chemical, material and structural properties, and new methods of manufacturing the same. According to one or more embodiments of the disclosure, it has been discovered that a polishing pad with improved properties may be produced by an additive manufacturing process, such as a three-dimensional (3D) printing process. Embodiments of the present disclosure thus may provide an advanced polishing pad that has discrete features and geometries, formed from at least two different materials that include functional polymers, functional oligomers, reactive diluents, and curing agents. For example, the advanced polishing pad may be formed from a plurality of polymeric layers, by the automated sequential deposition of at least one resin precursor composition followed by at least one curing step, wherein each layer may represent at least one polymer composition, and/or regions of different compositions. | 04-21-2016 |
Patent application number | Description | Published |
20140201411 | DEFERRED INTER-PROCESSOR INTERRUPTS - A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred IPI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI. | 07-17-2014 |
20160077987 | DEFERRED INTER-PROCESSOR INTERRUPTS - A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred WI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI. | 03-17-2016 |
Patent application number | Description | Published |
20090081302 | PULMONARY DELIVERY OF POLYENE ANTIFUNGAL AGENTS - The present invention provides spray-dried polyene compositions for oral inhalation to the lung. The polyene antifungal compositions demonstrate superior aerosol properties, do not exhibit appreciable degradation of the polyene upon spray-drying, and are useful in the treatment and prophylaxis of both pulmonary and systemic fungal infections. | 03-26-2009 |
20130022045 | SCALABLE FORWARDING TABLE WITH OVERFLOW ADDRESS LEARNING - A node is configured to receive a packet from a host device, where the packet includes a source address associated with the host device; determine that the source address is not stored by the node; generate one or more logical distances, associated with one or more nodes, based on the source address and a respective address associated with each of the nodes; determine that another node is associated with a shortest logical distance, of the one or more logical distances; and transmit the source address to the other node based on the determination that the other node is associated with the shortest logical distance, where transmitting the source address allows the other node to store the source address or enables further nodes to obtain the source address from the other node. | 01-24-2013 |
20140348170 | SCALABLE FORWARDING TABLE WITH OVERFLOW ADDRESS LEARNING - A node is configured to receive a packet from a host device, where the packet includes a source address associated with the host device; determine that the source address is not stored by the node; generate one or more logical distances, associated with one or more nodes, based on the source address and a respective address associated with each of the nodes; determine that another node is associated with a shortest logical distance, of the one or more logical distances; and transmit the source address to the other node based on the determination that the other node is associated with the shortest logical distance, where transmitting the source address allows the other node to store the source address or enables further nodes to obtain the source address from the other node. | 11-27-2014 |
Patent application number | Description | Published |
20100169283 | RECOVERY POINT DATA VIEW FORMATION WITH GENERATION OF A RECOVERY VIEW AND A COALESCE POLICY - Methods, software suites, networks, and systems of recovery point data view formation with generation of a recovery view and a coalesce policy are disclosed. In one embodiment, a network includes a virtualization module to form a data view around a recovery point, a recovery module to generate a recovery snapshot having an ability to position forward and backward from the recovery point when a rolling algorithm is applied, and an events module to generate a coalesce policy around the recovery point to reduce a storage requirement. The network may include an export module to transfer the data view to an external processing device as a virtual volume using one or more of an iSCSI and a fiber channel transport interface. The export module may automatically communicate the data view to a backup tape to provide extended data retention using a lifecycle management policy. | 07-01-2010 |
20100169592 | GENERATING A RECOVERY SNAPSHOT AND CREATING A VIRTUAL VIEW OF THE RECOVERY SNAPSHOT - Methods, software suites, and systems of generating a recovery snapshot and creating a virtual view of the recovery snapshot are disclosed. In an embodiment, a method includes generating a recovery snapshot at a predetermined interval to retain an ability to position forward and backward when a delayed roll back algorithm is applied and creating a virtual view of the recovery snapshot using an algorithm tied to an original data, a change log data, and a consistency data related to an event. The method may include redirecting an access request to the original data based on a meta-data information provided in the virtual view. The method may further include substantially retaining a timestamp data, a location of a change, and a time offset of the change as compared with the original data. | 07-01-2010 |
20100280999 | ENSURING DATA PERSISTENCE AND CONSISTENCY IN ENTERPRISE STORAGE BACKUP SYSTEMS - Ensuring data persistence and consistency in enterprise storage backup systems method and apparatus are disclosed. In one embodiment, a method includes creating a data log structure (e.g., a log file) on a storage device (e.g., a Serial ATA drive, a SCSI drive, a SAS drive, a storage are network, etc.) coupled to an application server to store a backup data generated by a filter module in a continuous backup environment and buffering the backup data generated by the filter module through a memory module that transfers the backup data to the data log structure on the storage device based on an occurrence of an event. The data log structure may be created by configuring a portion of the storage device as a dedicated resource available to the memory module to copy the backup data and the data log structure may be a file on the storage device coupled to the application server having the file system. | 11-04-2010 |
20110184918 | RECOVERY POINT DATA VIEW SHIFT THROUGH A DIRECTION-AGNOSTIC ROLL ALGORITHM - A method and system of recovery point data view shift through a direction-agnostic roll algorithm is disclosed. The method includes forming a data view around a recovery point, and shifting the data view around the recovery point through a direction-agnostic roll algorithm that uses at least one of a roll-forward algorithm to shift the data view to a time after the recovery point and a roll-backward algorithm to shift the data view to a time before the recover point. A data integrity may be determined to be consistent at the recover point by examining data and meta-data associated with the recovery point. The recovery point may be associated with one of an automatically generated event, a user definable event, and/or a prepackaged event. A marker data may be generated at the recovery point to enable the direction-agnostic roll algorithm to reduce a recovery time objective when an algorithm is applied. | 07-28-2011 |
Patent application number | Description | Published |
20100161451 | EFFICIENT COMPUTATION OF AVAILABLE TO PROMISE (ATP) IN SUPPLY CHAINS - An inventory supply management procedure involves representing inventory supply events in a data processing device memory with indications of times at which the supply events take place, and associating with each supply event at least an Available to Promise (ATP) and an ATP Restoration Guide (ATPRG) value. | 06-24-2010 |
20110137708 | Prioritized Promising with Preemption in Supply Chains - A supply chain management plan includes supply events for inventory and times at which the supplies will be received. The plan further includes demand events and when they occur. The demands may be prioritized. For each demand priority, an available to promise (ATP) amount of supply is determined in accordance with demand events of that priority. The ATP is determined for higher priority demand events before it is determined for lower priority demand events. Cancellations of a priority k order may be processed by determining, for each demand priority context i=k+1 to N, an amount of inventory to restore to available status at a particular supply event based upon a minimum ATPRG value between the particular supply event and the order committed date. | 06-09-2011 |
20150234842 | Mapping of Extensible Datasets to Relational Database Schemas - Data including a text file is received. The text file is arranged in an extensible format and includes a plurality of metadata lines, a header line, and a plurality of content lines. Metadata from the metadata lines is mapped to a plurality of metadata tables in a database that are formed according to a relational database schema using prefix parameters from each metadata line. Content from the content lines is mapped to a plurality of content tables in the database that are formed according to the relational database schema using the header line. A first subset of the content tables have a static structure and a second subset of the content tables have a dynamic structure. Related apparatus, systems, techniques and articles are also described. | 08-20-2015 |
20150234870 | DYNAMIC MAPPING OF EXTENSIBLE DATASETS TO RELATIONAL DATABASE SCHEMAS - A text file is received. The text file is arranged in an extensible format and includes a plurality of metadata lines, a header line, and a plurality of content lines. Keys are retrieved from the content lines. For each key, a data type and a number from at least one metadata table is retrieved. Using a combination of each key and the corresponding data type and number, a column title is derived. Upon verification that the derived column title does not already exist, a column for each key is generated in a content table having a dynamic structure in a relational database schema. The column has the derived column title, a column type based on the corresponding retrieved data type, and the number of generated columns determined by the corresponding retrieved number. The retrieved value is mapped into the column associated with the corresponding key. | 08-20-2015 |
Patent application number | Description | Published |
20130219412 | SYSTEM AND METHOD TO PROVIDE BPEL SUPPORT FOR CORRELATION AGGREGATION - A system and method are disclosed for providing BPEL support for correlation aggregation. The system can comprise a business process engine, executing on one or more application servers organized in a cluster. The system can comprise a database including a table which stores records relating to message groups and business process instances. When a message is received by the business process engine, the business process engine can determine an identity associated with the message, and check the database to determine if there is an entry associated with the identity. If there is no entry associated with the identity, then the business process engine can instantiate a first business process instance associated with the identity, and if there is an entry associated with the identity, then the business process engine can route the message to a business process instance associated with the identity. | 08-22-2013 |
20150046902 | EXECUTION SEMANTICS FOR SUB-PROCESSES IN BPEL - A system and method for facilitating execution of a portion of a process via a subprocess. An example method includes encapsulating process logic of a portion of a parent process via the subprocess, wherein the parent process is encoded via a business process language characterized by process lifecycle management functionality; using an instance of a call activity in a scope of the parent process or subprocess to activate the subprocess, yielding a called subprocess in response thereto; and employing a business process runtime engine to adjust a scope of the subprocess to inherit the scope of the process used to call the subprocess, thereby enabling the process lifecycle management functionality to govern a lifecycle of the subprocess. In a more specific embodiment, the business process language includes standard Business Prosecution Execution Language (BPEL); the parent process represents a business process; and the subprocess includes a standalone subprocess. | 02-12-2015 |
20150046905 | SUBPROCESS DEFINITION AND VISUALIZATION IN BPEL - A system and method for enabling reuse of a portion of a business process. An example method includes employing a business process language to facilitate accessing a definition of a subprocess characterizing the process logic, wherein the definition indicates one or more parameters to be used by the subprocess to implement a task specified by the process logic; and employing the definition to facilitate: using one or more variables of a parent process as one or more arguments that are passed to an instantiated version of the subprocess, and mapping the one or more arguments to the one or more parameters. In a more specific embodiment, the example method further includes characterizing a behavior of the subprocess via one or more dynamic scoping rules. The business process language includes a version of Business Process Execution Language (BPEL), and a BPEL extension activity facilitates defining the subprocess. | 02-12-2015 |
20150046929 | USING-SUB-PROCESSES ACROSS BUSINESS PROCESSES IN DIFFERENT COMPOSITES - A system and method for facilitating reuse of a portion of process logic by different processes. An example method includes providing a subprocess that is adapted to perform the process logic in a file accessible to a composite system, wherein the subprocess is adapted to be called by a first parent process via a subprocess extension to a business process language employed to encode the first parent process; using a call activity defined as part of the subprocess extension, and included in a scope of the first parent process to facilitate access to functionality of the subprocess by the parent process; and employing a business process engine to facilitate instantiating the subprocess, resulting in an instantiated subprocess in response thereto; and using a second parent process to share use of the instantiated subprocess with the first parent process. | 02-12-2015 |
20150058071 | SYSTEM AND METHOD FOR OBJECT LOCK MANAGEMENT USING CACHED LOCK OBJECTS - A system and method for enhancing performance of a business process execution engine, utilizing a database, a cache, and a lock management system operating in cache. The lock management system, upon receiving a request for a stored business process instance, determines by accessing the cache whether stored business process instance is locked and if the lock is expired. The stored business process object is served to the business process execution engine if it is not locked or the lock is expired. The lock functionality is implemented by writing, rewriting, and/or erasing a companion lock object stored in the cache such that no database access is required to determine whether a stored business process instance is locked. | 02-26-2015 |
20160070747 | TECHNIQUES TO REDUCE CONTENTION WINDOWS - Embodiments of the present invention provide improved concurrency by reducing the time period (also referred to herein as a locking window or contention window) during which a record is locked. This provides the benefits of pessimistic locking schemes by preventing transaction due to concurrent updates, while also reducing the time during which a record is exclusively locked. This improves user experience and performance. | 03-10-2016 |