| Patent application number | Description | Published |
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| 20090300278 | Embedded Programmable Component for Memory Device Training - A system and method by which a memory device can adapt or retrain itself in response to changes in its inputs or operating environment. The memory device, such as a DRAM, includes in its interface an embedded programmable component. The programmable component can be, for example and without limitation, a microprocessor, a microcontroller, or a microsequencer. A programmable component is programmed to make changes to the operation of the interface of the memory device, in response to changes in the environment of the memory device. | 12-03-2009 |
| 20110093644 | Memory Controller With Ring Bus for Interconnecting Memory Clients to Memory Devices - Embodiments of a distributed memory controller system implemented on a single integrated circuit device are described. In one embodiment, a memory controller that provides an interconnection circuit between a first plurality of memory devices to a second plurality of memory clients includes a ring bus to route at least one of the memory request and data return signals between the memory clients and the memory devices. The ring bus is configured in a ring topography that is distributed across a portion of an integrated circuit device, resulting in a reduction in the maximum wiring density at the center of memory controller. The ring bus structure also reduces the overall number of interconnections as well as the number of storage elements, thus reducing the total area used by the memory controller. The ring bus couples memory clients that are physically located within the ring topography on the integrated circuit to external memory devices through memory device interface circuits located on the integrated circuit device. The memory controller also includes deadlock avoidance mechanisms that utilize virtual channels on the ring bus for one or more defined types of bus traffic. | 04-21-2011 |
| 20120215996 | WRITE DATA MASK METHOD AND SYSTEM - In various embodiments, dedicated mask pins are eliminated by sending a data mask on address lines of the interface. A memory controller receives a request for a memory write operation from a memory client and determines the granularity of the write data from a write data mask sent by the client. Granularity, as used herein, indicates a quantity of write data to which each bit of the received write data mask applies. In an embodiment, the memory controller generates a particular write command and a particular write data mask based on the granularity of the write data. The write command generated is typically the most efficient of several write commands available, but embodiments are not so limited. The write command is transmitted on command lines of the interface, and the write data mask is transmitted on address lines of the interface. | 08-23-2012 |
| 20130159587 | Interconnect Redundancy for Multi-Interconnect Device - A multi-interconnect integrated circuit device includes an input/output (I/O) circuit for conveying a plurality of interleaved data channel groups by configuring the I/O circuit to convey a first data channel group over a default fixed interconnect signal paths if there are no connection failures in the default fixed interconnect signal paths, and to convey the first data channel group over a second plurality of default fixed interconnect signal paths if there is at least one connection failure in the first plurality of default fixed interconnect signal paths, where the second plurality of default fixed interconnect signal paths includes a redundant fixed interconnect signal path for replacing a failed interconnect signal path from the first plurality of default fixed interconnect signal paths. | 06-20-2013 |
| Patent application number | Description | Published |
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| 20090147015 | Aperture Compression for Multiple Data Streams - A hardware-based aperture compression system permits addressing large memory spaces via a limited bus aperture. Streams are assigned dynamic base addresses (BAR) that are maintained in registers on sources and destinations. Requests for addresses lying between BAR and BAR plus the size of the bus aperture are sent with BAR subtracted off by the source and added back by the destination. Requests for addresses outside that range are handled by transmitting a new, adjusted BAR before sending the address request. | 06-11-2009 |
| 20090248941 | Peer-To-Peer Special Purpose Processor Architecture and Method - A peer-to-peer special purpose processor architecture and method is described. Embodiments include a plurality of special purpose processors coupled to a central processing unit via a host bridge bus, a direct bus directly coupling each of the plurality of special purpose processors to at least one other of the plurality of special purpose processors and a memory controller coupled to the plurality of special purpose processors, wherein the at least one memory controller determines whether to transmit data via the host bus or the direct bus, and whether to receive data via the host bus or the direct bus. | 10-01-2009 |
| 20100329045 | Adjustment of Write Timing in a Memory Device - A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal. | 12-30-2010 |
| 20110019787 | Method and Apparatus Synchronizing Integrated Circuit Clocks - Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device. | 01-27-2011 |
| 20110060879 | SYSTEMS AND METHODS FOR PROCESSING MEMORY REQUESTS - A processing system is provided. The processing system includes a first processing unit coupled to a first memory and a second processing unit coupled to a second memory. The second memory comprises a coherent memory and a private memory that is private to the second processing unit. | 03-10-2011 |
| 20110148923 | POWER EFFICIENT MEMORY - A circuit includes a memory circuit. The memory retiling circuit moves image information configured to be distributed among a plurality of memory channels into reconfigured image information configured to be distributed among a subset of the plurality of memory channels. | 06-23-2011 |
| 20110185218 | Adjustment of Write Timing Based on a Training Signal - A method, system, and computer program product are provided for adjusting write timing in a memory device based on a training signal. For instance, the method can include configuring the memory device in a training mode of operation. The method can also include determining a write timing window between a signal on a data bus and a write clock signal based on the training signal. Further, the method includes adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference. | 07-28-2011 |
| 20110185256 | Adjustment of Write Timing Based on Error Detection Techniques - A method, system, and computer program product are provided for adjusting write timing in a memory device based on results of an error detection function. For instance, the method can include determining a write timing window between a signal on a data bus and a write clock signal based on the results of the error detection function. The method can also include adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference. | 07-28-2011 |
| 20110208989 | Command Protocol for Adjustment of Write Timing Delay - A method, system, and computer program product are provided for adjusting write timing in a memory device based on a command protocol. For instance, the method can include enabling a write clock data recovery (WCDR) mode of operation. The method can also include transmitting WCDR data from a processing unit to the memory device during the WCDR mode of operation and another mode of operation of the memory device. Based on a phase shift in the WCDR data, a phase difference between a signal on a data bus and a write clock signal can be adjusted. Further, the method can include transmitting the signal on the data bus based on the adjusted phase difference between the signal on the data bus and the write clock signal. | 08-25-2011 |
| 20120303995 | METHOD AND APPARATUS SYNCHRONIZING INTEGRATED CIRCUIT CLOCKS - Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device. | 11-29-2012 |
| 20130147821 | Methods and Systems to Facilitate Operation in Unpinned Memory - In an embodiment, a method of processing memory requests in a first processing device is provided. The method includes generating a memory request associated with a memory address located in an unpinned memory space managed by an operating system running on a second processing device; and responsive to a determination that the memory address is not resident in a physical memory, transmitting a message to the second processing device. In response to the message, the operating system controls the second processing device to bring the memory address into the physical memory. | 06-13-2013 |
| 20130159584 | DATA BUS INVERSION CODING - Techniques are disclosed relating to data inversion encoding. In one embodiment, an apparatus includes an interface circuit. The interface circuit is configured to perform first and second data bursts that include respective pluralities of data transmissions encoded using an inversion coding scheme. In such an embodiment, the initial data transmission of the second data burst is encoded using the final data transmission of the first data burst. In some embodiments, the first and second data bursts correspond to successive write operations or successive read operations to a memory module from a memory PHY. | 06-20-2013 |
| 20130159818 | Unified Data Masking, Data Poisoning, and Data Bus Inversion Signaling - Provided herein is a method and system for providing and analyzing unified data signaling that includes setting, or analyzing a state of a single indicator signal, generating or analyzing a data pattern of a plurality of data bits, and signal, or determine, based on the state of the single indicator signal and the pattern of the plurality of data bits, that data bus inversion has been applied to the plurality of data bits or that the plurality of data bits is poisoned. | 06-20-2013 |
| 20130166922 | METHOD AND SYSTEM FOR FRAME BUFFER PROTECTION - When content, such as premium video or audio, is decoded, the content is stored in protected memory segments. Read access to the protected memory segments from a component not in a frame buffer protected (FBP) mode is blocked by a memory controller. The memory controller also blocks components in the FBP mode from writing to unprotected memory segments. The content may be processed by a processing engine operating in the FBP mode and may only be written back to protected memory segments. The memory segment may later be marked as unprotected if the memory segment is no longer needed. If the content is encrypted in protected memory, the encrypting key associated with the memory segment may be removed. If the content is stored in the clear, the protected memory segments are scrubbed before releasing the segments for use as unprotected memory segments. | 06-27-2013 |
| 20140211571 | Adjustment of Write Timing in a Memory Device - A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal. | 07-31-2014 |
| 20150067244 | Method and System for Migrating Data Between Flash Memory Devices - The embodiments described herein include systems, methods and/or devices that may enhance the endurance of a storage system including a storage medium. The method includes: dividing a plurality of flash memory devices into logical chunks each logical chunk including one or more flash memory blocks; and detecting a trigger condition with respect to a respective flash memory device of the plurality of flash memory devices. In response to detecting the trigger condition, the method includes: selecting one of the logical chunks of the respective flash memory device for migration in accordance with predefined selection criteria; and storing a replicated logical chunk, comprising a copy of the selected logical chunk, at a second flash memory device. The method includes: remapping an address of the selected logical chunk to a physical location of the replicated logical chunk; and decreasing a number of logical chunks associated with the respective flash memory device. | 03-05-2015 |
| 20150067245 | Method and System for Rebalancing Data Stored in Flash Memory Devices - The embodiments described herein include systems, methods and/or devices that may enhance the endurance of a storage system including a storage medium. The method includes: dividing a plurality of flash memory devices into logical chunks each logical chunk including one or more flash memory blocks; assigning a weight to each of the flash memory devices for a distribution algorithm, where the weight is based on at least a number of available logical chunks; and storing data in the logical chunks in accordance with the distribution algorithm. The method includes detecting a trigger condition for a respective flash memory device. In response to detecting the trigger condition, the method includes: decreasing the weight of the respective flash memory device; updating the distribution algorithm to reflect the decreased weight of the respective flash memory device; and rebalancing data stored in the plurality of flash memory devices in accordance with the updated distribution algorithm. | 03-05-2015 |
