Patent application number | Description | Published |
20110037852 | DEVICE, METHOD, AND COMPUTER FOR IMAGE-BASED COUNTING OF OBJECTS PASSING THROUGH A COUNTING SECTION IN A SPECIFIED DIRECTION - For operators of public or commercial buildings, such as supermarkets, it is interesting to determine how many persons, in particular potential buyers, enter the building each day. In other areas, as well, entering and exiting moving objects are counted: it is typical, for example, that cars driving into and out of a parking garage are counted. The invention relates to a device | 02-17-2011 |
20120207350 | APPARATUS FOR IDENTIFICATION OF AN OBJECT QUEUE, METHOD AND COMPUTER PROGRAM - In daily life, people are often forced to join a queue in order, for example, to pay at a checkout or to be dealt with at an airport, etc. Because of the various forms of a queue, these are not usually recorded automatically, but are analyzed manually. For example, if a long queue is formed at a supermarket, as a result of which the predicted waiting time for the customers rises above a threshold value, this situation can be identified by the checkout personnel, and a further checkout can be opened. A device | 08-16-2012 |
Patent application number | Description | Published |
20090071710 | Flip-Chip Component and Method for its Production - The electrical and mechanical connection between a component chip and a carrier substrate having electrical wiring is realized by means of bumps. A support frame that is adapted in its height to the height of the bumps is arranged between the carrier substrate and the component chip and has a planar or planarized surface, so that it contacts closely to the bottom side of the component chip. Different covers are proposed for the additional encapsulation. | 03-19-2009 |
20090104415 | Element with Optical Marking, Manufacturing Method, and Use - A layer combination with a marking is proposed, for example, for a miniaturized electrical component. The layer combination includes a first layer and a different release layer, which is applied on it, on which a pattern is formed by a released pattern-like area. The release area is formed from an inorganic, semiconducting, insulating material, where the pattern produced thereon is machine-readable. | 04-23-2009 |
20100127377 | Method for Producing a MEMS Package - A carrier substrate has a mounting location with a number of electrical connection pads on a top side and external contacts connected thereto on an underside. A metal frame encloses the connection pads of the mounting location. A MEMS chip has electrical contacts on an underside. The MEMS chip is placed on the mounting location of the carrier substrate in such a way that the MEMS chip is seated with an edge region of its underside on the metal frame. Using a flip-chip process, the electrical contacts of the MEMS chip are connected to the connection pads of the carrier substrate by means of bumps the metal frame is connected to the MEMS chip such that a closed cavity is formed between MEMS chip and carrier substrate. | 05-27-2010 |
20100148285 | MEMS Component and Method for Production - A MEMS component includes a chip that has a rear side having a low roughness of less than one tenth of the wavelength at the center frequency of an acoustic wave propagating in the component. Metallic structures for scattering bulk acoustic waves are provided on the rear side of the chip and a material of the metallic structures is acoustically matched to a material of the chip. | 06-17-2010 |
20100187949 | Component with Reduced Temperature Response, and Method for Production - A component has a substrate and a compensation layer. A lower face of the substrate is mechanically firmly connected to the compensation layer. The lower face of the substrate and the upper face of the compensation layer have a topography. | 07-29-2010 |
20110114355 | HERMETICALLY SEALED HOUSING FOR ELECTRONIC COMPONENTS AND MANUFACTURING METHOD | 05-19-2011 |
20110233690 | SEMICONDUCTOR CHIP ARRANGEMENT WITH SENSOR CHIP AND MANUFACTURING METHOD - On a carrier ( | 09-29-2011 |
20120061778 | Method and Apparatus for Producing Chip Devices, and Chip Device Produced by Means of the Method - A chip device is produced providing at least one wafer having a plurality of chip components. The wafer or wafers are separated into the individual chip components and/or into groups of chip components. The individual chip components and/or the groups of chip components are applied to a carrier element, in such a way that interspaces having a predetermined width are formed between the individual chip components and/or the groups of chip components. A polymer is introduced into the interspaces in order to form a composite element composed of the chip components and a polymer matrix. The composite element is separated in such a way that chip devices composed of in each case one of the chip components and at least one section of the polymer matrix are formed. The invention furthermore relates to a chip device produced by means of the method. | 03-15-2012 |
20120159778 | Method for Connecting a Plurality of Unpackaged Substrates - A plurality of unpackaged substrates connected to one another is disclosed. The stepped structures on and/or in a first main area of a first substrate include a plurality of integrated circuits. The stepped structures run between the integrated circuits. The first conductor tracks extend from at least some contact connections of the respective integrated circuits as far as the stepped structures. The first substrate is connected on the side of the first main area to a further substrate. The first substrate is severed from a second main area opposite to the first main area such that the first substrate is divided into a plurality of substrate pieces. Each substrate piece has one of the integrated circuits. The first conductor tracks are accessible in interspaces between the substrate pieces. The second conductor tracks are formed from the second main area. At least some of the second conductor tracks lead from the second main area over side walls of the substrate pieces as far as the first conductor tracks. | 06-28-2012 |
20130119492 | Miniaturized Electrical Component Comprising an MEMS and an ASIC and Production Method - The invention relates to a miniaturized electrical component comprising an MEMS chip and an ASIC chip. The MEMS chip and the ASIC chip are disposed on top of each other; an internal mounting of MEMS chip and ASIC chip is connected to external electrical terminals of the electrical component by means of vias through the MEMS chip or the ASIC chip. | 05-16-2013 |
20130140656 | MEMS Microphone And Method For Producing The MEMS Microphone - The invention relates to a method for producing a microphone, in which a transducer element (WE) is mounted on a carrier (TR); a cover is arranged over the transducer element (WE) and the carrier (TR) such that the transducer element (WE) is enclosed between the cover and the carrier (TR); a first sound inlet opening (SO | 06-06-2013 |
20130214405 | Component and Method for Producing a Component - A component includes a substrate, a chip and a frame. The frame is bonded to the substrate and the chip rests on the frame. A sealing layer on parts of the frame and the chip is designed to hermetically seal a volume enclosed by the substrate, the chip and the metal frame. | 08-22-2013 |
20140111062 | Wafer-Level Package and Method for Production Thereof - A hermetic wafer-level package composed of two piezoelectric wafers, preferably identical in terms of material, and a production method therefor are presented. The electrical and mechanical connection between the two wafers is accomplished with frame structures and pillars, the partial structures of which, distributed between two wafers, are wafer-bonded with the aid of connecting layers. | 04-24-2014 |
Patent application number | Description | Published |
20080219287 | DEVICE FOR DETERMINING A NUMBER OF DATA PACKETS - The invention is directed to a device for determining a number of data packets which are to be converted into a coded sequence with a predetermined number K | 09-11-2008 |
20100045336 | Method and Device for Programmable Power Supply with Configurable Restrictions - The invention involves a programmable power supply device with configurable restrictions to the programmability of the power supply device, wherein the programmable power supply device comprises a number of freeze/programmability levels, each freeze/programmability defining a dedicated access restriction to the programmability of the power supply device. | 02-25-2010 |
20120262958 | POWER FACTOR CORRECTION CIRCUIT - A power factor correction circuit is provided which may include a first switched-mode converter circuit comprising a first inductor, at least one second switched-mode converter circuit having a second inductor, a control circuit coupled to the first and second switched-mode converter circuits, wherein the control circuit is configured to start a switching pulse for the second switched-mode converter circuit when the following conditions are fulfilled: the second inductor of the second switched-mode converter circuit has a predefined magnetization state and a predefined time period has elapsed since the start of a switching pulse for the first switched-mode converter circuit, wherein the predefined time period is a predefined fraction of the time period from the start of a previous switching pulse for the second switched-mode converter circuit to a time when the second inductor of the second switched-mode converter circuit has the predefined magnetization state. | 10-18-2012 |
20140217998 | System and Method for a Power Supply Controller - In accordance with an embodiment, a power supply controller includes an error signal input configured to be coupled to a sensing node of a power supply, a control output configured to be coupled to a switch control circuit, and a control circuit having an input coupled to the error signal input. The control circuit is configured to provide a first variable limit signal if the error signal input is in a first range, and to adjust the first variable limit signal according to the error signal input. | 08-07-2014 |
20150015217 | METHOD FOR OPERATING A POWER FACTOR CORRECTION CIRCUIT - A method for operating a power factor correction circuit is provided which may include the steps of providing a plurality of N switched-mode converter circuits each comprising an nth inductor, where N is at least 2, starting a switching pulse for the nth switched-mode converter circuit when the following conditions are fulfilled: the nth inductor of the nth switched-mode converter circuit has a predefined magnetization state; and a predefined time period has elapsed since the start of a switching pulse for an mth switched-mode converter circuit, where m=n−1 in case n>1 and m=N in case n=1. The predefined time period is a predefined fraction of the time period from the start of a previous switching pulse for the nth switched-mode converter circuit to a time when the nth inductor of the nth switched-mode converter circuit has the predefined magnetization state. | 01-15-2015 |
20150048807 | Power Factor Correction Circuit and Method - A power factor correction (PFC) circuit includes a first inductor, which is operably supplied with an input voltage and an input current. The input voltage is a rectified AC line voltage. A semiconductor switch has a load current path coupled in series with the first inductor. An output terminal is coupled to the inductor and operably providing an output voltage and an output current. A controller circuit controls the cyclic switching operation of the semiconductor switch. The controller circuit is configured to monitor a feedback signal representing the voltage drop across the load current path of the semiconductor switch, to detect at least one local minimum in the feedback signal while the semiconductor switch is off, and to switch on the semiconductor switch in response to detecting the N-th local minimum in the feedback signal. | 02-19-2015 |