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| 20090139449 | Method for manufacturing a semiconductor device, stencil mask and method for manufacturing a the same - Preparing a stencil mask comprising a silicon thin film in which an opening for selectively irradiating charged particles to a semiconductor substrate is provided and whose irradiation surface on which the charged particles are irradiated is implanted with an impurity, and selectively irradiating charged particles to the semiconductor substrate using the stencil mask which is opposingly arranged on the semiconductor substrate. | 06-04-2009 |
| 20090189203 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to an embodiment of the present invention includes a substrate, a gate insulation film formed on the substrate, a gate electrode formed on the gate insulation film, sidewall insulation films provided on side surfaces of the gate electrode, and stress application layers embedded in source and drain regions located, on a surface of the substrate, at a position which sandwiches the gate electrode, and applying stress to a channel region located under the gate insulation film in the substrate, a height of upper ends of interfaces between the substrate and the stress application layers being higher than a height of a lower end of an interface between the substrate and the gate insulation film. | 07-30-2009 |
| 20090256178 | SEMICONDUCTOR DEVICE HAVING MISFETS AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a dielectric film and gate electrode that are stacked on a substrate, sidewalls formed to cover the side surfaces of the electrode and dielectric film, and SiGe films formed to sandwich the sidewalls, electrode and dielectric film, filled in portions separated from the sidewalls, having upper portions higher than the surface of the substrate and having silicide layers formed on regions of exposed from the substrate. The lower portion of the SiGe film that faces the electrode is formed to extend in a direction perpendicular to the surface of the substrate and the upper portion is inclined and separated farther apart from the gate electrode as the upper portion is separated away from the surface of the substrate. The surface of the silicide layer of the SiGe film that faces the gate electrode is higher than the channel region. | 10-15-2009 |
| 20090317966 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method has forming a metal film containing platinum by depositing a metal on a source/drain diffusion layer primarily made of silicon formed on a semiconductor substrate and on a device isolation insulating film; forming a silicide film by silicidation of an upper part of the source/drain diffusion layer by causing a reaction between silicon in the source/drain diffusion layer and the metal on the source/drain diffusion layer by a first heating processing; forming a metal oxide film by a oxidation processing to oxidize selectively at least a surface of the metal film on the device isolation insulating film; increasing the concentration of silicon in the silicide film by a second heating processing; and selectively removing the metal oxide film and an unreacted part of the metal film on the device isolation insulating film. | 12-24-2009 |
| 20100072550 | Semiconductor device and method of manufacturing the same - A semiconductor device has plural columnar gate electrodes for plural MOSFETs formed in a row separately on a semiconductor substrate, and a semiconductor region which is formed in a part between the neighboring two columnar gate electrodes of the plural columnar gate electrodes to form a channel of the MOSFETs. | 03-25-2010 |
| 20100193874 | SEMICONDUCTOR DEVICE WITH EXTENSION STRUCTURE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation film, and a gate electrode. The source region, drain region, source extension region and drain extension region are formed in a surface portion of the semiconductor region. The first gate insulation film is formed on the semiconductor region between the source extension region and the drain extension region. The first gate insulation film is formed of a silicon oxide film or a silicon oxynitride film having a nitrogen concentration of 15 atomic % or less. The second gate insulation film is formed on the first gate insulation film and contains nitrogen at a concentration of between 20 atomic % and 57 atomic %. The gate electrode is formed on the second gate insulation film. | 08-05-2010 |
| 20110212589 | Semiconductor device manufacturing method - A semiconductor device manufacturing method has forming a metal film containing platinum by depositing a metal on a source/drain diffusion layer primarily made of silicon formed on a semiconductor substrate and on a device isolation insulating film; forming a silicide film by silicidation of an upper part of the source/drain diffusion layer by causing a reaction between silicon in the source/drain diffusion layer and the metal on the source/drain diffusion layer by a first heating processing; | 09-01-2011 |
| 20110248361 | SEMICONDUCTOR DEVICE WITH EXTENSION STRUCTURE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation film, and a gate electrode. The source region, drain region, source extension region and drain extension region are formed in a surface portion of the semiconductor region. The first gate insulation film is formed on the semiconductor region between the source extension region and the drain extension region. The first gate insulation film is formed of a silicon oxide film or a silicon oxynitride film having a nitrogen concentration of 15 atomic % or less. The second gate insulation film is formed on the first gate insulation film and contains nitrogen at a concentration of between 20 atomic % and 57 atomic %. The gate electrode is formed on the second gate insulation film. | 10-13-2011 |
| 20110303958 | NONVOLATILE SEMICONDUCTOR MEMORY - According to one embodiment, a nonvolatile semiconductor memory includes control gates provided in an array form, the control gates passing through the first semiconductor layer, data recording layers between the first semiconductor layer and the control gates, two first conductive-type diffusion layers at two ends in the first direction of the first semiconductor layer, two second conductive-type diffusion layers at two ends in the second direction of the first semiconductor layer, select gate lines extending in the first direction on the first semiconductor layer, and word lines extending in the second direction on the select gate lines. The select gate lines function as select gates shared by select transistors connected between the control gates and the word lines arranged in the first direction. Each of the word lines is commonly connected to the control gates arranged in the second direction. | 12-15-2011 |
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| 20090309133 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y≦1E-5exp(21541/T). | 12-17-2009 |
| 20110127578 | Manufacturing method for semiconductor device and semiconductor device - A manufacturing method for semiconductor device includes: forming an opening, in a surface of a semiconductor substrate being composed of first atom, the opening having an opening ratio y to an area of the surface of the semiconductor substrate ranging from 5 to 30%; forming an epitaxial layer in the opening, the epitaxial layer being made of a mixed crystal containing a second atom in a concentration ranging from 15 to 25%, and the second atom having a lattice constant different from a lattice constant of the first atom; implanting impurity ion into the epitaxial layer; and performing activation annealing at a predetermined temperature T, the predetermined temperature T being equal to or higher than 1150° C. and satisfies a relationship of y≦1E-5exp (21541/T). | 06-02-2011 |
| 20120068145 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile memory device includes a first interconnect, an insulating layer, a needle-like metal oxide, and a second interconnect. The insulating layer is provided on the first interconnect. The needle-like metal oxide pierces the insulating layer in a vertical direction. The second interconnect is provided on the insulating layer. | 03-22-2012 |
| 20120292587 | NONVOLATILE MEMORY DEVICE - According to one embodiment, a nonvolatile memory device includes a memory cell. The memory cell includes a stacked film structure. The stacked film structure is capable of maintaining a first state or a second state. The first state includes a lower electrode film, a first memory element film provided on the lower electrode film and containing a first oxide and an upper electrode film provided on the first memory element film. The second state includes the lower electrode film, the first memory element film provided on the lower electrode film, a second memory element film provided on the first memory element film and containing a second oxide and the upper electrode film provided on the second memory element film. | 11-22-2012 |
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| 20090126456 | SENSOR AND METHOD OF PRODUCING SENSOR - The present invention provides a sensor capable of maintaining an electrical connection between the lead frame and an electrode terminal section of the detection element even when an inadequate external force is applied to a lead frame and a sensor production method capable of preventing the lead frame from buckling and being deformed into an inadequate shape. The lead frame (second lead frame) can inhibit movement of a second frame main body section axially toward a rear end side through engagement of a third locking surface of a second locking section with a second locking groove and can inhibit the second frame main body section from going apart from an inner surface of an insertion hole through engagement of a fourth locking surface of the second frame locking section, which faces an element engagement section side. Namely, even when an external force is applied to the lead frame, movement of the lead frame main body section (second lead frame main body section) can be inhibited and a variation in the relative positions of the lead frame and the detection element can be prevented. | 05-21-2009 |
| 20130341706 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME - According to one embodiment, a semiconductor memory device includes a semiconductor laminated film comprising an embedded insulating film, and an SOI layer laminated on a semiconductor substrate. On the embedded insulating film, multiple pillar-shaped gate electrodes embedded in the SOI layer are provided. On the SOI layer, a pillar-shaped gate insulating film is provided to surround the side surface of each of the pillar-shaped gate electrodes. On the SOI layer, multiple first bit lines are arranged. On the pillar-shaped gate electrodes, multiple word lines are arranged. In the word line direction, the adjacent pillar-shaped gate electrodes are electrically connected to each other, and, in a first bit line direction, the adjacent pillar-shaped gate electrodes are electrically insulated from each other. | 12-26-2013 |
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| 20130248808 | RESISTANCE CHANGE ELEMENT AND NONVOLATILE MEMORY DEVICE - A resistance change element includes a first conductive layer, a second conductive layer, and a memory layer. The memory layer is provided between the first conductive layer and the second conductive layer. The memory layer is capable of reversibly transitioning between a first state and a second state due to at least one of a voltage and a current supplied via the first conductive layer and the second conductive layer. A resistance of the second state is higher than a resistance of the first state. The memory layer includes niobium oxide. One of a (100) plane, a (010) plane, and a (110) plane of the memory layer is oriented in a stacking direction from the first conductive layer toward the second conductive layer. | 09-26-2013 |
| 20140284542 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a plurality of first interconnects extending in a first direction, a plurality of second interconnects extending in a second direction crossing the first direction, and a memory element provided between the first interconnect and the second interconnect at a portion where the first interconnect crosses the second interconnect. The memory element includes a variable resistance film and a stress generating film stacked with the variable resistance film to apply stress to the variable resistance film in a surface direction. | 09-25-2014 |
| 20140284546 | MEMORY ELEMENT - According to one embodiment, a memory element includes: a first electrode layer; a second electrode layer; and a memory layer provided between the first electrode layer and the second electrode layer, and the memory layer including a plurality of first oxide layers in a second oxide layer, a resistivity of each of the plurality of first oxide layers being higher than a resistivity of the second oxide layer. | 09-25-2014 |
