Patent application number | Description | Published |
20120326745 | Current-Mode Logic Buffer with Enhanced Output Swing - A differential buffer circuit having increased output voltage swing includes a differential input stage including at least first and second transistors, the first and second transistors being operative to receive first and second signals, respectively. The buffer circuit further includes a bias stage connected between the differential input stage and a first voltage source. The bias stage is operative to generate a quiescent current as a function of a third signal supplied to the bias stage. A load circuit is connected between a second voltage source and the differential input stage, first and second differential outputs of the buffer circuit being generated at a junction between the load circuit and the differential input stage. The load circuit includes first and second switching elements coupled with the first and second transistors, respectively. The first switching element is operative to electrically connect the first differential output to the second voltage source when the first transistor is turned off. The second switching element is operative to electrically connect the second differential output to the second voltage source when the second transistor is turned off. | 12-27-2012 |
20120326768 | Hybrid Impedance Compensation in a Buffer Circuit - A compensation circuit for controlling a variation in output impedance of at least one buffer circuit includes a monitor circuit and a control circuit coupled with the monitor circuit. The monitor circuit includes a pull-up portion including at least one PMOS transistor and a pull-down portion comprising at least one NMOS transistor. The monitor circuit is configured to track an operation of an output stage of the buffer circuit and is operative to generate at least a first control signal indicative of a status of at least one characteristic of corresponding pull-up and pull-down portions in the output stage of the buffer circuit over variations in PVT conditions to which the buffer circuit may be subjected. The control circuit is operative to generate a set of digital control bits as a function of the first control signal. The set of digital control bits is operative to compensate the pull-up and pull-down portions in the output stage of the buffer circuit over prescribed variations in PVT conditions. | 12-27-2012 |
20130002267 | Impedance Mismatch Detection Circuit - A comparison circuit for detecting impedance mismatch between pull-up and pull-down devices in a circuit to be monitored includes a comparator operative to receive first and second signals and to generate, as an output, a third signal indicative of a difference between the first and second signals. A first signal generator is operative to generate the first signal indicative of a difference between reference pull-up and pull-down currents that is scaled by a prescribed amount. The reference pull-up current is indicative of a current flowing through at least one corresponding pull-up transistor device in the circuit to be monitored. The pull-down reference current is indicative of a current flowing through at least one corresponding pull-down transistor device in the circuit to be monitored. A second signal generator connected with the second input of the comparator is operative to generate the second signal as a reference voltage defining a prescribed impedance mismatch threshold associated with the circuit to be monitored. | 01-03-2013 |
20130021085 | Voltage Level Translator Circuit for Reducing Jitter - A voltage level translator circuit for translating an input signal referenced to a first voltage supply to an output signal referenced to a second voltage supply includes an input stage for receiving the input signal, the input stage including at least first and second nodes, a voltage at the second node being a logical complement of a voltage at the first node. A load circuit is coupled with the input stage, the load circuit being operative to at least temporarily store a signal at the first and/or second nodes which is indicative of a logical state of the input signal. An output stage connected with the second node is operative to generate an output signal which is indicative of a logical state of the input signal. The voltage level translator circuit further includes a compensation circuit connected with the output stage and operative to balance pull-up and pull-down propagation delays in the voltage level translator circuit as a function of a voltage at the first node. | 01-24-2013 |
20130328611 | JITTER REDUCTION IN HIGH SPEED LOW CORE VOLTAGE LEVEL SHIFTER - An apparatus comprising a level shifter circuit and a control circuit. The level shifter circuit may be configured to generate a differential output in response to (i) a first differential input, (ii) a second differential input and (iii) a first supply. The level shifter circuit comprises a first pull down transistor pair operating with the first supply. The control circuit may be configured to generate the second differential input in response to (i) the first differential input and (ii) a second supply. The control circuit generally comprises a second pull down transistor pair operating with the second supply. The second supply has a higher voltage than the first supply. | 12-12-2013 |
20130342258 | LOW POWER RECEIVER FOR IMPLEMENTING A HIGH VOLTAGE INTERFACE IMPLEMENTED WITH LOW VOLTAGE DEVICES - An apparatus comprising a first stage and a second stage. The first stage may be configured to generate an intermediate signal having a first voltage in response to an input signal having a second voltage received from a pad. The second stage may be configured to generate a core voltage in response to the first voltage. The voltage received from the pad may operate at a voltage compliant with one or more published interface specifications. | 12-26-2013 |
20140125404 | HIGH-VOLTAGE TOLERANT BIASING ARRANGEMENT USING LOW-VOLTAGE DEVICES - A reference circuit includes an NMOS transistor, a PMOS transistor and a bias circuit. The NMOS transistor includes a source connected with a first voltage supply and a gate adapted to receive a first bias signal. The PMOS transistor includes a source connected with a second voltage supply, a gate adapted to receive a second bias signal, and a drain connected with a drain of the NMOS transistor at an output of the reference circuit. The bias circuit generates the first and second bias signals. Magnitudes the first and second bias signals are configured to control a reference signal generated by the reference circuit such that when the reference signal is near a quiescent value of the reference signal, a current in the reference circuit is below a first level, and when the reference signal is outside of the prescribed limits, the current in the reference circuit increases nonlinearly. | 05-08-2014 |
20140176230 | High-Voltage Tolerant Biasing Arrangement Using Low-Voltage Devices - A reference circuit includes an NMOS transistor, a PMOS transistor and a bias circuit. The NMOS transistor includes a source connected with a first voltage supply and a gate adapted to receive a first bias signal. The PMOS transistor includes a source connected with a second voltage supply, a gate adapted to receive a second bias signal, and a drain connected with a drain of the NMOS transistor at an output of the reference circuit. The bias circuit generates the first and second bias signals. Magnitudes the first and second bias signals are configured to control a reference signal generated by the reference circuit such that when the reference signal is near a quiescent value of the reference signal, a current in the reference circuit is below a first level, and when the reference signal is outside of the prescribed limits, the current in the reference circuit increases nonlinearly. | 06-26-2014 |