Patent application number | Description | Published |
20090146716 | Timing control circuit, timing generation system, timing control method and semiconductor memory device - A timing control circuit DLY | 06-11-2009 |
20100073999 | SEMICONDUCTOR INTEGRATED CIRCUIT - In a readout circuit (RC) which detects a difference between a change that appears on a first signal line (CBL) and a change that appears on a second signal line (CBLdm) according to stored information of each selected memory cell, the first signal line and the second signal line are separated selectively from input nodes of a data latch circuit (DL) through second MOS transistors (MN | 03-25-2010 |
20110292709 | SEMICONDUCTOR DEVICE - A semiconductor device includes a sense amplifier circuit. The sense amplifier circuit includes a cross-coupled first transistor and second transistor that perform amplification. The sources of the cross-coupled transistors are respectively connected in series with a third transistor and a fourth transistor, and electrical current supply capability of the third and fourth transistors is controlled by a control voltage given to control electrodes of the third and fourth transistors. In a data retaining period, a minimum sub-threshold current necessary for retaining the data is flowed to the third and fourth transistors according to the control voltage, and bit line potential is maintained. | 12-01-2011 |
20120249180 | SEMICONDUCTOR DEVICE - A device is disclosed herein, which may be used a level-shift circuit. The device includes first, second and third power supply lines supplied respectively with first, second and third power voltages that are different from one another, first and second input terminals and an output terminal, an output circuit coupled to the first power supply line, the first and second input terminals and the output terminal, a first inverter including an input node coupled to the first input terminal and an output node coupled to the second input terminal, a first transistor coupled in series to the first inverter between the second and third power supply lines, the fifth transistor being rendered non-conductive to deactivate the first inverter, and a control circuit configured to prevent the output terminal from being brought into an electrical floating state during deactivation of the first inverter. | 10-04-2012 |
20120267792 | SEMICONDUCTOR DEVICE - A stacked device includes a plurality of semiconductor chips connected to each other by through electrodes. The same number of through electrodes are included in each of paths extending from a first power source terminal through each of circuit elements formed for the semiconductor chips to a second power source terminal. | 10-25-2012 |
20130258793 | SEMICONDUCTOR DEVICE - A semiconductor device includes a sense amplifier circuit. The sense amplifier circuit includes a cross-coupled first transistor and second transistor that perform amplification. The sources of the cross-coupled transistors are respectively connected in series with a third transistor and a fourth transistor, and electrical current supply capability of the third and fourth transistors is controlled by a control voltage given to control electrodes of the third and fourth transistors. In a data retaining period, a minimum sub-threshold current necessary for retaining the data is flowed to the third and fourth transistors according to the control voltage, and bit line potential is maintained. | 10-03-2013 |
20130292630 | SEMICONDUCTOR MEMORY DEVICE - The technical problem to be solved is to achieve high density with simple manufacturing process to decrease bit costs of memory. | 11-07-2013 |
20130322188 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device that detects an operation error of an SRAM caused by a device variation fluctuating with time is provided. In the SRAM, a memory cell has a transfer MOS transistor whose gate is connected to a word line. At the time of a write test of the memory cell, a control circuit including a test/normal operation selection circuit and a word line driver circuit applies a third voltage to the word line in a preparation period before writing test data, thereafter a first voltage to the word line, and a second voltage to the word line at the end of writing. Due to this, the threshold voltage of the transfer MOS transistor, which fluctuates with time, can be controlled. Therefore, it is possible to enhance detection efficiency for a malfunctioning cell of the SRAM due to a temporal variation. | 12-05-2013 |
Patent application number | Description | Published |
20110134678 | Semiconductor device having hierarchical structured bit line - A sense operation with respect to simultaneously-accessed two memory cells is performed by time division by using two sense amplifiers, and thereafter restore operations are performed simultaneously. With this arrangement, it is not necessary to provide switches in the middle of global bit lines, and no problem occurs when performing the restore operation by time division. Further, because a parasitic CR model of a first sense amplifier and that of a second sense amplifier become mutually the same, high sensitivity can be maintained. | 06-09-2011 |
20110176379 | SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CELL ARRAY OF OPEN BIT LINE TYPE AND CONTROL METHOD THEREOF - A semiconductor memory device includes: first and second bit lines of an open bit-line system; a sense amplifier that amplifies a potential difference between the first and second bit lines; a pair of first and second local data lines corresponding to the first and second bit lines, respectively; and a write amplifier circuit. The write amplifier circuit changes a potential of the second local data line without changing a potential of the first local data line at a time of writing data for the first bit line, and changes a potential of the first local data line without changing a potential of the second local data line at a time of writing data for the second bit line. | 07-21-2011 |
20110205820 | Semiconductor device - The semiconductor device comprises first and second memory cells, first and second bit lines connected to the first/second memory cells, first and second amplifiers connected to the second bit line, a local input/output line commonly connected to the first/second amplifiers, first and second local column switches connected between the first/second amplifiers and the local input/output line, a second local column switch connected between the second amplifier and the local input/output line, a column select line, a first global column switch connected between the column select line and the first local column switch and controlling a connection therebetween in response to a first select signal, and a second global column switch connected between the column select line and the second local column switch and controlling a connection therebetween in response to a first select signal. | 08-25-2011 |
20130057326 | SEMICONDUCTOR DEVICE USING MULTI-PHASE CLOCK SIGNAL AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME - Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1. | 03-07-2013 |
20130193507 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a sense amplifier; a plurality of memory cell arrays; a shared MOS transistor that connects/disconnects the sense amplifier and a bit line included in the memory cell arrays; and a control circuit that controls operation of the shared MOS transistor. A part or whole of an in-sense-amplifier bit line that is a bit line connecting the sense amplifier and the shared MOS transistor is embedded in a semiconductor substrate. | 08-01-2013 |
20130328187 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device which includes a plurality of first through-substrate vias that are used to supply power from a first power supply and that penetrate through a substrate structure, and a plurality of second through-substrate vias that are used to supply power from a second power supply different from the first power supply and that penetrate through a substrate structure. The semiconductor device also includes a through-substrate via string composed by the first and second through-substrate vias, in which the first through-substrate vias are located adjacent to one another and the second through-substrate vias are also located adjacent to one another. The through-substrate via string is disposed in the substrate structure for extending in a first direction. | 12-12-2013 |
20140003116 | SEMICONDUCTOR DEVICE HAVING HIERARCHICAL STRUCTURED BIT LINES | 01-02-2014 |
20140132317 | SEMICONDUCTOR DEVICE USING MULTI-PHASE CLOCK SIGNAL AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME - Disclosed herein is a device that includes a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles, and a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively. The n and the k are both integers more than 1 and a greatest common divisor thereof is 1. | 05-15-2014 |
20140154790 | BIOMOLECULE INFORMATION ANALYSIS DEVICE - Provided is a device that, on the basis of a measurement result of a current that has a low value and a wide distribution, identifies the composition of biological molecules passing through a nanoparticle path. This biomolecule information analysis device obtains a current value by applying an electrical field to biomolecules passing through a gap between a first electrode and a second electrode, and identifies the structure of the biomolecules by integrating the current value and making a comparison with a reference value (see FIG. | 06-05-2014 |
20140218999 | SEMICONDUCTOR STORAGE DEVICE - With the aim of providing a semiconductor memory device being suitable for miniaturization and allowing a contact resistance to lower, the wiring structure of a memory array (MA) is formed as follows. That is, word lines ( | 08-07-2014 |
20150041885 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: a sense amplifier; a plurality of memory cell arrays; a shared MOS transistor that connects/disconnects the sense amplifier and a bit line included in the memory cell arrays; and a control circuit that controls operation of the shared MOS transistor. A part or whole of an in-sense-amplifier bit line that is a bit line connecting the sense amplifier and the shared MOS transistor is embedded in a semiconductor substrate. | 02-12-2015 |
Patent application number | Description | Published |
20090189964 | Ink jet recording device - An ink jet recording device, comprises: a main body equipped with an ink container which accumulate ink, an ink supply pump which supplies the ink, an ink recovery pump which recovers the ink, and a control unit; a printing head equipped with a nozzle which jets the ink supplied from the main body as ink particles, an electrification electrode which electrifies the ink particles, a deflection electrode which deflects the electrified ink particles, and a gutter which collects ink particles which are not used for printing; and a cable in which an ink supply flow path for supplying the ink from the main body to the printing head, an ink recovery flow path for returning the ink particles collected by the gutter into the ink container, an exhaust circulation path which connects the ink container and the gutter, and various signal lines for connecting the control unit and the printing head, are arranged. The gutter comprises two members of an ink flow path block in which ink flows, and exhaust flow path block in which exhaust solvent vapor flows. | 07-30-2009 |
20100026754 | Ink Jet Recording Device - An ink jet recording device comprises a main body equipped with an ink container, an ink supply pump ink, an ink recovery pump, and a control unit. A printing head equipped with a nozzle emits ink supplied from the main body as ink particles. An electrification electrode electrifies the ink particles and a deflection electrode deflects the electrified ink particles. A gutter collects ink particles which are not used for printing. An exhaust circulation path connects the ink container and the gutter. The gutter comprises two members of an ink flow path block in which ink flows and an exhaust flow path block in which exhaust solvent vapor flows. | 02-04-2010 |
20100026770 | Ink Jet Recording Device - An ink jet recording device comprises a main body equipped with an ink container, an ink supply pump ink, an ink recovery pump, and a control unit. A printing head equipped with a nozzle emits ink supplied from the main body as ink particles. An electrification electrode electrifies the ink particles and a deflection electrode deflects the electrified ink particles. A gutter collects ink particles which are not used for printing. An exhaust circulation path connects the ink container and the gutter. The gutter comprises two members of an ink flow path block in which ink flows and an exhaust flow path block in which exhaust solvent vapor flows. | 02-04-2010 |
20100066790 | Image Display Apparatus - A configuration of an image display apparatus which can reduce a pump exclusive for solvent is provided. | 03-18-2010 |