Patent application number | Description | Published |
20110291630 | MICROPROCESSOR PERFORMANCE AND POWER OPTIMIZATION THROUGH SELF CALIBRATED INDUCTIVE VOLTAGE DROOP MONITORING AND CORRECTION - Disclosed is a digital voltage regulator system and method for mitigating voltage droop in an integrated circuit. If an unacceptable voltage droop is detected, the digital voltage regulator may take action to allow the power supply voltage to recover. A digital voltage regulator in accordance with embodiments discussed herein detects voltage droop by comparing a power supply voltage measurement with a threshold voltage. The threshold voltage may be calibrated based on power supply voltage measurements taken while the integrated circuit is operating. | 12-01-2011 |
20120066658 | System And Method For Integrated Circuit Power And Timing Optimization - A system for selecting gates for an integrated circuit design may include at least one processing device configured to identify gates of the integrated circuit design having a slack value less than a predefined slack threshold. The at least one processing device may be further configured to, for each of the identified gates, determine (i) a number of nodes of the integrated circuit design that experience a timing slack improvement if the gate is swapped with an alternative implementation having a reduced delay or (ii) a sum of timing slack improvements experienced by nodes of the integrated circuit design if the gate is swapped with the alternative implementation having a reduced delay. The at least one processing device may still be further configured to swap the gate with the alternative implementation having the reduced delay if the determined number or sum is greater than a corresponding predetermined threshold. | 03-15-2012 |
20120182055 | FLOP TYPE SELECTION FOR VERY LARGE SCALE INTEGRATED CIRCUITS - A method for determining flop circuit types includes performing a layout of an IC design including arranging master and slave latches of each of a plurality of flops to receive first and second clock signals, respectively. The initial IC design may then be implemented (e.g., on a silicon substrate). After implementation, the IC may be operated in first and second modes. In the first mode, the master latch of each flop is coupled to receive a first clock signal. In the second mode, the first clock signal is inhibited and the master latch is held transparent. The slave latch of each flop operates according to a second clock signal in both the first and second modes. The method further includes determining, for each flop, whether that flop is to operate as a master-slave flip-flop or as a pulse flop in a subsequent revision of the IC. | 07-19-2012 |
Patent application number | Description | Published |
20090297105 | BEND INSENSITIVE FIBER OPTIC DROP CABLE FOR IN-HOME USE - A bend insensitive fiber optic cable includes a singlemode fiber, a buffer layer surrounding the fiber wherein a thickest component of the buffer layer has an elastic modulus greater than 515 MPa (75,000 psi), and a jacket surrounding the buffer layer, wherein the jacket has a thickness of at least 1.2 mm. In one preferred embodiment, the buffer layer includes a nylon 12 resin with a nominal elastic modulus of approximately 218,000 psi. In this embodiment, an inner thin component of the buffer layer is made of an ethylene/ethyl acrylate resin so as to facilitate stripping of the buffer layer away from the fiber. | 12-03-2009 |
20110150404 | OPTICAL FIBER COATING WITH A COLOR CONCENTRATE HAVING SLICKNESS ADDITIVE - Certain embodiments of the invention may include systems and methods for coating an optical fiber. The method includes coating an optical fiber with a primary coating, preparing a secondary coating by selectively mixing a concentrate with an ultraviolet (UV) curable diluent coating, wherein the concentrate comprises predetermined amounts of a color agent and a release agent, and applying the secondary coating to the optical fiber and primary coating. | 06-23-2011 |
20110159178 | SYSTEMS AND METHODS FOR PURGING UV CURING TUBES - Certain embodiments of the invention may include systems and methods curing a coated optical fiber. The method includes drawing the coated optical fiber through a gas chamber filled with a predetermined gas, drawing the fiber through a cure tube coupled to the gas chamber, and purging at least a portion of an inner surface of the cure tube with a purge gas as the coated optical fiber is drawn through the cure tube. | 06-30-2011 |
20110188822 | OPTICAL FIBER COATINGS FOR REDUCING MICROBEND LOSSES - Certain embodiments of the invention may include systems and methods for providing optical fiber coatings to reduce microbend losses. According to an example embodiment of the invention, a method is provided for coating an optical fiber to reduce microbend losses and polarization mode dispersion (PMD). The method includes applying a primary layer to the optical fiber, wherein the optical fiber comprises a core region surrounded by a cladding region. The method includes applying a secondary layer to the primary layer, and curing the primary and secondary layers, wherein the cured primary layer adheres to the cladding region with a minimum pullout adhesion of 6 N/cm, and the cured secondary layer has an in situ modulus of about 700 MPa to about 1200 MPa at room temperature. | 08-04-2011 |
20140205251 | COLOR CODED OPTICAL FIBERS - The specification describes an optical fiber color coding scheme that uses two colors, where each of the two colors constitutes one half of the surface of the optical fiber coating. If a longitudinal portion of the coating is considered a hollow cylinder, then each of the two colors is a hollow hemi-cylinder. To ensure that each of the two colors is always plainly visible to an installer, the two colors are formed with a twist. Using two colors for coding substantially increases the number of available unique color codes. Coloring the entire coating reduces the chances of error in identifying the optical fibers. | 07-24-2014 |