Patent application number | Description | Published |
20090048336 | ESCITALOPRAM OXALATE POWDERS - Escitalopram oxalate powders having definite particle size distribution parameters, processes for preparing the powders, and solid pharmaceutical formulations containing the powders. | 02-19-2009 |
20090263475 | DEXLANSOPRAZOLE COMPOSITIONS - Premixes of dexlansoprazole with pharmaceutical excipients, processes for preparing premixes, pharmaceutical formulations containing the premixes, and their use in treatment of erosive esophagitis and heartburn associated with non-erosive gastroesophageal reflux disease. | 10-22-2009 |
20100298327 | APREPITANT POLYMORPH MIXTURES - Intimate mixtures of aprepitant crystalline Form I and crystalline Form II, having specific Hweight ratios of the forms. | 11-25-2010 |
20110028518 | DEXLANSOPRAZOLE PROCESS AND POLYMORPHS - Processes for the preparation of dexlansoprazole, an amorphous form of dexlansoprazole, a solid dispersion of amorphous dexlansoprazole and a pharmaceutically acceptable carrier, and processes for their preparation. Also provided are crystalline compounds 2-[(R)-[(4-chloro-3-methyl-2-pyridinyl)methyl]sulfinyl]-1H-benzimidazole and 2-[(R)-[(4-nitro-3-methyl-2-pyridinyl)methyl]sulfinyl]-1H-benzimidazole, and methods for their preparation. | 02-03-2011 |
20110094321 | PREPARATION OF APREPITANT - A process for preparing aprepitant. | 04-28-2011 |
20120046457 | PREPARATION OF DECITABINE - The present application relates to processes for the preparation and purification of decitabine structurally represented by formula (I): | 02-23-2012 |
20120231073 | DEXLANSOPRAZOLE COMPOSITIONS - Premixes of dexlansoprazole with pharmaceutical excipients, processes for preparing premixes, pharmaceutical formulations containing the premixes, and their use in treatment of erosive esophagitis and heartburn associated with non-erosive gastroesophageal reflux disease. | 09-13-2012 |
Patent application number | Description | Published |
20100077107 | STORAGE-SIDE STORAGE REQUEST MANAGEMENT - Techniques are provided for managing, within a storage system, the sequence in which I/O requests are processed by the storage system based, at least in part, on a one or more logical characteristics of the I/O requests. The logical characteristics may include, for example, the identity of the user for whom the I/O request was submitted, the service that submitted the I/O request, the database targeted by the I/O request, an indication of a consumer group to which the I/O request maps, the reason why the I/O request was issued, a priority category of the I/O request, etc. Techniques are also provided for automatically establishing a scheduling policy within a storage system, and for dynamically changing the scheduling policy in response to changes in workload. | 03-25-2010 |
20120173774 | STORAGE-SIDE STORAGE REQUEST MANAGEMENT - Techniques are provided for managing, within a storage system, the sequence in which I/O requests are processed by the storage system based, at least in part, on one or more logical characteristics of the I/O requests. The logical characteristics may include, for example, the identity of the user for whom the I/O request was submitted, the service that submitted the I/O request, the database targeted by the I/O request, an indication of a consumer group to which the I/O request maps, the reason why the I/O request was issued, a priority category of the I/O request, etc. Techniques are also provided for automatically establishing a scheduling policy within a storage system, and for dynamically changing the scheduling policy in response to changes in workload. | 07-05-2012 |
20130339636 | STORAGE-SIDE STORAGE REQUEST MANAGEMENT - Techniques are provided for managing, within a storage system, the sequence in which I/O requests are processed by the storage system based, at least in part, on one or more logical characteristics of the I/O requests. The logical characteristics may include, for example, the identity of the user for whom the I/O request was submitted, the service that submitted the I/O request, the database targeted by the I/O request, an indication of a consumer group to which the I/O request maps, the reason why the I/O request was issued, a priority category of the I/O request, etc. Techniques are also provided for automatically establishing a scheduling policy within a storage system, and for dynamically changing the scheduling policy in response to changes in workload. | 12-19-2013 |
Patent application number | Description | Published |
20100182816 | Power Saving Static-Based Comparator Circuits and Methods and Content-Addressable Memory (CAM) Circuits Employing Same - Static-based comparators and methods for comparing data are disclosed. The static-based comparator is configured to selectively switch at least one comparator output in response to a comparison of corresponding data with compare data, and a validity indicator for the data. If the validity indicator indicates valid data, the static-based comparator switches to drive the comparator output indicating either a match or mismatch between corresponding compared data. If the validity indicator indicates invalid data, the static-based comparator provides a mismatch on the comparator output without switching the static-based comparator regardless of whether or not the data matches the compare data. In this manner, the static-based comparator does not dissipate power switching the comparator output for data marked invalid. The static-based comparator can be employed in content addressable memories (CAMs) for comparing one or more bits of tag data to corresponding bit(s) of compare data. | 07-22-2010 |
20130332748 | Bi-Modal Power Delivery Scheme for Integrated Circuits that Enables Fine Grain Power Management for Multiple Functional Blocks on a Single Die - Systems and methods for bi-modal and fine grained power delivery to an integrated circuit comprising functional blocks. A first power source is coupled to a functional block of the integrated circuit for supporting a first operating mode of the functional block. A second power source is coupled to the functional block for supporting a second operating mode of the functional block. The first and second operating modes can be high and low frequency modes respectively. The second power source can be derived from the first power source using on-die regulators or provided independently. A desired average throughput of the functional block can be achieved by controlling duty cycles of the first and second power sources. | 12-12-2013 |
20140040647 | SYNTHESIZING INTERMEDIATE PERFORMANCE LEVELS IN INTEGRATED CIRCUITS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA - Synthesizing intermediate performance levels in integrated circuits, and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a synthesized performance level setting circuit receives an input indicating a synthesized performance mode. The circuit generates a power source selection output to select a first power source providing power to an integrated circuit functional block at a first voltage level, and generate a clock frequency setting output to select a first clock frequency associated with the first voltage level to clock the functional block, for a first predefined time interval. The circuit also generates the power source selection output to select a second power source to provide power at a second voltage level lower than the first voltage level, and generate the clock frequency setting output to select a second clock frequency associated with the second voltage level to clock the functional block, for a second predefined time interval. | 02-06-2014 |
20140117956 | METHOD AND APPARATUS FOR LDO AND DISTRIBUTED LDO TRANSIENT RESPONSE ACCELERATOR - A transient response accelerated (TRA) low dropout (LDO) regulator has an error amplifier having a feedback input, and a reference input configured to receive a reference voltage, and an output that controls a pass gate. The pass gate output voltage is applied to the feedback input. A transient response accelerator (TRA) circuit detects a rapid voltage drop on the pass gate output and, in response, applies a pulse control that rapidly lowers the resistance of the pass gate. | 05-01-2014 |
20140117958 | METHOD AND APPARATUS FOR LOAD ADAPTIVE LDO BIAS AND COMPENSATION - An adaptive low dropout (LDO) regulator includes a load-based bias controller that generates a bias control signal based on the output load current, and has a differential amplifier with a bias adjustment that receives the bias control signal and responds by adjusting a bias of a transistor within the adaptive LOD regulator. Optionally, the bias control signal is generated according to a hysteresis rule. Optionally, the adaptive LOD regulator includes an adaptive load-based compensation network having a zero, the zero having a location based, at least in part, one more of an adjustable resistance or capacitance value controlled by the load-based bias controller. | 05-01-2014 |
20140118176 | METHODS AND APPARATUS FOR A SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER - Methods and apparatus for a successive approximation register analog to digital converter are provided. In an example, provided is a method for digitally representing an analog input signal. A bit of the digital output signal is generated by altering a test voltage by an amount comparable to a weight afforded to the bit, comparing the altered test voltage with the analog input signal to create a comparison output, switching a two-to-one multiplexer to select the comparison output instead of a preceding shift-successive approximation register block output, storing the comparison output in a flip-flop, inhibiting clocking of the flip-flop, and outputting the comparison output from the flip-flop as the bit of the digital output signal. | 05-01-2014 |
20140125300 | METHOD AND APPARATUS REDUCED SWITCH-ON RATE LOW DROPOUT REGULATOR (LDO) BIAS AND COMPENSATION - A switchable bias current biases, in an operational state, a differential amplifier with a full-slew bias current. A system on/off signal transitions from an operational state to a power-down state. The transition disables the differential amplifier and switches the switchable bias current to a reduced slew bias current. The system on/off signal transitions from the power-down state to the operational state, the differential amplifier is enabled, and the switchable bias current is delayed, by a reduced slew duration, from switching to the full-slew bias current. The enabled differential amplifier slews toward a reference voltage at a reduced slew rate caused by the reduced slew bias current. The switchable bias current, after the reduced slew duration, switches to the full-slew bias current. Optionally, a regulated pass gate is disabled in response to the system on/off signal transitioning from the operational state to the power-down state. | 05-08-2014 |
20140139197 | METHOD AND APPARATUS FOR BYPASS MODE LOW DROPOUT (LDO) REGULATOR - A bypass low dropout regulator has a pass gate coupled to a voltage rail. The pass gate receives a pass gate control signal on a pass gate control line and controllably drops a voltage from a rail to a regulated output in accordance with the pass gate control signal. A differential amplifier generates the pass gate control voltage using a reference and feedback from the regulated output. A bypass switch selectively bypasses the regulator control signal, in response to a bypass signal, by placing a pass gate ON voltage on the pass gate control line. Optionally, and ON-OFF mode circuit selectively disables the pass gate in response to a system ON-OFF signal. | 05-22-2014 |
20140266835 | DUAL-STRING DIGITAL-TO-ANALOG CONVERTERS (DACS), AND RELATED CIRCUITS, SYSTEMS, AND METHODS - Dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a primary voltage divider of the dual string-DAC is comprised of at least one adjusting circuit. The adjusting circuit is configured to maintain the ideal voltage of a selected resistor node pair across a secondary voltage divider circuit in response to a primary switch unit selecting a selected resistor node pair. In this manner, impedance isolation is not required between a primary voltage divider and the secondary voltage divider circuit of the dual-string DAC. As a result, as non-limiting examples, the area on an integrated circuit (IC) for a dual-string DAC may be decreased, power consumption of the DAC may be decreased, and/or the dual-string DAC may have increased performance by not requiring a settling time. | 09-18-2014 |
20140266836 | POLARITY COMPENSATING DUAL-STRING DIGITAL-TO-ANALOG CONVERTERS (DACs), AND RELATED CIRCUITS, SYSTEMS, AND METHODS - Polarity compensating dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a secondary voltage divider of a dual-string DAC includes a switch logic unit. The switch logic unit is configured to compensate for polarity changes in the dual-string DAC to maintain monotonicity. Monotonicity means an output voltage of a DAC either increases or stays constant for monotonically increasing functions or either decreases or stays constant for monotonically decreasing functions given an incremental change in a DAC input code. The switch logic unit is configured to compensate for polarity changes in the input voltage from the primary voltage divider to the secondary resistor string. The switch logic unit is configured to select a secondary switch among the plurality of secondary switches in a secondary voltage divider, to divide an input voltage based on a polarity indicator and a DAC input code, to maintain monotonicity. | 09-18-2014 |
20140293682 | MEMORY BITCELL CLUSTERS EMPLOYING LOCALIZED GENERATION OF COMPLEMENTARY BITLINES TO REDUCE MEMORY AREA, AND RELATED SYSTEMS AND METHODS - Embodiments disclosed include memory bitcell clusters employing localized generation of complementary bitlines to reduce memory area. The memory bitcell clusters disclosed may be static random access memory (SRAM) used as central processing unit (CPU) register files. The memory bitcell clusters disclosed include a plurality of memory bitcells that share a common bitline. To reduce area required to provide complementary bitlines for the memory bitcells, the memory bitcell clusters include a localized inverter circuit. The localized inverter circuit is configured to invert a common bitline localized to the memory bitcells to provide a complementary bitline for the memory bitcells in the memory bitcell cluster. Because the inverter circuit is localized to the memory bitcells, a track in a semiconductor die for the complementary bitline does not extend beyond the memory bitcell cluster, minimizing the complexity of the memory bitcell cluster by reducing a number of bitline tracks used by half. | 10-02-2014 |
20140347202 | DUAL-STRING DIGITAL-TO-ANALOG CONVERTERS (DACs), AND RELATED CIRCUITS, SYSTEMS, AND METHODS - Dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a primary voltage divider of the dual string-DAC is comprised of at least one adjusting circuit. The adjusting circuit is configured to maintain the ideal voltage of a selected resistor node pair across a secondary voltage divider circuit in response to a primary switch unit selecting a selected resistor node pair. In this manner, impedance isolation is not required between a primary voltage divider and the secondary voltage divider circuit of the dual-string DAC. As a result, as non-limiting examples, the area on an integrated circuit (IC) for a dual-string DAC may be decreased, power consumption of the DAC may be decreased, and/or the dual-string DAC may have increased performance by not requiring a settling time. | 11-27-2014 |
20150381113 | PHASE-DEPENDENT OPERATIONAL AMPLIFIERS EMPLOYING PHASE-BASED FREQUENCY COMPENSATION, AND RELATED SYSTEMS AND METHODS - Phase-dependent operational amplifiers (“op-amps”) employing phase-based frequency compensation, and related systems and methods are disclosed. A phase-dependent op-amp is provided configured to provide output voltage based on inputs switched by clock signal. The op-amp employs a frequency compensation system having multiple frequency compensation circuits. The frequency compensation circuit corresponding to the clock phase is selected by selection circuit and coupled to the voltage output node. The op-amp charges each frequency compensation circuit during the clock phase to store voltage approximately equal to output voltage. When transitioning to a clock phase, output voltage of op-amp does not have to charge frequency compensation circuit. Voltage of frequency compensation circuit stored during clock phase is approximately equal to output voltage of op-amp for clock phase. The op-amp need only provide a small amount of voltage to the frequency compensation circuit to slew it to its designed voltage during instances of its clock phase. | 12-31-2015 |
20160070277 | DISTRIBUTED VOLTAGE NETWORK CIRCUITS EMPLOYING VOLTAGE AVERAGING, AND RELATED SYSTEMS AND METHODS - Distributed voltage network circuits employing voltage averaging, and related systems and methods are disclosed. In one aspect, because voltage in one area of a distributed load circuit may vary from voltage in a second area, a distributed voltage network circuit is configured to tap voltages from multiple areas to calculate average voltage in the distributed load circuit. The distributed voltage network circuit includes a voltage distribution source component having source nodes. Voltage is distributed from each source node to a corresponding voltage load node via resistive interconnects. Voltage tap nodes access voltage from each corresponding voltage load node. Each voltage tap node is coupled to an input node of a corresponding resistive element in voltage averaging circuit. An output node of each resistive element is coupled to a voltage output node of the voltage averaging circuit, generating the average voltage of the distributed load circuit on the voltage output node. | 03-10-2016 |
20160072491 | AUTOMATIC CALIBRATION CIRCUITS FOR OPERATIONAL CALIBRATION OF CRITICAL-PATH TIME DELAYS IN ADAPTIVE CLOCK DISTRIBUTION SYSTEMS, AND RELATED METHODS AND SYSTEMS - Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems, are disclosed. The adaptive clock distribution system includes a tunable-length delay circuit to delay distribution of a clock signal provided to a clocked circuit, to prevent timing margin degradation of the clocked circuit after a voltage droop occurs in a power supply supplying power to the clocked circuit. The adaptive clock distribution system also includes a dynamic variation monitor to reduce frequency of the delayed clock signal provided to the clocked circuit in response to the voltage droop in the power supply, so that the clocked circuit is not clocked beyond its performance limits during a voltage droop. An automatic calibration circuit is provided in the adaptive clock distribution system to calibrate the dynamic variation monitor during operation based on operational conditions and environmental conditions of the clocked circuit. | 03-10-2016 |