Koji Tamura
Koji Tamura, Fukuyama-Shi JP
Patent application number | Description | Published |
---|---|---|
20080206981 | Semiconductor device and manufacturing method therefor - In a manufacturing method for a semiconductor storage device, an interlayer insulating film, a first hard mask made of an insulative material for coating the interlayer insulating film and a second hard mask are formed on a substrate. The second hard mask is opened, and with use of the second hard mask as a mask, a recess groove, where an embedded interconnection is to be embedded, is formed in the interlayer insulating film. A diffusion preventing film is formed for preventing an embedded interconnection material from diffusing into the interlayer insulating film. The second hard mask and the diffusion preventing film are made of an identical material, which is a conductive material containing a metallic element in its composition. A conductive metal to be a material of the embedded interconnection is deposited. The surface side of the conductive metal is polished to the level that the first hard mask is exposed therefrom. | 08-28-2008 |
20090117344 | METHOD OF CORRECTING MASK PATTERN, PHOTO MASK, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - A method of correcting a mask pattern, the method correcting the mask pattern of a mask such that a wiring pattern having desired dimensions is formed based on a micro-fabrication process using the mask, corrects the mask pattern so that, before carrying out the micro-fabrication process, an etching proximity effect is dealt with by use of the correction model in which a pattern size and a inter-patter space size are set as parameters. This makes it possible to correct the mask pattern with high accuracy so that the wiring pattern having the desired dimensions is formed on the substrate, thereby dealing with the etching proximity effect. | 05-07-2009 |
Koji Tamura, Higashi Ibaraki-Gun JP
Patent application number | Description | Published |
---|---|---|
20090071616 | METHOD OF UPGRADING BIOMASS, UPGRADED BIOMASS, BIOMASS WATER SLURRY AND METHOD OF PRODUCING SAME, UPGRADED BIOMASS GAS, AND METHOD OF GASIFYING BIOMASS - This method of upgrading a biomass comprises: an upgrading step for performing upgrading treatment of a cellulose based biomass with an oxygen/carbon atomic ratio of at least 0.5, in presence of water and under a pressure of at least saturated water vapor pressure, and reducing said oxygen/carbon atomic ratio of said biomass to no more than 0.38, and a separation step for separating an upgraded reactant obtained from said upgrading step into a solid component and a liquid component. | 03-19-2009 |
Koji Tamura, Hiroshima JP
Patent application number | Description | Published |
---|---|---|
20080308799 | WIRING STRUCTURE AND MANUFACTURING METHOD THEREFOR - A wiring structure including a wiring pattern formed in an insulation film on a substrate, a pattern for measurement which is formed in the insulation film on the substrate in a region different from a region where the wiring pattern is formed and is irradiated with measuring light, and a light transmission inhibiting film formed directly below the pattern for measurement, wherein the pattern for measurement is the same pattern as the wiring pattern, and the light transmission inhibiting film is made of a material having light transmissivity that is smaller than light transmissivity of a material of the insulation film forming the pattern for measurement. | 12-18-2008 |
Koji Tamura, Himeji-Shi JP
Patent application number | Description | Published |
---|---|---|
20150069592 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SAME, AND APPLICATION BOARD MOUNTED WITH SAME - In one embodiment, a semiconductor device includes a lead frame including an island portion and a terminal portion separated from the island portion. The device further includes a semiconductor chip mounted on the island portion and including an electrode. The device further includes an insulating layer disposed on the semiconductor chip and having an opening to expose at least a part of the electrode. The device further includes a connector covering the electrode exposed through the opening and electrically connecting the electrode and the terminal portion. | 03-12-2015 |
20150069598 | HEAT DISSIPATION CONNECTOR AND METHOD OF MANUFACTURING SAME, SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME, AND SEMICONDUCTOR MANUFACTURING APPARATUS - In one embodiment, a heat dissipation connector mounted on a semiconductor chip and sealed up with a molding resin along with the semiconductor chip and a lead frame includes a heat dissipation portion configured to have a block shape, and have an upper face exposed out of the molding resin. The connector further includes a connecting portion configured to extend from a first side face of the heat dissipation portion, and electrically connect an electrode arranged on the semiconductor chip to the lead frame. The heat dissipation portion and the connecting portion are integrally made of the same metal sheet. | 03-12-2015 |
Koji Tamura, Tokyo JP
Patent application number | Description | Published |
---|---|---|
20150178888 | DISPLAY DEVICE, DATA PROCESSING DEVICE AND COMPUTER READABLE MEDIUM - A display device, including: a storage unit in which page image data including a figure or a photograph and figure photo information are stored so as to be associated with each other for each page, the figure photo information corresponding to a figure or a photograph included in a page, being information for individually displaying the figure or the photograph and including area information which indicates an area occupied by the figure or the photograph in page image data corresponding to the page; a display unit; an operation unit; an identification unit; and a display control unit. | 06-25-2015 |
Koji Tamura, Himeji Hyogo JP
Patent application number | Description | Published |
---|---|---|
20150221581 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a first frame includes a first thin plate section and a first thick plate section. A second frame includes a second thin plate section and a second thick plate section. A semiconductor chip includes a first electrode bonded to a first inner surface of the first thin plate section of the first frame, and a second electrode bonded to a second inner surface of the second thick plate section of the second frame. A resin layer seals the semiconductor chip, but leaves exposed the first outer surface of the first frame and the second outer surface of the second frame. | 08-06-2015 |
20150239093 | GRINDING APPARATUS, AND GRINDING METHOD - According to one embodiment, a grinding apparatus includes a chuck table, a grinding wheel that is pressed against a plurality of separate ground surfaces of a plurality of workpieces fixed to the chuck table while rotating to grind the workpieces, a measuring device that measures heights of the ground surfaces, and a control device that controls amount of grinding of the workpieces based on the heights of the plurality of ground surfaces measured before grinding the workpieces, and the heights of the plurality of ground surfaces measured after grinding the workpieces. | 08-27-2015 |
Koji Tamura, Kawasaki-Shi JP
Patent application number | Description | Published |
---|---|---|
20150255383 | MOUNTING MEMBER, ELECTRONIC COMPONENT, AND METHOD FOR MANUFACTURING MODULE - A mounting member includes a plurality of internal connecting portions, each of which is electrically connected to an electronic device, and a plurality of external connecting portions, each of which is soldered, wherein the plurality of external connecting portions include a first connecting portion in communication with at least any of the plurality of internal connecting portions, and a second connecting portion different from the first connecting portion, and surfaces of the first connecting portion and the second connecting portion include gold layers, and a thickness of the gold layer of the second connecting portion is smaller than a thickness of the gold layer of the first connecting portion. | 09-10-2015 |