Patent application number | Description | Published |
20100053671 | IMAGE FORMATION APPARATUS, RECORDING MEDIUM, IMAGE FORMATION METHOD, AND CONSUMABLES MANAGEMENT SYSTEM - An image formation apparatus, which includes: a detector unit that detects a status of consumables; a prediction unit that predicts a run-out timing of the consumables on the basis of the status detected by the detector unit; a transmission unit that transmits the status detected by the detector unit to a management apparatus as consumables information; a reception unit that receives run-out timing information indicating a run-out timing predicted by the management apparatus on the basis of the consumables information transmitted by the transmission unit; and a notification unit that notifies the run-out timing of the consumables on the basis of the run-out timing information received by the reception unit if communication with the management apparatus is possible, or notifies the run-out timing of the consumables on the basis of the run-out timing predicted by the prediction unit if communication with the management apparatus is not possible. | 03-04-2010 |
20100082867 | Multi-thread processor and its interrupt processing method - A first exemplary aspect of an embodiment of the present invention is a multi-thread processor including a plurality of hardware threads each of which generates an independent instruction flow, and an interrupt controller that determines whether or not an input interrupt request signal is associated with one or more than one of the plurality of hardware threads, and when the input interrupt request signal is associated, assigns the interrupt request to an associated hardware thread. | 04-01-2010 |
20100082944 | Multi-thread processor - In an exemplary aspect, the present invention provides a multi-thread processor including a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that outputs a thread selection signal in accordance with a first or second schedule, the thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware threads, a first selector that selects one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread, and an execution pipeline that executes an instruction output from the first selector, wherein when the multi-thread processor is in a first state, the thread scheduler selects the first schedule, and when the multi-thread processor is in a second state, the thread scheduler selects the second schedule. | 04-01-2010 |
20100082945 | Multi-thread processor and its hardware thread scheduling method - A multi-thread processor in accordance with an exemplary aspect of the present invention includes a plurality of hardware threads each of which generates an independent instruction flow, a thread scheduler that outputs a thread selection signal TSEL designating a hardware thread to be executed in a next execution cycle, a first selector that outputs an instruction generated by a hardware thread selected according to the thread selection signal, and an execution pipeline that executes an instruction output from the first selector, wherein the thread scheduler specifies execution of at least one hardware thread selected in a fixed manner in a predetermined first execution period, and specifies execution of an arbitrary hardware thread in a second execution period. | 04-01-2010 |
20100083267 | Multi-thread processor and its hardware thread scheduling method - A multi-thread processor in accordance with an exemplary aspect of the present invention includes a plurality of hardware threads each of which generates an independent instruction flow, a first thread scheduler that outputs a first thread selection signal designating a hardware thread to be executed in the next execution cycle, a first selector that outputs an instruction generated by the selected hardware thread according to the first thread selection signal, and an execution pipeline that executes an instruction output from the first selector, wherein whenever a hardware thread is executed in the execution pipeline, the first thread scheduler updates the priority rank of the executed hardware thread and outputs the first thread selection signal in accordance with the updated priority rank. | 04-01-2010 |
20100123285 | MEDIUM TRANSPORT DEVICE, CONTROL PROGRAM FOR MEDIUM TRANSPORT DEVICE AND CONTROL METHOD FOR MEDIUM TRANSPORT DEVICE - A medium transport device includes a sensor unit, a timing data collection unit, and a sampling resolution changing unit. The sensor unit is provided in a transport path of a print recording medium to detect a transport timing of the print recording medium. A timing data collection unit receives an output from the sensor unit and samples the output at a sampling interval as timing data. A sampling resolution changing unit changes the sampling interval. | 05-20-2010 |
20100123914 | IMAGE PROCESSING APPARATUS AND COMPUTER READABLE MEDIUM - An image processing apparatus includes a determination unit determining, based on a pixel value of a prescribed background color area in image data obtained by inputting a printed image, and based on information regarding a color of a toner used in printing the image, whether or not the background color of the image corresponds to the color of the toner. | 05-20-2010 |
20100135680 | PAPER WRINKLE SIGN MONITORING DEVICE, PAPER WRINKLE SIGN MONITORING METHOD, AND COMPUTER READABLE MEDIUM - A paper wrinkle sign monitoring device includes: at least one timing detecting unit that is set on a transport path of a printing medium, and that detects transport timing of the printing medium; and a sign output unit that detects a sign of paper wrinkle generation in the transporting time of the printing medium based on the transport timing of the printing medium detected by the timing detecting unit, and that outputs the sign. | 06-03-2010 |
20100161546 | FAILURE DIAGNOSIS SYSTEM, A FAILURE DIAGNOSIS DEVICE, AN INFORMATION UPDATE DEVICE, AND A COMPUTER-READABLE MEDIUM - According to an aspect of the present invention, there is provided a failure diagnosis system including: a causal relationship information storage unit configured to store causal relationship information representing a causal relationship between events regarding a diagnosis-target apparatus, the causal relationship information including: common causal relationship information that is commonly used in a plurality of types of failure diagnosis regarding the diagnosis-target apparatus; and specific causal relationship information that is used in each specific type of failure diagnosis among the plurality of types of failure diagnosis; and a diagnosis execution unit configured to selectively execute the plural types of failure diagnosis by using a combined causal relationship information that is a combination of the common causal relationship information and a piece of the specific causal relationship information corresponding to a diagnosis-target type of failure diagnosis. | 06-24-2010 |
20100225052 | TRANSPORT DEVICE, OVERLAP FEED SIGN DETECTION DEVICE, AND COMPUTER READABLE MEDIUM - A transport device includes a feed unit that feeds transport subjects being loaded in a loading portion one by one in a transport direction, a protrusion amount detection unit that detects a protrusion amount of the transport subjects from the loading portion in the transport direction and an overlap feed sign detection unit that detects a sign of occurrence of overlap feed of the transport subjects based on a detection result of the protrusion amount. | 09-09-2010 |
20100235140 | DETECTED DATA PROCESSING APPARATUS AND COMPUTER READABLE MEDIUM FOR DETECTING DATA - A detected data processing apparatus includes a selecting unit that calculates mutual correlation between a plurality of groups of detected data acquired from a detecting unit that detects an operational state of a circuit board, and then selects as analysis data the detected data of a group whose value indicating correlation with other groups is smaller than a threshold value set up in advance; and a first calculating unit that calculates a first Mahalanobis distance on a basis of a first Mahalanobis space generated by using the analysis data selected by the selecting unit from the detected data obtained when a normal circuit board is operated and on a basis of the detected data obtained when a circuit board of diagnosis target is operated. | 09-16-2010 |
20120013935 | IMAGE DEFECT INSPECTION APPARATUS, IMAGE DEFECT INSPECTION SYSTEM, IMAGE DEFECT INSPECTION METHOD AND NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM - An image defect inspection apparatus includes a supply unit, an acquiring unit, an inspection unit and an adjustment unit. The supply unit supplies a test image corresponding to an inferred image defect regarding an image forming unit that forms an image on a recording material, to the image forming unit to form the test image on the recording material. The acquiring unit acquires a scanned image obtained by scanning the recording material on which the test image is formed. The inspection unit compares the scanned image acquired with the test image and inspects as to whether or not the inferred image defect is in the scanned image. The adjustment unit adjusts a value of a setting item which is defined as an adjust target regarding the inferred image defect, so as to enhance detectability of the inferred image defect in the inspection. | 01-19-2012 |
20130013900 | MULTI-THREAD PROCESSOR AND ITS HARDWARE THREAD SCHEDULING METHOD - A multi-thread processor includes a plurality of hardware threads each of which generates an independent instruction flow, a first thread scheduler that outputs a first thread selection signal, the first thread selection signal designating a hardware thread to be executed in a next execution cycle among the plurality of hardware threads according to a priority rank, the priority rank being established in advance for each of the plurality of hardware threads, a first selector that selects one of the plurality of hardware threads according to the first thread selection signal and outputs an instruction generated by the selected hardware thread, and an execution pipeline that executes an instruction output from the first selector. Whenever the hardware thread is executed in the execution pipeline, the first scheduler updates the priority rank for the executed hardware thread and outputs the first thread selection signal in accordance with the updated priority rank. | 01-10-2013 |
20130263129 | SEMICONDUCTOR DEVICE - A semiconductor device includes an instruction decoder that decodes an instruction code and thereby generates instruction information, an execution unit that performs an operation based on the instruction information through pipeline processing, and a pipeline control unit that controls an order of the instruction code to be processed in the pipeline processing, in which the pipeline control unit includes a register for defining presence/absence of an authority to execute a first privilege program for each virtual machine, the first privilege program being to be executed on one virtual machine, refers to the register, and when the virtual machine that has issued the instruction code relating to the first privilege program has an authority to execute the first privilege program, instructs the execution unit to execute a process based on the instruction code relating to a second privilege program, based on an operation of the first privilege program. | 10-03-2013 |
20130297916 | SEMICONDUCTOR DEVICE - A related art semiconductor device suffers from a problem that a processing capacity is decayed by switching an occupied state for each partition. A semiconductor device according to the present invention includes an execution unit that executes an arithmetic instruction, and a scheduler including multiple first setting registers each defining a correspondence relationship between hardware threads and partitions, and generates a thread select signal on the basis of a partition schedule and a thread schedule. The scheduler outputs a thread select signal designating a specific hardware thread without depending on the thread schedule as the partition indicated by a first occupation control signal according to a first occupation control signal output when the execution unit executes a first occupation start instruction. | 11-07-2013 |