| Patent application number | Description | Published |
|---|
| 20130007439 | MULTICORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND NOTIFICATION METHOD - A multicore processor system includes a processor configured to detect, among cores that have booted with an old boot program in the multicore processor, a core to which no process is assigned; change upon detecting a core to which no process is assigned, a reference area from a storage area for the old boot program to a storage area for a new boot program; and notify the core to which no process is assigned of a reboot instruction specifying the reference area after the change. | 01-03-2013 |
| 20130007490 | MULTICORE PROCESSOR SYSTEM, POWER CONTROL METHOD, AND COMPUTER PRODUCT - A multicore processor system having multiple cores, includes processors configured to measure bandwidth of a network; compare the measured bandwidth and a given threshold; determine among the cores and based on an obtained comparison result, a core adjustment number by which the number of cores executing a given process related to data communicated through the network is adjusted; calculate the number of executing cores after adjustment by the core adjustment number and based on the number of cores executing the given process before the adjustment and the determined core adjustment number; specify a core executing the given process among the cores and based on the calculated number of executing cores after the adjustment; and distribute the communicated data to the specified core executing the given process. | 01-03-2013 |
| 20130007758 | MULTI-CORE PROCESSOR SYSTEM, THREAD SWITCHING CONTROL METHOD, AND COMPUTER PRODUCT - A multi-core processor system includes a given core configured to switch at a prescribed switching period, threads assigned to the given core; identify whether the given core has switched threads at a period exceeding the prescribed switching period; correct the prescribed switching period into a shorter switching period, based on a difference of an actual switching period at which the threads have been switched by the given core and the prescribed switching period; and set the corrected switching period as the prescribed switching period. | 01-03-2013 |
| 20130007763 | GENERATING METHOD, SCHEDULING METHOD, COMPUTER PRODUCT, GENERATING APPARATUS, AND INFORMATION PROCESSING APPARATUS - A generating method is executed by a processor. The method includes executing simulation using a simulation model expressing a processor model, a memory model to which the processor model is accessible, and a load source that accesses the memory model according to an access contention rate, to obtain an index value for performance of the processor model, for each access contention rate; and saving to a memory area and as contention characteristics information, the index value for each access contention rate. | 01-03-2013 |
| 20130007765 | SOFTWARE CONTROL DEVICE, SOFTWARE CONTROL METHOD, AND COMPUTER PRODUCT - A software control device includes a processor configured to determine whether starting software and running software are accessing the same common resource; and control the running software to be temporarily suspended upon determining that the starting software and the running software are accessing the same common resource. | 01-03-2013 |
| 20130013834 | MULTI-CORE PROCESSOR SYSTEM, ARBITER CIRCUIT CONTROL METHOD, AND COMPUTER PRODUCT - A multi-core processor system includes multiple cores; shared memory accessed by the cores; and an arbiter circuit that arbitrates contention of right to access the shared memory by the cores. Each of the cores is configured to acquire for the core, a measured speed of access to the shared memory; calculate for the core, a response performance based on the measured speed of access and a theoretical speed of access for the core; calculate for the cores and based on the response performance calculated for each of the cores, ratios of access rights to access the shared memory, the ratios being calculated such that a ratio of access rights for a given core is larger than a ratio of access rights for another core whose response performance is higher than that of the given core; and notify the arbiter circuit of the calculated ratios of access rights. | 01-10-2013 |
| 20130013835 | MULTICORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND CONTROL METHOD - A multicore processor system includes a processor configured to detect any among a switching process and an assignment process of applications in a multicore processor; acquire upon detecting any among the switching process and the assignment process, a priority level concerning execution of each application assigned to each core of the multicore processor and number of accesses of a shared resource shared by the multicore processor; determine an access ratio of an application whose priority level is highest to each of application remaining after excluding the application whose priority level is highest, among the assigned applications, by comparing the number of accesses by each remaining application and the number of accesses by the application whose priority level is highest; notify an arbiter circuit of the determined access ratios; and arbitrate using the arbiter circuit, the access of the shared resource by the multicore processor, based on the access ratios. | 01-10-2013 |
| 20130013892 | HIERARCHICAL MULTI-CORE PROCESSOR, MULTI-CORE PROCESSOR SYSTEM, AND COMPUTER PRODUCT - A hierarchical multi-core processor includes a core group for each hierarchy of a hierarchy group constituting a series of communication functions divided according to communication protocol, where a first core group of a given hierarchy among the hierarchy group is connected to a second core group of another hierarchy constituting a first communication function to be executed following a second communication function of the given hierarchy. | 01-10-2013 |
| 20130019069 | MULTI-CORE PROCESSOR SYSTEM, MEMORY CONTROLLER CONTROL METHOD, AND COMPUTER PRODUCT - A multi-core processor system includes a memory controller that includes multiple ports and shared memory that includes physical address spaces divided among the ports. A CPU acquires from a parallel degree information table, the number of CPUs to which software that is to be executed by the multi-core processor system, is to be assigned. After this acquisition, the CPU determines the CPUs to which the software to be executed is to be assigned and sets for each CPU, physical address spaces corresponding to logical address spaces defined by the software to be executed. After this setting, the CPU notifies an address converter of the addresses and notifies the software to be executed of the start of execution. | 01-17-2013 |
| 20130024588 | MULTICORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND CONTROL METHOD - A multicore processor system includes a core configured to detect a change in a state of assignment of a multicore processor; obtain, upon detecting the change in the state of assignment, number of accesses of a common resource shared by the multicore processor by each of process that are assigned to cores of the multicore processor; calculate an access ratio based on the obtained number of accesses; and notify an arbitration circuit of the calculated access ratio, the arbitration circuit arbitrating accesses of the common resource by the multicore processor. | 01-24-2013 |
| 20130024589 | MULTI-CORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND CONTROL METHOD - A multi-core processor system includes a given configured to queue an interrupt process of a software interrupt request to the given core, and execute queued processes in the order of queuing at the given core; execute preferentially an interrupt process of a hardware interrupt request to the given core over a process under execution at the given core; determine whether the software interrupt request is a specific software interrupt request; and perform control to preferentially execute the interrupt process without queuing, upon determining that the software interrupt request is the specific software interrupt request. | 01-24-2013 |
| 20130024865 | MULTI-CORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND CONTROL METHOD - A multi-core processor system includes a core configured to determine whether a task to be synchronized with a given task is present; identify among cores making up the multi-core processor and upon determining that a task to be synchronized with the given task is present, a core to which no non-synchronous task that is not synchronized with another task has been assigned, and identify among cores making up the multi-core processor and upon determining that a task to be synchronized with the given task is not present, a core to which no synchronous task to be synchronized with another task has been assigned; and send to the identified core, an instruction to start the given task. | 01-24-2013 |
| 20130024870 | MULTICORE SYSTEM AND ACTIVATING METHOD - A multicore system includes multiple processor cores; a scheduler in each of the processor cores and allocating a process to the processor cores when having a master authority that is an authority to assign processes; and a master controller performing control to repeat until a process to be executed no longer exists, a cycle in which the schedulers transfer the master authority to another processor core after receiving the master authority and before assigning a process to the processor cores, discards the master authority after assigning the process to the processor cores, and enters a state of waiting to receive the master authority. | 01-24-2013 |
| 20130031391 | MULTI-CORE PROCESSOR SYSTEM, ELECTRICAL POWER CONTROL METHOD, AND COMPUTER PRODUCT - A multi-core processor system includes a core configured to detect that among cores different from a specific core executing a specific process, a given software different from specific software having a function equivalent to the specific process, is under execution; extract, from a database storing required computing capacities for the plural software and upon detecting that a given software is under execution, requirement values indicating the required computing capacity of the specific software and of the given software; judge for each the cores, whether a sum of the required computing capacities of the specific software and the software is at most a computing capacity value of the core; assign the specific software to a core for which the sum of the required computing capacities is judged to be at most the computing capacity value of the core; and suspend the specific core, upon assigning the specific software to the core. | 01-31-2013 |
| 20130047021 | MULTIPLE-CORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND CONTROL METHOD - A multiple-core processor system includes a memory unit storing the number of time intervals within a time bin, a time interval being a time interval between two consecutive operations; and a processor configured to: update the number of time intervals, specify a time stretch during which the number of time intervals stays above a threshold, and set, based on the number of time intervals, a power supply mode in which the multiple-core processor is supplied with power. | 02-21-2013 |
| 20130060974 | DATA TRANSFERRING APPARATUS AND DATA TRANSFERRING METHOD - A memory stores data generated by a processor and a transferring unit burst transfers the data from the memory unit to a processing unit. Based on an access capability of the processor when accessing the memory, a prescribed value for a burst width and information concerning the time that the processing unit consumes to process the data are set in advance at the data transferring apparatus. When the transferring unit performs data transfer, the time allowed for data transfer is calculated based on the information concerning the time that the processing unit consumes to process the data, and the burst width is determined as a value greater than or equal to the prescribed value for the burst width and is as close as possible to the prescribed value for the burst width within a range in which data transfer can be finished within the allowed time. | 03-07-2013 |
| 20130097382 | MULTI-CORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND CONTROL METHOD - A multi-core processor system includes a first processor that among cores of the multi-core processor, identifies other cores having a cache miss-hit rate lower than that of a given core storing a specific program in a cache, based on a task information volume of each core; a control circuit that migrates the specific program from the cache of the given core to a cache of the identified core; and a second processor that, after the specific program is migrated to the cache of the identified core, sets as a write-inhibit area, an area that is of the cache of the identified core and to which the specific program is stored. | 04-18-2013 |
| 20130097384 | MULTI-CORE PROCESSOR SYSTEM, CACHE COHERENCY CONTROL METHOD, AND COMPUTER PRODUCT - A multi-core processor system includes a processor configured to establish coherency of shared data values stored in a cache memory accessed by a multiple cores; detect a first thread executed by a first core among the cores; identify upon detecting the first thread, a second thread under execution by a second core other than the first core and among the cores; determine whether shared data commonly accessed by the first thread and the second thread is present; and stop establishment of coherency for a first cache memory corresponding to the first core and a second cache memory corresponding to the second core, upon determining that no shared data commonly accessed is present. | 04-18-2013 |
| 20130097389 | MEMORY ACCESS CONTROLLER, MULTI-CORE PROCESSOR SYSTEM, MEMORY ACCESS CONTROL METHOD, AND COMPUTER PRODUCT - A memory access controller includes a semiconductor circuit configured to classify into a first group of cores having made an exclusive access request to shared memory and a second group of cores not having made an exclusive access request to the shared memory, multiple cores capable of accessing the shared memory; detect a core having completed the exclusive access among the first group of cores; and send to a core among the first group of cores and standing by for the exclusive access, a notification of release from a standby state, when detecting a core having completed the exclusive access. | 04-18-2013 |
| 20130097441 | MULTI-CORE PROCESSOR SYSTEM, POWER CONTROL METHOD, AND COMPUTER PRODUCT - A multi-core processor system includes a core configured to detect among multiple cores, a state of migration of first software from a first core to the core whose specific processing capacity value is lower than that of the first core; and set the processing capacity value of the first core at a time of the detection to be a processing capacity value that is lower than that before the migration when detecting the state of migration. | 04-18-2013 |
| 20130111078 | DATA TRANSFER CONTROL APPARATUS, DATA TRANSFER CONTROL METHOD, AND COMPUTER PRODUCT | 05-02-2013 |
| 20130111138 | MULTI-CORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND CONTROL METHOD | 05-02-2013 |
| 20130111143 | MULTI-CORE SYSTEM AND EXTERNAL INPUT/OUTPUT BUS CONTROL METHOD | 05-02-2013 |
| 20130111158 | MULTI-CORE PROCESSOR SYSTEM, CONTROL PROGRAM, AND CONTROL METHOD | 05-02-2013 |
| 20130117347 | COMMUNICATION APPARATUS, COMMUNICATION METHOD, AND COMPUTER PRODUCT - A communication apparatus includes a processor configured to access memory of the communication apparatus; communicate with a second apparatus; detect an access request generated by the communication apparatus; determine whether an address of access targeted data indicated in the detected access request is an address allocated to the memory of the communication apparatus; and perform control for selecting and executing based on a determination result, any one among a process of accessing the memory of the communication apparatus based on the access request and a process of communicating with the second apparatus based on the access request. | 05-09-2013 |
| 20130117754 | MULTI-CORE SYSTEM AND SCHEDULING METHOD - A multi-core system includes multiple processor cores; a bus connected to the processor cores; multiple peripheral devices accessed by the processor cores via the bus; profile information including information concerning access of the peripheral devices by each task assigned to the processor cores; a monitor that based on the profile information, monitors access requests to the peripheral devices from tasks under execution at the processor cores and prohibits an access request that causes contention at the bus; and a scheduler that when the monitor prohibits an access request that causes contention at the bus, switches to a different task. | 05-09-2013 |
| 20130117762 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND COMPUTER PRODUCT - An information processing apparatus includes a processor that is configured to detect a changeover request in a first mode in which a first OS executes a process that includes a second OS different from the first OS; and change the first mode over to a second mode in which the second OS executes a process that includes the first OS, upon detecting the changeover request. | 05-09-2013 |
| 20130124804 | DATA RESTORATION PROGRAM, DATA RESTORATION APPARATUS, AND DATA RESTORATION METHOD - A computer-readable recording medium stores a program that causes a computer capable of accessing a multicore processor equipped with volatile memories and a plurality of cores accessing the volatile memories, to execute a data restoration process. The data restoration process includes detecting a suspend instruction to any one of the cores in the multicore processor; and restoring, when the suspend instruction is detected, data stored in a volatile memory accessed by a core receiving the suspend instruction, the data being restored in a shared memory accessed by the cores in operation and based on parity data stored in the volatile memories accessed by the cores in operation other than the core receiving the suspend instruction. | 05-16-2013 |
| 20130125131 | MULTI-CORE PROCESSOR SYSTEM, THREAD CONTROL METHOD, AND COMPUTER PRODUCT - A multi-core processor system includes a first core configured to detect a state where a first thread that is allocated to a first core and a second thread that is allocated to a second core access a common resource; calculate, upon detecting the state and based on a first cycle for the first thread to be allocated to the first core and a second cycle for the second thread to be allocated to the second core, a contention cycle for the first and the second threads to cause access contention for the resource; and select a thread allocated at a time before or after the contention cycle of a core to which a given thread that is either the first or the second thread is allocated at the contention cycle; and a second core configured to switch the times at which the given thread and the selected thread are allocated. | 05-16-2013 |
| 20130132708 | MULTI-CORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND CONTROL METHOD - A multi-core processor system includes a first core that is of a multi-core processor and configured to detect preprocessing for access of shared resources by a second core that is of the multi-core processor excluding the first core, when the first core is accessing the shared resources shared by the multi-core processor; and switch a task being executed by the second core to another task upon detecting the preprocessing. | 05-23-2013 |
| 20130138849 | MULTICORE PROCESSOR SYSTEM, COMPUTER PRODUCT, ASSIGNING METHOD, AND CONTROL METHOD - A multicore processor system includes core configured to detect a process assignment instruction; acquire a remaining time obtained by subtracting a processing time of interrupt processing assigned to an arbitrary core of a multicore processor from a period that is from a calling time of the interrupt processing to an execution time limit of the interrupt processing, upon detecting the process assignment instruction; judge if the remaining time acquired at the acquiring is greater than or equal to a processing time of processing defined to limit an interrupt in the process; and assign the process to the arbitrary core, upon judging that the remaining time is greater than or equal to the processing time of the processing defined to limit an interrupt in the process. | 05-30-2013 |
| 20130138886 | SCHEDULER, MULTI-CORE PROCESSOR SYSTEM, AND SCHEDULING METHOD - A scheduler that causes a given core in a multi-core processor to determine if a priority level of a process that is to be executed by a core of the multi-core processor is greater than or equal to a threshold; save to a cache memory of each core that executes a process having a priority level greater than or equal to the threshold, data that is accessed by the process upon execution; save to a memory area different from the cache memory and to which access is relatively slower, data that is accessed by a process having a priority level not greater than or equal to the threshold; and save the data saved in the memory area, to a cache memory of a requesting core, when the requesting core issues an access request for the data saved in the memory area. | 05-30-2013 |
| 20130151882 | COMPUTER PRODUCT, CONTROL APPARATUS, AND CONTROL METHOD - A computer-readable recording medium stores a control program causing a processor of a first terminal to execute a process that includes detecting that a remaining battery level of the first terminal has become less than or equal to a first threshold while a task is under execution by the first terminal; suspending execution of the task upon detecting that the remaining battery level of the first terminal has become less than or equal to the first threshold; transmitting identification information of the task to a second terminal upon detecting that the remaining battery level of the first terminal has become less than or equal to the first threshold; receiving from the second terminal and after transmitting the identification information of the task, information related to a potential of executing the task; and transmitting to the second terminal, information corresponding to the information related to the potential of executing the task. | 06-13-2013 |
| 20130159397 | COMPUTER PRODUCT, INFORMATION PROCESSING APPARATUS, AND PARALLEL PROCESSING CONTROL METHOD - A computer-readable recording medium stores a parallel processing control program that causes a connection origin processor to execute a process. The process includes measuring a band between the connection origin apparatus and a connection destination apparatus; calculating, based on the measured band, an execution time period for each execution object for which parallel processing is executable by the connection origin processor in the connection origin apparatus and a connection destination processor in the connection destination apparatus, the execution objects having granularities of the parallel processing that differ from each other; selecting from among the execution objects and based on a length of each calculated execution time period, an execution object to be executed; and setting the selected execution object to be executable by the connection origin processor and the connection destination processor in cooperation with each other. | 06-20-2013 |
| 20130160023 | SCHEDULER, MULTI-CORE PROCESSOR SYSTEM, AND SCHEDULING METHOD - In an embodiment, a scheduler coordinates timings at which cores execute processes, for any two sequential processes to consecutively be executable. The processes are executed in order scheduled by the scheduler by concentrating on a specific core processes obstructing the consecutive execution such as an external interrupt and an internal interrupt. The scheduler does not always cause processes of another application to be executed during all standby time periods while the scheduler determines whether a length of a standby time period is shorter than a predetermined value, and does not cause any process of the other application to be executed when the length is shorter than that. | 06-20-2013 |
| 20130179666 | MULTI-CORE PROCESSOR SYSTEM, SYNCHRONIZATION CONTROL SYSTEM, SYNCHRONIZATION CONTROL APPARATUS, INFORMATION GENERATING METHOD, AND COMPUTER PRODUCT - A multi-core processor system includes a given core that includes a detecting unit that detects migration of a thread under execution by a synchronization source core to a synchronization destination core in the multi-core processor; an identifying unit that refers to a table identifying a combination of a thread and a register associated with the thread, and identifies a particular register corresponding to the thread for which migration was detected; a generating unit that generates synchronization control information identifying the synchronization destination core and the particular register; and a synchronization controller that, communicably connected to the multi-core processor, acquires from the given core, the synchronization control information, reads in from the particular register of the synchronization source core, a value of the particular register obtainable from the synchronization control information, and writes to the particular register of the synchronization destination core, the value. | 07-11-2013 |
| 20130185521 | MULTIPROCESSOR SYSTEM AND SCHEDULING METHOD - A multiprocessor system includes a master processor, at least one slave processor, and a synchronization unit. The master processor has a first flag indicating whether the master processor is in a task activation accepting state and a second flag reflective of a flag of a slave processor, iteratively updates the first flag at a frequency based on the volume of tasks processed by the master processor, and activates a task on the master processor or the slave processor based on the first flag and the second flag. Each slave processor has a third flag indicating whether the slave processor is in the task activation accepting state and iteratively updates the third flag at a frequency based on the volume of tasks processed by the slave processor. Tasks are allocated to the slave processor by the master processor. The synchronization unit synchronizes the third flag and the second flag. | 07-18-2013 |
| 20130198270 | DATA SHARING SYSTEM, TERMINAL, AND DATA SHARING METHOD - A data sharing system includes communicable terminals and selects a server-client system in which a first terminal is designated as a server and other terminals are designated as clients, when a sum of estimated time for transferring data to the first terminal from the other terminals, estimated time for performing, by the first terminal, arithmetic processing of the data in the first terminal, and estimated time for transferring arithmetically processed data from the first terminal to the other terminals satisfies a real time restriction, and power estimated to be consumed at a time of performing, by the first terminal, the arithmetic processing of the data in the first terminal is less than power estimated to be consumed at a time of performing the arithmetic processing by the other terminals. The data sharing system selects a peer-to-peer system, when the sum does not satisfy the real time restriction in any terminal. | 08-01-2013 |
| 20130198390 | COMPUTER PRODUCT, TERMINAL, SERVER, DATA SHARING METHOD, AND DATA DISTRIBUTION METHOD - A computer-readable recording medium stores a data sharing program that causes a processor of a first terminal to execute a process that includes detecting a communication bandwidth used between the first terminal and a second terminal that are communicably connected in an ad-hoc network; comparing the detected communication bandwidth and a bandwidth related to a storage apparatus of the first terminal; determining an operation scheme related to data sharing of data in the storage apparatus of the first terminal and data in a storage apparatus of the second terminal, based on a comparison result obtained at the comparing; notifying the second terminal of the determined operation scheme; and executing a mounting process that enables access of the storage apparatus of the first terminal by the second terminal, based on the determined operation scheme. | 08-01-2013 |
| 20130227579 | INFORMATION PROCESSING APPARATUS, COMPUTER PRODUCT, AND INFORMATION PROCESSING METHOD - An information processing apparatus includes a computer configured to set respectively a storage location for each value of a common variable among threads of a thread group having write requests to write the values of the common variable of the threads in a given process, from a specific storage location defined in the write requests, to the storage locations respectively set for the threads; store, for each thread of the thread group, a value of the common variable to the storage location set for the thread; and read out in order of execution of the threads of the thread group defined in the given process and when all the threads in the thread group have ended, each value of the common variable stored at the first storing, and in the order of execution, overwrite a value in the specific storage location with each read value of the common variable. | 08-29-2013 |
| 20130238882 | MULTI-CORE PROCESSOR SYSTEM, MONITORING CONTROL METHOD, AND COMPUTER PRODUCT - A multi-core processor system includes a given core among multiple cores, wherein the given core is configured to detect execution of a process by the cores; and generate upon detecting the execution of the process, a specific thread that saves state information indicating an executed state of the process and an executed state of each thread to be monitored of the process. | 09-12-2013 |
| 20130239113 | INFORMATION PROCESSING APPARATUS, COMPUTER PRODUCT, AND INFORMATION PROCESSING METHOD - An information processing apparatus includes a memory unit having numbers each specifying an output order and a data memory area corresponding to each number; a setting unit that sets in each data memory area correlating an execution order of a thread with a number specifying the output order, a storage location for a value of a common variable of the thread among threads receiving write requests for the value or the common variable; a first storing unit that stores to the data memory area set for each thread, the value of the common variable for the thread of the execution order corresponding to the number specifying the output order of the data memory area; and a second storing unit that upon completion of ail the threads and In the output order, reads-out each value of the common variable stored to the data memory areas and overwrites a specific storage location. | 09-12-2013 |
| 20130246670 | INFORMATION PROCESSING SYSTEM - An information processing system includes a CPU that is connected to a bus; a device that is connected to the bus; a memory that is accessed by the CPU or the device; and a power mode control circuit that sets a power consumption mode. The power mode control circuit sets the power consumption mode based on first information that indicates a cache hit or a cache miss of a cache memory in the CPU and second information that indicates an activated state or a non-activated state of the device. | 09-19-2013 |
| 20130254598 | ACCESS METHOD AND MULTI-CORE PROCESSOR SYSTEM - An access method is executed by a multi-core processor system. The access method includes activating a driver that corresponds to a first CPU, based on a start of execution of a first application; starting measurement of an access time period, based on access of a peripheral device; outputting, when the access time period exceeds a predetermined time period, a detection signal to reset the driver; and prohibiting, when the access time period exceeds a predetermined time period, writing into a register retaining data to be written into the peripheral device from the first CPU. | 09-26-2013 |
| 20130262905 | INFORMATION PROCESSING APPARATUS, COMPUTER PRODUCT, AND INFORMATION PROCESSING METHOD - An information processing apparatus includes a processor configured to detect an unexecuted first thread and an unexecuted second thread; calculate standby power consumption of the first thread in a case of executing the second thread followed by the first thread, based on an execution period of the second thread and standby power consumption per unit time of the first thread; calculate standby power consumption of the second thread in a case of executing the first thread followed by the second thread, based on an execution period of the first thread and standby power consumption per unit time of the second thread; and determine an order of execution of the first thread and the second thread, based on comparison of the standby power consumption of first thread and the standby power consumption of the second thread. | 10-03-2013 |
| 20130275790 | MULTICORE PROCESSOR SYSTEM AND POWER CONTROL METHOD - A multicore processor system includes multiple processors; a device; a memory that stores information of voltage and clock frequency for minimizing power consumption in connection with a number of the processors accessing to the device; and a power control unit that controls the voltage and the clock frequency of the processors on the basis of the information stored in the memory if the number of the processors accessing to the device changes. | 10-17-2013 |
| 20130275996 | SYNCHRONIZATION METHOD - A synchronization method of multiple threads is executed by a computer. The synchronization method includes determining a type of a synchronization process of a first thread performing the synchronization process for synchronization with a second thread; starting time measurement when the type of the synchronization process of the first thread is a first type; performing the synchronization process of the first thread and a synchronization process of the second thread based on a synchronization process history of the second thread when the measured time exceeds a permitted response period of the first thread; and updating the permitted response period and performing the synchronization processes of the first thread and the second thread based on the synchronization process history of the second thread, when another processing request is received. | 10-17-2013 |
| 20130297888 | SCHEDULING METHOD AND MULTI-CORE PROCESSOR SYSTEM - A scheduling method of a scheduler that manages threads is executed by a computer. The scheduling method includes selecting a CPU of relatively less load, when a second thread is generated from a first thread to be processed; determining whether the second thread operates exclusively from the first thread; copying a first storage area assessed by the first thread onto a second storage area managed by the CPU, when the second thread operates exclusively; calculating based on an address of the second storage area and a predetermined value, an offset for a second address for the second thread to access the first storage area; and notifying the CPU of the offset for the second address to convert a first address to a third address for accessing the second storage area. | 11-07-2013 |
| 20130298132 | MULTI-CORE PROCESSOR SYSTEM AND SCHEDULING METHOD - A multi-core processor system includes plural processors; and a scheduler that assigns applications to the processors. The scheduler upon receiving a startup request for a given application and based on start times of the applications executed by the processors, selects a processor that is to execute the given application. | 11-07-2013 |
| 20130298137 | MULTI-TASK SCHEDULING METHOD AND MULTI-CORE PROCESSOR SYSTEM - A multi-task scheduling method includes assigning a first thread to a first processor; detecting a second thread that is executed after the first thread; calculating based on a load of a processor that is assigned a third thread that generates the second thread, a first time that lasts until a start of the second thread; calculating a second time that lasts until completion of execution of the first thread; and changing a first time slice of the first processor to a second time slice when the second time is greater than the first time. | 11-07-2013 |
| 20130303221 | SCHEDULING METHOD - A scheduling method includes acquiring first information, second information, and third information from a first terminal located in a service area of a first base station; determining based on the first information, the second information, and the third information, whether a first process assigned to the first terminal is to be collected; and assigning the first process to a second terminal located in the service area of the first base station, when at the determining the first process is determined to be collected. | 11-14-2013 |
| 20130305251 | SCHEDULING METHOD AND SCHEDULING SYSTEM - A scheduling method is performed by a scheduler that manages plural processors including a first processor and a second processor. The scheduling method includes assigning an application to the first processor when the application is started; instructing the second processor to calculate load of the processors; and maintaining assignment of the application or changing assignment of the application based on the load. | 11-14-2013 |
| 20130305257 | SCHEDULING METHOD AND SCHEDULING SYSTEM - A scheduling method is executed by a given CPU among multiple CPUs. The scheduling method includes subtracting for each of the CPUs, a number of processes assigned to the CPU from a maximum number of speculative processes that can be assigned to each of the CPUs; summing results yielded at the subtracting to yield a total number of speculative processes; and assigning to the CPUs, speculative processes of a number is less than or equal to the total number of speculative processes. | 11-14-2013 |
| 20130311727 | MEMORY CONTROL METHOD AND SYSTEM - A memory control method includes assigning based on a table to which an allocated device that executes a first process in a first application is registered, the first process in the first application to the allocated device registered; notifying a port connector of identification information of a port of memory, the port to be used by the first application, and registering a number of the port into the table; and allocating a storage area to the port and registering an address of the storage area into the table. | 11-21-2013 |
| 20130311751 | SYSTEM AND DATA LOADING METHOD - A system includes plural processors; memory that stores a program currently under execution by the processors; and a pre-loader that pre-loads into a fragment area of the memory, a target program that is to be executed and is a program other than the program currently under execution by the processors. | 11-21-2013 |
| 20130312002 | SCHEDULING METHOD AND SCHEDULING SYSTEM - A scheduling method executed by a scheduler that manages multiple processors, includes detecting based on an application information table when a first application is started up, a processor that executes a second application that is not executed concurrently with the first application; and assigning the first application to the processor. | 11-21-2013 |
| 20130318310 | PROCESSOR PROCESSING METHOD AND PROCESSOR SYSTEM - A processor processing method is executed by a memory controller, and includes determining based on a log of access of a shared resource by a first application, whether the first application running on a first processor operates normally; and causing a second processor to run a second application other than the first application upon the first application being determined to not be operating normally. | 11-28-2013 |
| 20130318375 | PROGRAM EXECUTING METHOD - A program executing method is executed by a computer and includes calculating a first power consumption for execution of a first program described by first code; calculating a second power consumption for execution of a second program of a function identical to that of the first program and described by second code; and converting the first program into the second program and executing the second program, if the second power consumption is less than the first power consumption. | 11-28-2013 |
| 20130326527 | SCHEDULING METHOD, SYSTEM DESIGN SUPPORT METHOD, AND SYSTEM - A scheduling method is executed by a processor, and includes detecting a transition from a first process to a second process; acquiring from memory, an operating frequency and a CPU count for executing the second process; suspending a CPU under operation or starting a suspended CPU, based on the CPU count; and assigning the operating frequency to a CPU that is to execute the second process. | 12-05-2013 |
| 20130331108 | COMMUNICATION APPARATUS AND COMMUNICATION METHOD - A communication apparatus includes a first CPU that is capable of executing a communication process at a first processing speed; a measuring unit that measures a first transmission speed when the communication process is executed with a base station; a collecting unit that collects from at least one other apparatus, a second transmission speed between the base station and the apparatus, and a second processing speed of a second CPU included in the other apparatus based on the first transmission speed; a determining unit that determines whether the communication process is to be transferred to the other apparatus, based on the second transmission speed and the second processing speed; and a transferring unit that transfers the communication process to the other apparatus based on a determination result. | 12-12-2013 |
| 20130339632 | PROCESSOR MANAGEMENT METHOD - A processor management method includes setting a master mechanism in a given processor among multiple processors, where the master mechanism manages the processors; setting a local master mechanism and a virtual master mechanism in each of processors other than the given processor among the processors, where the local master mechanism and the virtual master mechanism manage each of the processors; and notifying by the master mechanism, the processors of an offset value of an address to allow a shared memory managed by the master mechanism to be accessed as a continuous memory by the processors. | 12-19-2013 |
| 20140006666 | TASK SCHEDULING METHOD AND MULTI-CORE SYSTEM | 01-02-2014 |
| 20140007131 | SCHEDULING METHOD AND SCHEDULING SYSTEM | 01-02-2014 |
| 20140007135 | MULTI-CORE SYSTEM, SCHEDULING METHOD, AND COMPUTER PRODUCT | 01-02-2014 |
| 20140012921 | FILE SHARING METHOD AND TERMINAL - A file sharing method executed by a first terminal, and including selecting from among multiple terminals including the first terminal and based on a remaining battery level of the terminals and a processing time of a shared process, a second terminal to execute the shared process for sharing multiple files among the terminals; and assigning the shared process to the second terminal. | 01-09-2014 |
| 20140019710 | ENDIAN CONVERSION METHOD AND SYSTEM - An endian conversion method is executed by a CPU, and includes executing a program that includes endian conversion setting; and performing, when accessing an address of a main memory indicated in the endian conversion setting, endian conversion of data specified by the address of the main memory. | 01-16-2014 |
| 20140019717 | SYNCHRONIZATION METHOD, MULTI-CORE PROCESSOR SYSTEM, AND SYNCHRONIZATION SYSTEM - A synchronization method is executed by a multi-core processor system. The synchronization method includes registering based on a synchronous command issued from a first CPU, CPUs to be synchronized and a count of the CPUs into a specific table; counting by each of the CPUs and based on a synchronous signal from the first CPU, an arrival count for a synchronous point, and creating by each of the CPUs, a second shared memory area that is a duplication of a first shared memory area accessed by processes executed by the CPUs; and comparing the first shared memory area and the second shared memory area when the arrival count becomes equal to the count of the CPUs, and based on a result of the comparison, judging the processes executed by the CPUs. | 01-16-2014 |
| 20140019989 | MULTI-CORE PROCESSOR SYSTEM AND SCHEDULING METHOD - A multi-core processor system includes plural CPUs; memory that is shared among the CPUs; and a monitoring unit that instructs a change of assignment of threads to the CPUs based on a first process count stored in the memory and representing a count of processes under execution by the CPUs and a second process count representing a count of processes assigned to the CPUs, respectively. | 01-16-2014 |
| 20140025903 | MULTI-CORE PROCESSOR SYSTEM - A multi-core processor system includes CPUs; memory; and a memory protect controller that is disposed between the plurality of CPUs and the memory, and that accesses a first memory area consequent to an access request of the CPUs upon application execution and further accesses a second memory area established when the system is booted. | 01-23-2014 |
| 20140026143 | EXCLUSIVE ACCESS CONTROL METHOD AND COMPUTER PRODUCT - An exclusive access control method is executed by a computer having an operating system that when an excluded thread accesses a shared resource, executes a first exclusive access control process of prohibiting the excluded thread from attempting to access the shared resource until exclusive access control is released, the exclusive access control process being executed according to a number of attempts, by the excluded thread, to access the shared resources. The exclusive access control method includes counting by at least one second thread, including the excluded thread and different from a first thread, the number of attempts to access the shared resource, when the first thread executes a second exclusive access control process of allowing the excluded thread to attempt to access the shared resource until the excluded thread is permitted access; and storing to a memory area by the second thread, the counted number of attempts. | 01-23-2014 |
| 20140032700 | DATA PROCESSING METHOD AND MOBILE TERMINAL - A data processing method is executed by a first device, and includes suspending execution of a first process by the first device that belongs to a first device group that includes plural devices; saving based on a request for execution of a second process from a second device that belongs to a second device group that includes plural devices, process information of the first process to shared memory that is set in each of the devices of the first device group and shared by the devices of the first device group; and releasing the saving of the process information of the first process consequent to completion of the execution of the second process. | 01-30-2014 |
| 20140033215 | SCHEDULING METHOD AND SCHEDULING SYSTEM - A scheduling method that is executed by a first device includes acquiring in response to a process request received by the first device, any one among a device count of peripheral devices near the first device and a device count of the peripheral devices near the first device, including the first device; and determining, by a CPU of the first device, a scheduling method for scheduling a process corresponding to the process request, based on the device count. | 01-30-2014 |
| 20140045512 | SCHEDULING METHOD AND TASK PROCESSING METHOD - A scheduling method is executed by a first apparatus among a plurality of apparatuses. The scheduling method includes assigning a process to at least one apparatus among the apparatuses based on a first table that includes each communication strength of the apparatuses; receiving an execution result of the process and a communication strength from the at least one apparatus; and creating the first table based on the received communication strength. | 02-13-2014 |
| 20140052806 | DATA ALLOCATION METHOD AND DATA ALLOCATION SYSTEM - A data allocation method executed by a data allocation system. The data allocation method includes allocating to a first processing apparatus included among a plurality of processing apparatuses and allocating based on a first communication speed of the first processing apparatus, data having communication amount information on a frequency at which the processing apparatuses access the data, and further supplying first priority level information to the first processing apparatus; and exchanging based on variation of a communication speed of at least one processing apparatus among the processing apparatuses, the data or the first priority level information, and data or second priority level information allocated to a second processing apparatus included among the processing apparatuses and having a second communication speed. | 02-20-2014 |
| 20140053012 | SYSTEM AND DETECTION MODE - A system includes a CPU; a sensor that detects power of the CPU; a cache memory state monitoring circuit that monitors a state of a cache memory; and a detection circuit that based on a sensor signal from the sensor and a state signal from the cache memory state monitoring circuit, detects a spin state of a program executed by the CPU. | 02-20-2014 |
| 20140053162 | THREAD PROCESSING METHOD AND THREAD PROCESSING SYSTEM - A thread processing method is executed by a specific apparatus included among a plurality of apparatuses, and includes assigning one thread among a plurality of threads to the apparatuses, respectively; acquiring first time information that indicates a time at which the specific apparatus receives an execution result of a corresponding thread from each of the apparatuses; and setting a priority level of an access right to access shared memory that is shared by the apparatuses and the specific apparatus, the setting being based on the first time information and second time information that indicates a time at which reception of execution results of the threads from the apparatuses ends. | 02-20-2014 |
| 20140053163 | THREAD PROCESSING METHOD AND THREAD PROCESSING SYSTEM - A thread processing method that is executed by a multi-core processor, includes supplying a command to execute a first thread to a first processor; judging a dependence relationship between the first thread and a second thread to be executed by a second processor; comparing a first threshold and a frequency of access of any one among shared memory and shared cache memory by the first thread; and changing a phase of a first operation clock of the first processor when the access frequency is greater than the first threshold and upon judging that no dependence relationship exists. | 02-20-2014 |
| 20140082041 | DATA PROCESSING METHOD - A data processing method is executed by a processor, and includes detecting an addition request to add a first device to a first group that includes a plurality of devices; registering the first device into a main group in which devices of the first group are registered, the first device being registered when the first device does not belong to a second group that is different from the first group; registering the first device into a subgroup, when the first device belongs to the second group; and performing by the devices registered in the main group, distributed processing that includes a plurality of tasks. | 03-20-2014 |
| 20140082637 | DATA PROCESSING METHOD AND DATA PROCESSING SYSTEM - A data processing method executed by a first data processing apparatus and includes acquiring process information concerning a first process, in response to a process request for the first process; setting a first process flag included in the process information concerning the first process to indicate “true”; setting a first end flag of the process information concerning the first process to indicate “true” after executing the first process; acquiring process information concerning a second process that is to be executed before a third process that is to be executed subsequent the first process; and determining a process to be executed, based on a second process flag and a second end flag included in the process information concerning the second process. | 03-20-2014 |
| 20140089377 | DATA SHARING METHOD AND DATA PROCESSING SYSTEM - A data sharing method includes detecting by a first data processing apparatus that is among multiple data processing apparatuses that share data, any one among a shortage of available memory, a change in remaining battery power, a change in a relative positional distance of the first data processing apparatus to a second data processing apparatus that is among the data processing apparatuses, a change in a communication speed of communication with the second data processing apparatus, and an interruption of communication with the second data processing apparatus; and transmitting by the first data processing apparatus to a third data processing apparatus that is among the data processing apparatuses, a shared portion of the data saved in the first data processing apparatus. | 03-27-2014 |
| 20140092747 | DATA COMMUNICATION METHOD AND DATA COMMUNICATION SYSTEM - A data communication method includes determining by a first terminal apparatus that is included among plural terminal apparatuses capable of direct communication with one another, whether a communication volume of data received from a second terminal apparatus that is included among the terminal apparatuses exceeds a processable communication volume; and transmitting by the first terminal apparatus to the second terminal apparatus, a portion of the data of a given communication volume, when the communication volume of the data exceeds the processable communication volume. | 04-03-2014 |
| 20140095573 | DATA COMMUNICATION METHOD AND DATA COMMUNICATION SYSTEM - A data communication method includes registering as a group and by a first data processing device of plural data processing devices, at least one second data processing device capable of communicating with the first data processing device; transmitting by the first data processing device and to the data processing devices, a first reception request for data; transmitting by the first data processing device and to the at least one second data processing device, a second reception request for the data when there is no response to the first reception request from the first data processing devices; and transmitting the data to the second data processing device, by the first data processing device and based on a response from the second data processing device. | 04-03-2014 |
| 20140108758 | DATA PROCESSING METHOD AND DATA PROCESSING SYSTEM - A data processing method that is executed by a first data processing apparatus included among plural data processing apparatuses, includes producing a copy of data, and restoration information that includes a first address of memory to which the copy of the data is stored; transmitting any one among the data and the copy of the data to a second data processing apparatus that is included among the data processing apparatuses; and storing the restoration information to shared memory that is memory of at least one data processing apparatus among the data processing apparatuses, and shared among the data processing apparatuses. | 04-17-2014 |
| 20140109100 | SCHEDULING METHOD AND SYSTEM - A scheduling method that is executed by a first CPU includes determining whether a task belongs to a first task category; determining whether a first access area accessed by the task is located in a first memory or a second memory, when the task belongs to the first task category; and setting a memory accessed by the task to the first memory or the second memory, based on a result at the determining. | 04-17-2014 |
| 20140115601 | DATA PROCESSING METHOD AND DATA PROCESSING SYSTEM - A data processing method that is executed by a processor includes determining based on a size of an available area of a first memory whether first data of a first thread executed by a first data processing apparatus among a plurality of data processing apparatuses is transferable to a first memory; transferring second data that is of a second thread and stored in the first memory to second memory, when at the determining, the first data is determined to not be transferrable; and transferring the first data to the first memory. | 04-24-2014 |
| 20140122632 | CONTROL TERMINAL AND CONTROL METHOD - A control terminal has access to a storage apparatus storing a first processing period for execution of an application by sequential processing and a second processing period for execution of the application by parallel processing; and includes a processor configured to transmit an execution request for the application to a request terminal upon accepting a startup instruction for the application; receive a response to the execution request; determine whether a sum of the second processing period and a difference of a reception time of the response and a transmission time of the execution request, is at least the first processing period; and execute the application by sequential processing by the control terminal when the sum is at least equal to the first processing period, and execute the application by parallel processing using the control terminal and the request terminal when the sum is less than the first processing period. | 05-01-2014 |
| 20140123154 | DATA PROCESSING METHOD AND DATA PROCESSING SYSTEM - A data processing method that is executed by a data processing system includes determining whether an application whose startup is requested by a first data processing apparatus among a plurality of data processing apparatuses, belongs to a predetermined group; determining whether a second data processing apparatus among the data processing apparatuses has started up the application, when the application belongs to the predetermined group; and aborting startup of the application by the first data processing apparatus, when the second data processing apparatus has started up the application. | 05-01-2014 |
| 20140129811 | MULTI-CORE PROCESSOR SYSTEM AND CONTROL METHOD - A multi-core processor system includes a multi-core processor that has plural core groups; and a storage device that stores a constraint on execution time for each application. A first identified core of the multi-core processor is configured to identify a constraint on execution time of a given application that is among the applications and for which an invocation instruction is received; determine whether the identified constraint meets a performance drop condition; assign the given application to a predetermined core of the multi-core processor, upon determining that the identified constraint meets the performance drop condition; and notify a second identified core of a core group among the core groups, of an assignment instruction for the given application, upon determining that the identified constraint does not meet the performance drop condition. | 05-08-2014 |
| 20140143788 | ASSIGNMENT METHOD AND MULTI-CORE PROCESSOR SYSTEM - An assignment method executed by a given core of a multi-core processor includes identifying for each core, the number of storage areas to be used by a given thread and the number of storage areas used by threads already assigned; detecting for each core, a highest value from the number of storage areas used by the threads already assigned; determining whether a sum of a greater value of the detected highest value of a core selected as a candidate assignment destination and the number of storage areas to be used by the given thread, and the detected highest value of the cores excluding the selected core, is at most the number of storage areas of the shared resource; and assigning the given thread to the selected core, when the sum is at most the number of storage areas of the shared resource. | 05-22-2014 |
| 20140143790 | DATA PROCESSING SYSTEM AND SCHEDULING METHOD - A data processing system includes an interrupt controller that counts, as an interrupt processing execution count, executions of interrupt processing by threads executed by data processing devices; and a processor that is configured to select one scheduling method from among a plurality of scheduling methods, based on the interrupt processing execution count. | 05-22-2014 |
| 20140149691 | DATA PROCESSING SYSTEM AND DATA PROCESSING METHOD - A data processing system includes multiple data processing apparatuses; a peripheral apparatus; memory that is shared by the data processing apparatuses and the peripheral apparatus; peripheral memory provided corresponding to the peripheral apparatus; and a memory managing unit that secures in any one among the memory and the peripheral memory, an area for a thread that is based on thread information, the area being secured based on the thread information that is read out from a heap area that sequentially stores the thread information that is executed at any one among the data processing apparatuses and the peripheral apparatus. | 05-29-2014 |
| 20140149991 | SCHEDULING SYSTEM, DATA PROCESSING SYSTEM, AND SCHEDULING METHOD - A scheduling system includes a processor that is configured to assign a process to at least one data processing system among plural data processing systems, based on an execution request for the process; estimate time consumed for completion of a first process, when the process is the first process; and append specific information to the first process, based on the estimated time. | 05-29-2014 |
| 20140157280 | SCHEDULING METHOD AND SCHEDULING SYSTEM - A scheduling method includes determining whether priority of an application to be activated is of a given priority, the determining being performed by a first data processing apparatus that is included in a first group having at least one data processing apparatus; transferring to a second data processing apparatus that is included in any one among a second group and the first group, a predetermined function of the first data processing apparatus so as to execute the application by the first data processing apparatus, the transferring being performed when the priority of the application is of the given priority, and the first and the second groups being among a plurality of groups that each includes at least one data processing apparatus; and placing the application in an execution queue of the first data processing apparatus, when the priority of the application is not the given priority. | 06-05-2014 |
| 20140164468 | DATA PROCESSING METHOD - A data processing method is executed by a first data processing apparatus, and includes setting based on a size of data that is for executing a predetermined function, a first division number for dividing the data; producing groups of a second division number, each including N (a positive integer) elements by dividing the first division number; assigning a plurality of data processing apparatuses each capable of communicating with the first data processing apparatus, to the groups of the second division number; and assigning sub-data formed by dividing the data by the first division number, to the groups of the second division number. | 06-12-2014 |
| 20140189185 | INTERRUPT MONITORING SYSTEM AND COMPUTER SYSTEM - An interrupt monitoring apparatus includes a storage that stores a given threshold that corresponds to an external interrupt notification; a measuring circuit that measures time that elapses from a time when the external interrupt notification is received until a time when dispatch notification is received from a CPU; a comparing circuit that compares the given threshold and the time measured by the measuring circuit; and an output circuit that outputs to the CPU, a comparison result obtained by the comparing circuit. | 07-03-2014 |
| 20140201546 | POWER SUPPLY CONTROL METHOD AND SYSTEM - A power supply control method includes detecting that a result of a first function performed by a first device ceases to be displayed on a display screen; suspending power supply to the first device and supplying power to a second device, based on a detection of the result ceasing to be displayed; and causing the second device to output a response signal to a CPU in response to a control signal from the CPU. | 07-17-2014 |
| 20140222229 | POWER CONTROL APPARATUS, ELECTRONIC COMPUTER, AND POWER CONTROL METHOD - A power control apparatus includes a processor configured to collect first information related to operation of a performing unit configured to perform data processing and information related to operation of a bus configured to transfer data; determine an operating frequency and an operating voltage for the performing unit, based on the collected information; estimate based on the collected information, a period elapsing until the performing unit suspends operation and a period elapsing until the bus suspends operation; derive a discriminant that obtains a difference of total power consumption and power consumption pre-switching; and execute a switching of an operating frequency and an operating voltage of the performing unit, based on a value of the discriminant. | 08-07-2014 |
| 20140237150 | ELECTRONIC COMPUTER AND INTERRUPT CONTROL METHOD - An electronic computer includes a processor that executes a thread and an interrupt handler, and monitors load of the processor; and an interrupt controller that is configured to determine a notification timing for an interrupt request to call the interrupt handler, the notification timing being determined based on the load and an effect of execution of the interrupt handler on user performance of the thread under execution by the processor; and notify the processor of the interrupt request, based on the notification timing. When the load is higher than a threshold, the interrupt controller sets the notification timing for an interrupt request that does not affect the user performance, to be later than the notification timing for an interrupt request that affects the user performance. Based on notification of the interrupt request, the processor calls and executes the interrupt handler that corresponds to the interrupt request. | 08-21-2014 |
| 20140241277 | COMMUNICATION METHOD AND COMMUNICATIONS APPARATUS - A communication method includes performing, by a processor, digital processing for radio communication by multiple communication schemes; combining based on an actual communication state and within a processing capability of the processor, one or more among the communication schemes; and performing concurrent communication. | 08-28-2014 |
| 20140282588 | SYSTEM AND SCHEDULING METHOD - A system includes a CPU; an accelerator; a comparing unit that compares a first value that is based on a first processing time period elapsing until the CPU completes a first process and a second processing time period elapsing until the accelerator completes the first process, and a second value that is based on a state of use of a battery driving the CPU and the accelerator; and a selecting unit that selects any one among the CPU and the accelerator, based on a result of comparison by the comparing unit. | 09-18-2014 |
| 20140310723 | DATA PROCESSING APPARATUS, TRANSMITTING APPARATUS, TRANSMISSION CONTROL METHOD, SCHEDULING METHOD, AND COMPUTER PRODUCT - A data processing apparatus includes a processor configured to receive an interrupt request that is a trigger for execution of an interrupt process executed by the processor; store the received interrupt request to a recording area; calculate based on a time when the interrupt request is received and particular time information read from the recording area, a predicted time when a subsequent interrupt request is to be received; detect a thread to be executed by the processor, among executable threads of the processor; judge based on the calculated predicted time and a current time, whether there is a possibility of the interrupt process being executed while the detected thread is under execution; decide based on a judgment result, whether to execute the detected thread on the processor; and execute the detected thread on the processor, based on a decision result. | 10-16-2014 |
| 20140316745 | DETECTING APPARATUS, DETECTING METHOD, AND COMPUTER PRODUCT - A detecting apparatus includes processors configured to access sensors; select from among the sensors, a sensor that has not been selected by any processor, acquire data from the selected sensor, and release selection of the sensor when data acquisition has been completed; execute processing for the sensor, based on the acquired data; set the sensor to an execution state during execution of the processing for the sensor, and set the sensor to an execution completed state when the execution of the processing for the sensor has ended; copy from a processor that has set the sensor to the execution state, the data acquired from the sensor by the processor, upon determining the sensor to be in the execution state, without executing the data acquisition; and execute the processing for the sensor, based on the copied data. | 10-23-2014 |
| 20140380333 | DETECTION APPARATUS, NOTIFICATION METHOD, AND COMPUTER PRODUCT - A coprocessor stores to local memory, a driver execution start time, for each execution start of drivers. If a CPU call process is executed during the execution of driver A, the coprocessor calculates the difference of the execution start time and the current time, for drivers B and C. Taking driver C as an example, the coprocessor adds to the difference calculated for the driver C, a processing time required for the CPU call process of driver A and a processing time required for a normal process of driver B. The coprocessor determines whether respective addition results for driver C comply with respective time constraints. If it is determined that an addition result for the driver C cannot comply with the time constraint, and the coprocessor sends an execution request for driver C to another coprocessor. | 12-25-2014 |
| 20150019837 | DATA PROCESSOR - A data processor includes: a plurality of controllers that process data; a program memory that stores a standby instruction and a data processing instruction at a plurality of addresses respectively; and a queue that stores different execution start addresses for the plurality of controllers, wherein after the plurality of controllers sequentially access the queue, the plurality of controllers acquire the different execution start addresses from the queue in an order of the sequential access, start execution of instructions from the acquired different execution start addresses in the program memory, and execute the data processing instruction and execute the standby instruction the number of times different for each of the controllers. | 01-15-2015 |
| 20150081942 | MULTI-CORE PROCESSOR SYSTEM, COMPUTER PRODUCT, AND CONTROL METHOD - A multi-core processor system includes a given configured to queue an interrupt process of a software interrupt request to the given core, and execute queued processes in the order of queuing at the given core; execute preferentially an interrupt process of a hardware interrupt request to the given core over a process under execution at the given core; determine whether the software interrupt request is a specific software interrupt request; and perform control to preferentially execute the interrupt process without queuing, upon determining that the software interrupt request is the specific software interrupt request. | 03-19-2015 |
