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| 20090080374 | METHOD OF CREATING AND DELETING SERVICE FLOW FOR ROBUST HEADER COMPRESSION, AND WIRELESS COMMUNICATION SYSTEM SUPPORTING THE SAME - A method of creating a service flow for ROHC in a control station is disclosed, which can establishes a ROHC channel between ROHC entities, the method comprising obtaining a first ROHC parameter from a ROHC entity of the control station, upon receiving a subscriber profile to which ROHC is applied; and transmitting a first message including the first ROHC parameter for requesting the creation of service flow to a mobile station related with the subscriber profile and a base station performing a dynamic service addition (DSA) procedure through the use of a second message including the first ROHC parameter. | 03-26-2009 |
| 20090080422 | HEADER-COMPRESSION PACKET PROCESSING METHOD, MOBILE STATION, BASE STATION, AND CONTROL STATION IN WIRELESS COMMUNICATION SYSTEM - A header-compression packet processing method in a wireless communication system is disclosed, which can transmit a header-compression packet through a packet transmission path mapped to a service flow, the method comprising, when a service flow of a downlink packet is mapped to a header-compression transmission channel, obtaining a second packet by adding a header-compression context ID mapped to an IP flow of the downlink packet to a first packet made by compressing a header of the downlink packet, in a control station; adding a data path tag mapped to the service flow of the downlink packet to the second packet; and transmitting the second packet with the data path tag to a base station maintaining mapping information of a connection ID for a corresponding mobile station and the data path tag, so as to transmit the second packet with the data path tag to the corresponding mobile station using the header-compression transmission channel. | 03-26-2009 |
| 20100235515 | Method and apparatus for managing connection - A method and apparatus for managing connection is disclosed, which is capable of realizing an efficient management through a bi-directional connection, the method comprising pairing two uni-directional connections between a receiver and a transmitter, if Internet service to be provided requires bi-directional data delivery capability; and creating a second uni-directional connection by assigning the second uni-directional connection at the time of creating a first uni-directional connection for the Internet service, wherein the first uni-directional connection is opposite to the second uni-directional connection. | 09-16-2010 |
| 20100302986 | APPARATUS AND METHOD FOR SUPPORTING MCBCS PROXY SELECTION FOR MCBCS AND MACRO DIVERSITY IN WIRELESS COMMUNICATION SYSTEM - An apparatus and method for supporting MultiCast and BroadCast Service (MCBCS) proxy selection for MCBCS and macro diversity in a wireless communication system is provided. The apparatus and method selects a first MCBCS proxy among MCBCS proxies in the plurality of ASNs as a master MCBCS proxy, and selects other MCBCS proxies except for the first MCBCS proxy as slave MCBCS proxies, and the first MCBCS proxy transmits information for macro diversity to the slave MCBCS proxies, wherein the master MCBCS proxy first receives an MCBCS join message from a Mobile Station (MS) in one Multicast and Broadcast Service (MBS) zone. | 12-02-2010 |
| 20100302989 | METHOD AND APPARATUS FOR SUPPORTING MULTICAST BROADCAST SERVICE (MBS) IN WIMAX - Disclosed is a mobile internet system, and more particularly, to a method and apparatus for supporting a multicast broadcast service (MBS) over WIMAX. The MBS supporting method of the present invention comprises assigning a first GRE key to a first MBS service flow for a first MS, and delivering MBS contents having the first MBS service flow through the use of first GRE key; and if a second MBS service flow for a second MS is the same as the first MBS service flow, delivering MBS contents having the second MBS service flow through the use of first GRE key pre-assigned to the first MBS service flow. | 12-02-2010 |
| 20110103379 | TCP ACK PACKET TRANSMISSION AND RECEPTION METHOD, AND A DEVICE SUPPORTING THE SAME - Disclosed is a broadband wireless network, and more particularly, to a method for transmitting and receiving a TCP ACK packet, and a device supporting the same, wherein the method for transmitting and receiving a TCP ACK packet receiving TCP ACK packets and data packets from an upper layer; creating a MAC PDU by unifying the TCP ACK packet and data packet buffered in the same queue among the received TCP ACK packets and data packets; and transmitting the MAC PDU to a physical layer. | 05-05-2011 |
| 20110317612 | MULTICAST AND BROADCAST SERVICE SYSTEM AND METHOD - The present invention relates to a multicast and broadcast service (MCBCS) system and method. According to the present invention, the MCBCS system comprises: an MBS distribution DPF (Data Patch Function) for receiving MBS data from an MCBCS server/controller and distributing the data; an MBS synchronization controller for acquiring GRE (Generic Routing Encapsulation) for the MBS data from the MBS distribution DPF and then generating an MBS synchronization rule; an MBS synchronization executor for executing MBS synchronization on the MBS synchronization rule received from the MBS synchronization controller; and an MBS DPF for receiving MBS data from the MBS distribution DPF, packaging the MBS data into an MBS burst and then transmitting the data to an MS (Mobile station). As such, multicast and broadcast services can be provided efficiently. | 12-29-2011 |
| 20130117456 | METHOD AND APPARATUS FOR MANAGING CONNECTION - A method and apparatus for managing connection is disclosed, which is capable of realizing an efficient management through a bi-directional connection, the method comprising pairing two uni-directional connections between a receiver and a transmitter, if Internet service to be provided requires bi-directional data delivery capability; and creating a second uni-directional connection by assigning the second uni-directional connection at the time of creating a first uni-directional connection for the Internet service, wherein the first uni-directional connection is opposite to the second uni-directional connection. | 05-09-2013 |
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| 20110188176 | APPARATUS AND METHOD FOR DATA ENTRY FROM A REMOVABLE PORTABLE DEVICE COVER - One or more apparatuses and methods are disclosed for data entry from a removable portable device cover which are configured to cover, surround, and/or encapsulate at least a portion of an exterior shell of a portable electronic device. In one embodiment of the invention, a physical keyboard is operatively connected and/or attached to a removable portable device frame of the removable portable device cover, wherein the removable portable device frame is designed to fit a portable electronic device. In some embodiments of the invention, the operative connection and/or attachment of a physical keyboard to a removable portable frame may be accomplished by using straps, connector ports, and/or wireless protocols. Furthermore, a physical keyboard operatively connected and/or attached to the removable portable device frame may be a foldable physical keyboard which enables easy touch-typing for a user if the foldable physical keyboard is fully expanded. | 08-04-2011 |
| 20110230261 | APPARATUS AND METHOD FOR USING A DEDICATED GAME INTERFACE ON A WIRELESS COMMUNICATION DEVICE WITH PROJECTOR CAPABILITY - Apparatuses and methods are disclosed for a game interface on a wireless communication device with projector capability. In one example, an apparatus has an integrated projector lens on a casing of a wireless communication device and a dedicated game interface with a directional control and a fire button. In another example, an apparatus has a dedicated game interface with at least one directional control, a fire button, and a projector body with a projector lens which can extend from, retract to, or dock with a casing of a wireless communication device. Furthermore, this apparatus may include a novel hardware and/or software module which can invert, adjust, and/or re-orient a desired image before a corrected orientation of the desired image is projected from the integrated projector lens, depending on frontal, rear, or another surface usage of the wireless communication device by the user. | 09-22-2011 |
| 20120068936 | Apparatus and Method for Automatic Enablement of a Rear-Face Entry in a Mobile Device - The present invention discloses one or more embodiments of a mobile device capable of automatic enablement of a rear-face data entry. In a preferred embodiment of the invention, the mobile device can automatically detect and determine that a rear-face data entry interface is either facing up or facing the user's line of sight, which prompts activation of the rear-face data interface for immediate enablement of data entry (e.g. typing). If the rear-face data entry interface is either facing down or away from the user's line of sight, the mobile device disables the rear-face data interface for data entry to minimize accidental and undesirable data entry via the rear-face data interface. The preferred embodiment of the invention also incorporates a primary frontal touch-screen display, a secondary rear touch-screen display, a QWERTY keyboard, and display elevation guards on both displays. | 03-22-2012 |
| 20120243163 | Apparatus and Method for Data Entry from a Removable Portable Device Cover - One or more apparatuses and methods are disclosed for data entry from a removable portable device cover which are configured to cover, surround, and/or encapsulate at least a portion of an exterior shell of a portable electronic device. In one embodiment of the invention, a physical keyboard is operatively connected and/or attached to a removable portable device frame of the removable portable device cover, wherein the removable portable device frame is designed to fit a portable electronic device. In some embodiments of the invention, the operative connection and/or attachment of a physical keyboard to a removable portable frame may be accomplished by using straps, connector ports, and/or wireless protocols. Furthermore, a physical keyboard operatively connected and/or attached to the removable portable device frame may be a foldable physical keyboard which enables easy touch-typing for a user if the foldable physical keyboard is fully expanded. | 09-27-2012 |
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| 20090249026 | Vector instructions to enable efficient synchronization and parallel reduction operations - In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed. | 10-01-2009 |
| 20100073368 | METHODS AND SYSTEMS TO DETERMINE CONSERVATIVE VIEW CELL OCCLUSION - Methods and systems to determine view cell occlusion, including to project objects of a 3-dimensional graphics environment to a 2-dimensional image plane with respect to the view point, to reduce sizes of corresponding object images, to generate an occluder map from the reduced-size object images, to compare at least a portion of the object images to the occluder map, and to identify an object as occluded with respect to the view cell when pixel depth values of the object image are greater than corresponding pixel depth values of the occluder map. Methods and systems to reduce an object image size include methods and systems to nullify pixel depth values within a radius of an edge pixel, and to determine the radius as a distance from the edge pixel to a second pixel so that a line between the view point and the second pixel is parallel with one or more of a line and a plane that is tangential to a sphere enclosing the view cell and a point on the object that corresponds to the edge pixel. | 03-25-2010 |
| 20110138122 | GATHER AND SCATTER OPERATIONS IN MULTI-LEVEL MEMORY HIERARCHY - Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed. | 06-09-2011 |
| 20110161060 | Optimization-Based exact formulation and solution of crowd simulation in virtual worlds - A method of computing a collision-free velocity ( | 06-30-2011 |
| 20110320913 | RELIABILITY SUPPORT IN MEMORY SYSTEMS WITHOUT ERROR CORRECTING CODE SUPPORT - Methods and apparatuses for error correction. A N-bit block data to be stored in a memory device is received. The memory device does not perform any error correction code (ECC) algorithm nor provide designated error correction code storage for the N-bit block of data. Data compression is applied to the N-bit data to compress the block of data to generate a M-bit compressed block of data. A K-bit ECC is computed for the M-bit compressed data, wherein M+K is less than or equal to N. The M-bit compressed data and the K-bit ECC are stored together in the memory device. | 12-29-2011 |
| 20120042121 | Scatter-Gather Intelligent Memory Architecture For Unstructured Streaming Data On Multiprocessor Systems - A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion. | 02-16-2012 |
| 20120137074 | METHOD AND APPARATUS FOR STREAM BUFFER MANAGEMENT INSTRUCTIONS - A method and system to perform stream buffer management instructions in a processor. The stream buffer management instructions facilitate the creation and usage of a dedicated memory space or stream buffer of the processor in one embodiment of the invention. The dedicated memory space is a contiguous memory space and has a sequential or linear addressing scheme in one embodiment of the invention. The processor has logic to execute a stream buffer management instruction to copy data from a source memory address to a destination memory address that is specified with a desired level of memory hierarchy. | 05-31-2012 |
| 20120159130 | MECHANISM FOR CONFLICT DETECTION USING SIMD - A system and method are configured to detect conflicts when converting scalar processes to parallel processes (“SIMDifying”). Conflicts may be detected for an unordered single index, an ordered single index and/or ordered pairs of indices. Conflicts may be further detected for read-after-write dependencies. Conflict detection is configured to identify operations (i.e., iterations) in a sequence of iterations that may not be done in parallel. | 06-21-2012 |
| 20120290799 | GATHER AND SCATTER OPERATIONS IN MULTI-LEVEL MEMORY HIERARCHY - Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed. | 11-15-2012 |
| 20130179633 | SCATTER-GATHER INTELLIGENT MEMORY ARCHITECTURE FOR UNSTRUCTURED STREAMING DATA ON MULTIPROCESSOR SYSTEMS - A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion. | 07-11-2013 |
| 20130297878 | GATHER AND SCATTER OPERATIONS IN MULTI-LEVEL MEMORY HIERARCHY - Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed. | 11-07-2013 |
| 20130311530 | APPARATUS AND METHOD FOR SELECTING ELEMENTS OF A VECTOR COMPUTATION - An apparatus and method are described for performing a vector reduction. For example, an apparatus according to one embodiment comprises: a reduction logic tree comprised of a set of N-1 reduction logic blocks used to perform reduction in a single operation cycle for N vector elements; a first input vector register storing a first input vector communicatively coupled to the set of reduction logic blocks; a second input vector register storing a second input vector communicatively coupled to the set of reduction logic blocks; a mask register storing a mask value controlling a set of one or more multiplexers, each of the set of multiplexers selecting a value directly from the first input vector register or an output containing a processed value from one of the reduction logic blocks; and an output vector register coupled to outputs of the one or more multiplexers to receive values output passed through by each of the multiplexers responsive to the control signals. | 11-21-2013 |
| 20130332701 | APPARATUS AND METHOD FOR SELECTING ELEMENTS OF A VECTOR COMPUTATION - An apparatus and method are described for selecting elements to be used in a vector computation. For example, a method according to one embodiment includes the following operations: specifying whether to identify the first, last or next after last active element of an input mask register using an immediate value; identifying the first, last or next after last active element in the input mask register according to the immediate value; reading a value from an input vector register corresponding to the identified first, last or next after last active element in the input mask register; and writing the value to an output vector register. | 12-12-2013 |
| 20140040542 | SCATTER-GATHER INTELLIGENT MEMORY ARCHITECTURE FOR UNSTRUCTURED STREAMING DATA ON MULTIPROCESSOR SYSTEMS - A scatter/gather technique optimizes unstructured streaming memory accesses, providing off-chip bandwidth efficiency by accessing only useful data at a fine granularity, and off-loading memory access overhead by supporting address calculation, data shuffling, and format conversion. | 02-06-2014 |
| 20140068226 | VECTOR INSTRUCTIONS TO ENABLE EFFICIENT SYNCHRONIZATION AND PARALLEL REDUCTION OPERATIONS - In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed. | 03-06-2014 |
| 20140089634 | APPARATUS AND METHOD FOR DETECTING IDENTICAL ELEMENTS WITHIN A VECTOR REGISTER - An apparatus, system and method are described for identifying identical elements in a vector register. For example, a computer implemented method according to one embodiment comprises the operations of: reading each active element from a first vector register, each active element having a defined bit position within the first vector register; reading each element from a second vector register, each element having a defined bit position within the second vector register corresponding to a bit position of a current active element in the first vector register; reading an input mask register, the input mask register identifying active bit positions in the second vector register for which comparisons are to be made with values in the first vector register, the comparison operations comprising: comparing each active element in the second vector register with elements in the first vector register having bit positions preceding the bit position of the current active element in the second vector register; and setting a bit position in an output mask register equal to a true value if all of the preceding bit positions in the first vector register are equal to the bit in the current active bit position in the second vector register. | 03-27-2014 |
| 20140096119 | LOOP VECTORIZATION METHODS AND APPARATUS - Loop vectorization methods and apparatus are disclosed. An example method includes setting a dynamic adjustment value of a vectorization loop; executing the vectorization loop to vectorize a loop by grouping iterations of the loop into one or more vectors; identifying a dependency between iterations of the loop as; and setting the dynamic adjustment value based on the identified dependency. | 04-03-2014 |
| 20140149718 | INSTRUCTION AND LOGIC TO PROVIDE PUSHING BUFFER COPY AND STORE FUNCTIONALITY - Instructions and logic provide pushing buffer copy and store functionality. Some embodiments include a first hardware thread or processing core, and a second hardware thread or processing core, a cache to store cache coherent data in a cache line for a shared memory address accessible by the second hardware thread or processing core. Responsive to decoding an instruction specifying a source data operand, said shared memory address as a destination operand, and one or more owner of said shared memory address, one or more execution units copy data from the source data operand to the cache coherent data in the cache line for said shared memory address accessible by said second hardware thread or processing core in the cache when said one or more owner includes said second hardware thread or processing core. | 05-29-2014 |
| 20140181580 | SPECULATIVE NON-FAULTING LOADS AND GATHERS - According to one embodiment, a processor includes an instruction decoder to decode an instruction to read a plurality of data elements from memory, the instruction having a first operand specifying a storage location, a second operand specifying a bitmask having one or more bits, each bit corresponding to one of the data elements, and a third operand specifying a memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the instruction, to read one or more data elements speculatively, based on the bitmask specified by the second operand, from a memory location based on the memory address indicated by the third operand, and to store the one or more data elements in the storage location indicated by the first operand. | 06-26-2014 |
| 20140189247 | APPARATUS AND METHOD FOR IMPLEMENTING A SCRATCHPAD MEMORY - An apparatus and method for implementing a scratchpad memory within a cache using priority hints. For example, a method according to one embodiment comprises: providing a priority hint for a scratchpad memory implemented using a portion of a cache; determining a page replacement priority based on the priority hint; storing the page replacement priority in a page table entry (PTE) associated with the page; and using the page replacement priority to determine whether to evict one or more cache lines associated with the scratchpad memory from the cache. | 07-03-2014 |
| 20140189288 | INSTRUCTION TO REDUCE ELEMENTS IN A VECTOR REGISTER WITH STRIDED ACCESS PATTERN - A vector reduction instruction with non-unit strided access pattern is received and executed by the execution circuitry of a processor. In response to the instruction, the execution circuitry performs an associative reduction operation on data elements of a first vector register. Based on values of the mask register and a current element position being processed, the execution circuitry sequentially set one or more data elements of the first vector register to a result, which is generated by the associative reduction operation applied to both a previous data element of the first vector register and a data clement of a third vector register. The previous data element is located more than one element position away from the current element position. | 07-03-2014 |
| 20140189323 | APPARATUS AND METHOD FOR PROPAGATING CONDITIONALLY EVALUATED VALUES IN SIMD/VECTOR EXECUTION - An apparatus and method for propagating conditionally evaluated values. For example, a method according to one embodiment comprises: reading each value contained in an input mask register, each value being a true value or a false value and having a bit position associated therewith; for each true value read from the input mask register, generating a first result containing the bit position of the true value; for each false value read from the input mask register following the first true value, adding the vector length of the input mask register to a bit position of the last true value read from the input mask register to generate a second result; and storing each of the first results and second results in bit positions of an output register corresponding to the bit positions read from the input mask register. | 07-03-2014 |
| 20140223139 | SYSTEMS, APPARATUSES, AND METHODS FOR SETTING AN OUTPUT MASK IN A DESTINATION WRITEMASK REGISTER FROM A SOURCE WRITE MASK REGISTER USING AN INPUT WRITEMASK AND IMMEDIATE - Embodiments of systems, apparatuses, and methods for performing in a computer processor generation of a predicate mask based on vector comparison in response to a single instruction are described. | 08-07-2014 |
| 20140304477 | OBJECT LIVENESS TRACKING FOR USE IN PROCESSING DEVICE CACHE - A processing device comprises a processing device cache and a cache controller. The cache controller initiates a cache line eviction process and determines determine an object liveness value associated with a cache line in the processing device cache. The cache controller applies the object liveness value to a cache line eviction policy and evicts the cache line from the processing device cache based on the object liveness value and the cache line eviction policy. | 10-09-2014 |
| 20140337580 | GATHER AND SCATTER OPERATIONS IN MULTI-LEVEL MEMORY HIERARCHY - Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed. | 11-13-2014 |
| 20140379998 | DYNAMIC HOME TILE MAPPING - Technologies for dynamic home tile mapping are described. an address request can be received from a processing core, the processing core being associated with a home tile table, the home tile table including respective mappings of one or more directory addresses to one or more home tiles. A buffer can be scanned to identify a presence of the address within the buffer. Based on an identification of the presence of the address within the buffer, a home tile identifier corresponding to the address can be provided from the buffer. | 12-25-2014 |
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| 20120249842 | CMOS IMAGE SENSOR WITH BUILT IN CORRECTION FOR COLUMN FAILURE - A system for correcting a column line failure in an imager includes a pixel selection circuit configured to receive three adjacent pixel output signals, P(n−1), P(n) and P(n+1), respectively, from three adjacent column lines, (n−1) | 10-04-2012 |
| 20120280113 | CORRELATED DOUBLE SAMPLING - Apparatus and a method for correlated double sampling using an up-counter for parallel image sensors. All bits of a counter are set to one. An offset signal is compared to a first reference signal to define a first period during which the counter is incremented. After the first period, all bits of the counter are inverted. A sensor signal is compared to a second reference signal to define a second period during which the counter is incremented to generate a correlated double sampling value. | 11-08-2012 |
| 20120287316 | RAMP AND SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERSION METHODS, SYSTEMS AND APPARATUS - Successive approximation register (SAR) and ramp analog to digital conversion (ADC) methods, systems, and apparatus are disclosed. An analog voltage signal may be converted into a multiple bit digital value by generating bits of the multiple bit digital value by performing a SAR conversion on the analog voltage signal, where the bits corresponding to a SAR voltage level, and generating other bits of the multiple bit digital value by performing one or more ramp conversions on the analog voltage signal, the ramp conversion comparing the analog voltage signal to a ramp of voltage levels based on the SAR voltage level. The SAR and ramp ADC can provide multi-sampling using one SAR conversion and multiple ramp conversions. The SAR can set the voltage level of a first ramp of a multiple ramp conversion, which can then be used to preset the voltage level prior to subsequent ramps. | 11-15-2012 |
| 20130026384 | TIME-OF-FLIGHT IMAGING SYSTEMS - Electronic devices may include time-of-flight image pixels. A time-of-flight image pixel may include first and second charge storage regions coupled to a photosensor and a transfer transistor with a gate terminal coupled to the first storage region. An electronic device may further include a light pulse emitter configured to emit pulses of light to be reflected by objects in a scene. Reflected portions of the emitted pulses of light may be captured along with background light by the time-of-flight image pixels. Time-of-flight image pixels may be configured sense the time-of-flight of the reflected portions of the emitted pulses. The electronic device may include processing circuitry configured to use the sensed time-of-flight of the reflected portions to generate depth images of a scene. Depth images may include depth-image pixel values that contain information corresponding to the distance of the objects in the scene from the electronic device. | 01-31-2013 |
| 20130027575 | METHOD AND APPARATUS FOR ARRAY CAMERA PIXEL READOUT - Imaging systems may include camera modules that include an array of image sensors. An image sensor may include multiple image pixel arrays arranged in rows and columns, multiple control circuits for operating the image pixels of that image sensor, and shared readout circuitry for reading out the image pixels of the image pixel arrays of that image sensor. Each control circuit may be operable to select rows of image pixels that extend across a row of image pixel arrays. Shared readout circuitry may include one or more line buffers configured to temporarily store image data captured by image pixels in the selected rows of image pixels. Shared readout circuitry may include selection circuitry configured to readout image data from groups of associated pixels located in separate image pixel arrays. An imaging system may include processing circuitry for processing the image data from each group of pixels. | 01-31-2013 |
| 20140078364 | IMAGE SENSORS WITH COLUMN FAILURE CORRECTION CIRCUITRY - Electronic devices may include image sensors having image pixel arrays with image pixels arranged in pixel rows and pixel columns. Each pixel column may be coupled to column readout circuitry through column randomizing circuitry. The column readout circuitry may include a column circuit associated with each pixel column and at least one reserve column circuit. The column randomizing circuitry may randomize the distribution of image signals from the pixel columns to the column readout circuitry. The column randomizing circuitry may distribute the randomized image signals from at least one of the pixel columns to a reserve column circuit when any of the column circuits associated with the pixel columns has failed. The column randomizing circuitry may include an output column line for each column circuit and first and second transistors coupled in parallel to each output column line. | 03-20-2014 |
| 20140078365 | COLUMN-BASED HIGH DYNAMIC RANGE IMAGING SYSTEMS - Electronic devices may have camera modules that include an image sensor and processing circuitry. An image sensor may include a pixel array having pixel rows and pixel columns. The image pixels in a pixel row may include long-integration pixels and short-integration pixels. Row control signal lines for each pixel row may include a row-select control line, a reset control line, and two transfer control lines or may include a row-select control line, two reset control lines, and a transfer control line. Row control circuitry may be used to operate the pixel array to capture a column-interleaved image with short-exposure pixel values and long-exposure pixel values interleaved in a column-based pattern. The column-interleaved image may be used to form an interpolated short-exposure image and an interpolated long-exposure image from which a column-based interleaved high-dynamic-range image is generated. | 03-20-2014 |
| 20140263957 | IMAGING SYSTEMS WITH SWITCHABLE COLUMN POWER CONTROL - Electronic devices may include image sensors having image pixel arrays with image pixels arranged in pixel rows and pixel columns. Each pixel column may be coupled to a column line having column readout circuitry and column power control circuitry that selectively enables or disables the column readout circuitry for various column lines. The column power control circuitry and the column readout circuitry may be coupled to column decoder circuitry. The column decoder circuitry may provide a column address signals to the power control and the readout circuitry. The power control circuitry may enable only column lines for which column addresses have been received. | 09-18-2014 |
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| 20090072912 | OSCILLATOR SIGNAL GENERATION WITH SPUR MITIGATION IN A WIRELESS COMMUNICATION DEVICE - Techniques for generating oscillator signals in a wireless communication device are described. A phase-locked loop (PLL) may be used to generate an oscillator signal for a selected frequency channel. Different PLL settings may be used for the blocks in the PLL for different frequency channels. The different PLL settings may be for different PLL loop bandwidths, different amounts of charge pump current, different frequency equations associated with different sets of high and low divider ratios, different frequency division schemes associated with different prescaler ratios and/or different integer divider ratios, high side or low side injection for a super-heterodyne receiver or transmitter, and/or different supply voltages for one or more circuit blocks such as an oscillator. A suitable set of PLL settings may be selected for each frequency channel such that adverse impact due to spurs can be mitigated. | 03-19-2009 |
| 20100109751 | HIGH-PERFORMANCE ANALOG SWITCH - Techniques for designing a high performance analog switch for use in electronic circuit applications. In one aspect, a variable bulk voltage generation module is provided to vary the bulk voltage of a transistor in the switch, such that the threshold voltage of the transistor is reduced during the on state. In another aspect, a pulling transistor is provided to pull a middle node of the switch to a DC voltage during the off state to further increase the isolation provided by the switch. | 05-06-2010 |
| 20100295622 | SYSTEMS AND METHODS FOR SELF TESTING A VOLTAGE CONTROLLED OSCILLATOR IN AN OPEN LOOP CONFIGURATION - Methods and apparatus for self testing a multiband voltage controlled oscillator (VCO) are disclosed. A tuning voltage of the VCO is adjusted where the output of the VCO does not affect the input to the VCO. Frequency bands in the VCO are selected. Output frequencies of the VCO are measured. | 11-25-2010 |
| 20120326792 | SYSTEMATIC INTERMODULATION DISTORTION CALIBRATION FOR A DIFFERENTIAL LNA - Systematic IM2 calibration for a differential LNA is disclosed. In an aspect, an apparatus includes an amplifier configured to output an amplified signal having a level of systematic pre-mixer IM2 distortion, a detector configured to detect the level of the systematic pre-mixer IM2 distortion in the amplified signal, and a bias signal generator configured to generate at least one bias signal configured to adjust the amplifier to reduce the level of the systematic pre-mixer IM2 distortion. | 12-27-2012 |
| 20130106553 | SINGLE DIFFERENTIAL TRANSFORMER CORE | 05-02-2013 |
| 20130281042 | RECONFIGURABLE LNA FOR INCREASED JAMMER REJECTION - A reconfigurable LNA for increased jammer rejection is disclosed. An exemplary embodiment includes an LNA having a tunable resonant frequency, and a detector configured to output a control signal to tune the resonant frequency of the LNA to increase jammer suppression. An exemplary method includes detecting if a jammer is present, tuning a resonant frequency of an LNA away from the jammer to increase jammer rejection if the jammer is present, and tuning the resonant frequency of the LNA to a selected operating frequency if the jammer is not present. | 10-24-2013 |
| 20140256278 | SIMULTANEOUS SIGNAL RECEPTION WITH INTERSPERSED FREQUENCY ALLOCATION - Methods and circuits can down convert at least a first RF signal on a first path in a first frequency band to provide a first IF signal. A second RF signal on second path in a second frequency band can be down converted to provide a second IF signal. The first IF signal and the second IF signal are interspersed in the frequency domain, and the first frequency band is different from the second frequency band. A combiner can combine at least part of the first IF signal and the second IF signal to provide a combined signal on an output signal path for reception by a digital processing circuit. The first IF signal or second IF signal can be a Zero IF (ZIF), very low IF (VLIF), or Low IF (LIF) signal. | 09-11-2014 |
| 20140266886 | CONCURRENT MULTI-SYSTEM SATELLITE NAVIGATION RECEIVER WITH REAL SIGNALING OUTPUT - A global navigation satellite system (GNSS) receiver includes at least one GNSS antenna configured to receive input signaling from at least a first GNSS source and a second GNSS source; an in-phase/quadrature (I/Q) mixer coupled to the at least one GNSS antenna and configured to process the input signaling to obtain complex intermediate signaling; a first complex filter coupled to the I/Q mixer and configured to filter the complex intermediate signaling with respect to a first frequency range to obtain first real output signaling; a second complex filter coupled to the I/Q mixer and configured to filter the complex intermediate signaling with respect to a second frequency range to obtain second real output signaling; and a signal combiner coupled to the first and second complex filters and configured to generate combined real output signaling by combining the first real output signaling and the second real output signaling. | 09-18-2014 |
| 20140269853 | REUSING A SINGLE-CHIP CARRIER AGGREGATION RECEIVER TO SUPPORT NON-CELLULAR DIVERSITY - A wireless communication device configured for receiving multiple signals is described. The wireless communication device includes a single-chip carrier aggregation receiver architecture. The single-chip carrier aggregation receiver architecture includes a first antenna, a second antenna, a third antenna, a fourth antenna and a transceiver chip. The transceiver chip includes multiple carrier aggregation receivers. The single-chip carrier aggregation receiver architecture reuses at least one of the carrier aggregation receivers for secondary diversity. | 09-18-2014 |
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| 20100087848 | Loop Structures For Supporting Diagnostic and/or Therapeutic Elements in Contact With Tissue - An apparatus which includes a dual loop structure that carries a plurality of operative elements. A guide with a distal indentation that may be used to reorient a dual loop structure. | 04-08-2010 |
| 20100331658 | MAP AND ABLATE OPEN IRRIGATED HYBRID CATHETER - An embodiment of an open-irrigated catheter system comprises a tip section, a distal insert, and mapping electrodes. The tip section has an exterior wall that defines an open interior region within the tip section. The exterior wall includes mapping electrode openings and irrigation ports. The exterior wall is conductive for delivering radio frequency (RF) energy for an RF ablation procedure. The irrigation ports are in fluid communication with the open interior region to allow fluid to flow from the open interior region through the irrigation ports. The distal insert is positioned within the tip section to separate the open region into a distal fluid reservoir and a proximal fluid reservoir. The mapping electrodes are positioned in the mapping electrode openings in the tip section. | 12-30-2010 |
| 20110028826 | MAPPING PROBE ASSEMBLY WITH SKIVED TUBE BODY FRAME - An embodiment of a mapping probe assembly includes a body frame with a lumen therein. The body frame includes a catheter shaft region, a loop section and a transition region between the catheter shaft region and a loop section. A plurality of mapping electrodes are attached around the loop section. Electrical conductors extend through the lumen of the body frame to the mapping electrodes. In some embodiments, the loop section is skived, where a portion of the body frame is removed toward the interior of the loop section. The loop section has a generally planar loop, and further has a loop center. In some embodiments, the catheter shaft has an alignment generally perpendicular to the loop section where the alignment of the catheter shaft is along a line that intersects the planar loop proximate to the loop center. | 02-03-2011 |
| 20110040167 | SYSTEMS AND METHODS FOR MAKING AND USING MEDICAL ABLATION SYSTEMS AND HAVING MAPPING CATHETERS WITH IMPROVED ANCHORING ABILITY - A mapping catheter includes an elongated body for inserting into patient vasculature. A distal end of the elongated body includes a distal portion that includes a plurality of electrodes, a proximal portion disposed proximal to the distal portion, and a reduced-dimension portion disposed between the proximal and distal portions. The distal end is formed, at least in part, from a memory shape material that bends into a preformed shape upon release from a confined space. The preformed shape includes a first loop formed, at least in part, by the distal portion. The first loop is transverse to a longitudinal axis of the proximal portion. The reduced-dimension portion is configured and arranged to bend such that the reduced-dimension section advances distally through the first loop when the first loop is held in a fixed position and a force is applied distally along the longitudinal axis of the proximal portion. | 02-17-2011 |
| 20110224667 | ABLATION CATHETER WITH ISOLATED TEMPERATURE SENSING TIP - Disclosed herein, among other things, are methods and apparatus related to radio frequency (RF) ablation catheters. The present subject matter provides an ablation catheter system including a catheter body with a distal tip, and a thermocouple component at the distal tip. The thermocouple component is adapted to sense temperature of bodily fluid and/or tissue. The system includes a non-conductive insert configured to physically separate and thermally insulate the thermocouple component from the catheter body. Various embodiments include an open-irrigated ablation catheter system, the system further including at least one fluid chamber and a plurality of irrigation ports within the catheter body, where the plurality of irrigation ports enable fluid to exit from the at least one fluid chamber. The non-conductive insert is further configured to physically separate and thermally insulate the thermocouple component from the plurality of fluid flow channels and irrigation ports. | 09-15-2011 |
| 20120130363 | INVERTED BALLOON RF ABLATION CATHETER AND METHOD - Disclosed herein, among other things, are methods and apparatus related to radio frequency (RF) ablation catheters. The present subject matter provides a method for forming an ablation catheter having a balloon at a distal end of the catheter. The method includes applying a band of conductive material to an outer surface of the balloon. The band of conductive material is adapted to provide one or more electrodes for radio frequency ablation therapy. A distal end of a lead is connected to the band of conductive material. The balloon is inverted, so that the inverted balloon includes the band of conductive material on an inside surface. According to various embodiments, the balloon includes a semi-permeable or hydro-able membrane. | 05-24-2012 |
| 20120227457 | Corewire Design and Construction for Medical Devices - A guidewire for use in ear, nose and throat procedures may include an elongate core wire having a proximal region and a distal region. The distal region of the core wire may include a flattened portion adapted to provide preferential flexure along at least one axis of the wire. The distal region of the core wire may include a tip portion distal of the flattened portion, where at least one cross-sectional dimension of the tip portion is greater than at least one cross-sectional dimension of the flattened portion. The guidewire may include an outer coil disposed around at least a portion of the elongate core wire. The guidewire may also include an atraumatic tip coupled to the core wire or the outer coil. | 09-13-2012 |
| 20130165759 | SYSTEMS AND METHODS FOR MAKING AND USING MEDICAL ABLATION SYSTEMS HAVING MAPPING CATHETERS WITH IMPROVED ANCHORING ABILITY - A mapping catheter includes an elongated body for inserting into patient vasculature. A distal end of the elongated body includes a distal portion that includes a plurality of electrodes, a proximal portion disposed proximal to the distal portion, and a reduced-dimension portion disposed between the proximal and distal portions. The distal end is formed, at least in part, from a memory shape material that bends into a preformed shape upon release from a confined space. The preformed shape includes a first loop formed, at least in part, by the distal portion. The first loop is transverse to a longitudinal axis of the proximal portion. The reduced-dimension portion is configured and arranged to bend such that the reduced-dimension section advances distally through the first loop when the first loop is held in a fixed position and a force is applied distally along the longitudinal axis of the proximal portion. | 06-27-2013 |
| 20140257261 | SYSTEMS AND METHODS FOR MAKING AND USING MEDICAL ABLATION SYSTEMS HAVING MAPPING CATHETERS WITH IMPROVED ANCHORING ABILITY - A mapping catheter includes an elongated body for inserting into patient vasculature. A distal end of the elongated body includes a distal portion that includes a plurality of electrodes, a proximal portion disposed proximal to the distal portion, and a reduced-dimension portion disposed between the proximal and distal portions. The distal end is formed, at least in part, from a memory shape material that bends into a preformed shape upon release from a confined space. The preformed shape includes a first loop formed, at least in part, by the distal portion. The first loop is transverse to a longitudinal axis of the proximal portion. The reduced-dimension portion is configured and arranged to bend such that the reduced-dimension section advances distally through the first loop when the first loop is held in a fixed position and a force is applied distally along the longitudinal axis of the proximal portion. | 09-11-2014 |
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| 20080230511 | HALOGEN-FREE AMORPHOUS CARBON MASK ETCH HAVING HIGH SELECTIVITY TO PHOTORESIST - In one embodiment of the present invention, a halogen-free plasma etch processes is used to define a feature in a multi-layered masking stack including an amorphous carbon layer. In a particular embodiment, oxygen (O | 09-25-2008 |
| 20080286979 | Method of controlling sidewall profile by using intermittent, periodic introduction of cleaning species into the main plasma etching species - A method of removing a silicon-containing hard polymeric material from an opening leading to a recessed feature during the plasma etching of said recessed feature into a carbon-containing layer in a semiconductor substrate. The method comprises the intermittent use of a cleaning step within a continuous etching process, where at least one fluorine-containing cleaning agent species is added to already present etchant species of said continuous etching process for a limited time period, wherein the length of time of each cleaning step ranges from about 5% to about 100% of the time length of an etch step which either precedes or follows said cleaning step. | 11-20-2008 |
| 20100101729 | PROCESS KIT HAVING REDUCED EROSION SENSITIVITY - Process kits for use in a semiconductor process chambers have been provided herein. In some embodiments, a process kit for a semiconductor process chamber includes a body configured to rest about a periphery of a substrate support and having sidewalls defining an opening corresponding to a central region of the substrate support. A lip extends from the sidewalls of the body into the opening, wherein a portion of an upper surface of the lip is configured to be disposed beneath a substrate during processing. A first distance measured between opposing sidewalls of the body is greater than a width across the upper surface of a substrate to be disposed within the opening by at least about 7.87 mm. | 04-29-2010 |
| 20130029484 | MAINTAINING MASK INTEGRITY TO FORM OPENINGS IN WAFERS - One or more openings in an organic mask layer deposited on a first insulating layer over a substrate are formed. One or more openings in the first insulating layer are formed through the openings in the organic mask using a first iodine containing gas. An antireflective layer can be deposited on the organic mask layer. One or more openings in the antireflective layer are formed down to the organic mask layer using a second iodine containing gas. The first insulating layer can be deposited on a second insulating layer over the substrate. One or more openings in the second insulating layer can be formed using a third iodine containing gas. | 01-31-2013 |
| 20130109188 | PLASMA ETCH PROCESSES FOR BORON-DOPED CARBONACEOUS MASK LAYERS | 05-02-2013 |
| 20130122707 | METHODS OF POLYMERS DEPOSITION FOR FORMING REDUCED CRITICAL DIMENSIONS - Methods of polymer deposition for forming reduced critical dimensions are described. In one embodiment, a substrate is provided into a chamber, the substrate having a patterned layer disposed on an underlying layer formed thereon. The patterned layer includes a plurality of openings, each opening having a sidewall, a bottom, and a critical dimension. A gas mixture is provided into the chamber, the gas mixture having an etching gas and a polymer control gas. The polymer control gas includes a polymerizing fluorocarbon C | 05-16-2013 |
| 20130122712 | METHOD OF ETCHING HIGH ASPECT RATIO FEATURES IN A DIELECTRIC LAYER - Methods of etching HAR features in a dielectric layer are described. In one embodiment, a substrate is provided into an etch chamber. The substrate has a patterned mask disposed on a dielectric layer formed thereon where the patterned mask has openings. A gas mixture is provided into the etch chamber, the gas mixture includes CO, O | 05-16-2013 |
| 20130224960 | METHODS FOR ETCHING OXIDE LAYERS USING PROCESS GAS PULSING - Methods for etching an oxide layer disposed on a substrate through a patterned layer defining one or more features to be etched into the oxide layer are provided herein. In some embodiments, a method for etching an oxide layer disposed on a substrate through a patterned layer defining one or more features to be etched into the oxide layer may include: etching the oxide layer through the patterned layer using a process gas comprising a polymer forming gas and an oxygen containing gas to form the one or more features in the oxide layer; and pulsing at least one of the polymer forming gas or the oxygen containing gas for at least a portion of etching the oxide layer to control a dimension of the one or more features. | 08-29-2013 |
| 20140065824 | MAINTAINING MASK INTEGRITY TO FORM OPENINGS IN WAFERS - One or more openings in an organic mask layer deposited on a first insulating layer over a substrate are formed. One or more openings in the first insulating layer are formed through the openings in the organic mask using a first iodine containing gas. An antireflective layer can be deposited on the organic mask layer. One or more openings in the antireflective layer are formed down to the organic mask layer using a second iodine containing gas. The first insulating layer can be deposited on a second insulating layer over the substrate. One or more openings in the second insulating layer can be formed using a third iodine containing gas. | 03-06-2014 |
| 20140213059 | BORON-DOPED CARBON-BASED HARDMASK ETCH PROCESSING - Boron-doped carbon-based hardmask etch processing is described. In an example, a method of patterning a film includes etching a boron-doped amorphous carbon layer with a plasma based on a combination of CH | 07-31-2014 |
| 20140213062 | SILICON DIOXIDE-POLYSILICON MULTI-LAYERED STACK ETCHING WITH PLASMA ETCH CHAMBER EMPLOYING NON-CORROSIVE ETCHANTS - Multilayered stacks having layers of silicon interleaved with layers of a dielectric, such as silicon dioxide, are plasma etched with non-corrosive process gas chemistries. Etching plasmas of fluorine source gases, such as SF | 07-31-2014 |
| 20140342570 | ETCH PROCESS HAVING ADAPTIVE CONTROL WITH ETCH DEPTH OF PRESSURE AND POWER - The disclosure concerns a plasma-enhanced etch process in which chamber pressure and/or RF power level is ramped throughout the etch process. | 11-20-2014 |
| 20150041061 | RECURSIVE PUMPING FOR SYMMETRICAL GAS EXHAUST TO CONTROL CRITICAL DIMENSION UNIFORMITY IN PLASMA REACTORS - Embodiments of the present invention provide apparatus and methods for reducing non-uniformity and/or skews during substrate processing. One embodiment of the present invention provides a flow equalizer assembly for disposing between a vacuum port and a processing volume in a processing chamber. The flow equalizing assembly includes a first plate having at least one first opening, and a second plate having two or more second openings. The first and second plates define a flow redistributing volume therebetween, and the at least one first opening and the two or more second openings are staggered. | 02-12-2015 |
| 20150072530 | METHODS FOR ETCHING MATERIALS USING SYNCHRONIZED RF PULSES - Embodiments of the present invention provide methods for etching a material layer using synchronized RF pulses. In one embodiment, a method includes providing a gas mixture into a processing chamber, applying a first RF source power at a first time point to the processing chamber to form a plasma in the gas mixture, applying a first RF bias power at a second time point to the processing chamber to perform an etching process on the substrate, turning off the first RF bias power at a third time point while continuously maintaining the first RF source power on from the first time point through the second and the third time points, and turning off the first RF source power at a fourth time point while continuously providing the gas mixture to the processing chamber from the first time point through the second, third and fourth time points. | 03-12-2015 |
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| 20110012609 | METHOD AND APPARTUS FOR SUB-ASSEMBLY ERROR DETECTION IN HIGH VOLTAGE ANALOG CIRCUITS AND PINS - The innovation relates to systems and/or methodologies for error detection during sub-assembly in high voltage analog circuits. A signal driver communicates test signals to one or more high voltage analog circuits, and a state machine compares the electrical and/or thermal responses of the high voltage analog circuits to a set of predetermined expected results (e.g., signatures). The signal driver and state machine can be incorporated into the high voltage analog circuits. The expected results can be stored in the target circuits in the form of look-up tables, matrices, and so forth. Errors, such as, dry solders and bridge solders can be determined based on the comparison of the obtained responses to the expected signatures. | 01-20-2011 |
| 20120223648 | Adaptive Switch Mode LED System - A system that provides an intelligent approach to driving multiple strings of LEDs. A processing device determines an optimal current level for each LED string from a limited set of allowed currents. The processing device also determines a PWM duty cycle for driving the LEDs in each LED string to provide precise brightness control over the LED string. The settings for the current level and duty cycle are transmitted to an LED driver for regulating the current and on-off times of the LED strings. Beneficially, the system reduces the size of the LED driver while leveraging existing resources available in the processing device to operate the LEDs in a power efficient manner. | 09-06-2012 |
| 20120280622 | LIGHT EMITTING DIODE DRIVER - A driver circuit for driving light emitting diodes (LEDs). The driver circuit includes: a string of LEDs divided into n groups, the n groups of LEDs being electrically connected to each other in series, a downstream end of group m-1 being electrically connected to the upstream end of group m, where m is a positive number equal to or less than n. The driver circuit also includes a plurality of current regulating circuits, each of the current regulating circuits being coupled to the downstream end of a corresponding group at one end and coupled to the ground at the other end and including a sensor amplifier and a cascode having first and second transistors, each sensor amplifier being coupled to a different voltage source for providing a different reference voltage thereto. | 11-08-2012 |
| 20130147374 | HIGH PERFORMANCE ADAPTIVE SWITCHED LED DRIVER - An LED driver controls current through an LED string. The LED driver generates a boosted PWM signal to drive a PWM transistor in the LED current path such that the PWM transistor maintains a substantially constant V | 06-13-2013 |
| 20140210365 | HIGH PERFORMANCE ADAPTIVE SWITCHED LED DRIVER - An LED driver controls current through an LED string. The LED driver generates a boosted PWM signal to drive a PWM transistor in the LED current path such that the PWM transistor maintains a substantially constant V | 07-31-2014 |
| 20140232278 | LIGHT EMITTING DIODE DRIVER - A driver circuit for driving light emitting diodes (LEDs). The driver circuit includes: a string of LEDs divided into n groups, the n groups of LEDs being electrically connected to each other in series, a downstream end of group m−1 being electrically connected to the upstream end of group m, where m is a positive number equal to or less than n. The driver circuit also includes a plurality of current regulating circuits, each of the current regulating circuits being coupled to the downstream end of a corresponding group at one end and coupled to the ground at the other end and including a sensor amplifier and a cascode having first and second transistors, each sensor amplifier being coupled to a different voltage source for providing a different reference voltage thereto. | 08-21-2014 |
| 20140252968 | LIGHT EMITTING DIODE DRIVER - A driver circuit for driving light emitting diodes (LEDs). The driver circuit includes: a string of LEDs divided into n groups, the n groups of LEDs being electrically connected to each other in series, a downstream end of group m-1 being electrically connected to the upstream end of group m, where m is a positive number equal to or less than n. The driver circuit also includes a plurality of current regulating circuits, each of the current regulating circuits being coupled to the downstream end of a corresponding group at one end and coupled to the ground at the other end and including a sensor amplifier and a cascode having first and second transistors, each sensor amplifier being coupled to a different voltage source for providing a different reference voltage thereto. | 09-11-2014 |
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| 20110284986 | BYPASS DIODE FOR A SOLAR CELL - Bypass diodes for solar cells are described. In one embodiment, a bypass diode for a solar cell includes a substrate of the solar cell. A first conductive region is disposed above the substrate, the first conductive region of a first conductivity type. A second conductive region is disposed on the first conductive region, the second conductive region of a second conductivity type opposite the first conductivity type. | 11-24-2011 |
| 20110300665 | Ablation Of Film Stacks In Solar Cell Fabrication Processes - A dielectric film stack of a solar cell is ablated using a laser. The dielectric film stack includes a layer that is absorptive in a wavelength of operation of the laser source. The laser source, which fires laser pulses at a pulse repetition rate, is configured to ablate the film stack to expose an underlying layer of material. The laser source may be configured to fire a burst of two laser pulses or a single temporally asymmetric laser pulse within a single pulse repetition to achieve complete ablation in a single step. | 12-08-2011 |
| 20120060904 | Fabrication Of Solar Cells With Silicon Nano-Particles - A solar cell structure includes silicon nano-particle diffusion regions. The diffusion regions may be formed by printing silicon nano-particles over a thin dielectric, such as silicon dioxide. A wetting agent may be formed on the thin dielectric prior to printing of the nano-particles. The nano-particles may be printed by inkjet printing. The nano-particles may be thermally processed in a first phase by heating the nano-particles to thermally drive out organic materials from the nano-particles, and in a second phase by heating the nano-particles to form a continuous nano-particle film over the thin dielectric. | 03-15-2012 |
| 20120171799 | BYPASS DIODE FOR A SOLAR CELL - Methods of fabricating bypass diodes for solar cells are described. In one embodiment, a method includes forming a first conductive region of a first conductivity type above a substrate of a solar cell. A second conductive region of a second conductivity type is formed on the first conductive region. In another embodiment, a method includes forming a first conductive region of a first conductivity type above a substrate of a solar cell. A second conductive region of a second conductivity type is formed within, and surrounded by, an uppermost portion of the first conductive region but is not formed in a lowermost portion of the first conductive region. | 07-05-2012 |
| 20120204926 | PROCESS AND STRUCTURES FOR FABRICATION OF SOLAR CELLS - Contact holes of solar cells are formed by laser ablation to accommodate various solar cell designs. Use of a laser to form the contact holes is facilitated by replacing films formed on the diffusion regions with a film that has substantially uniform thickness. Contact holes may be formed to deep diffusion regions to increase the laser ablation process margins. The laser configuration may be tailored to form contact holes through dielectric films of varying thicknesses. | 08-16-2012 |
| 20120247560 | Thin Silicon Solar Cell And Method Of Manufacture - A method of fabricating a solar cell is disclosed. The method includes the steps of forming a sacrificial layer on a silicon substrate, forming a doped silicon layer atop the sacrificial substrate, forming a silicon film atop the doped silicon layer, forming a plurality of interdigitated contacts on the silicon film, contacting each of the plurality of interdigitated contacts with a metal contact, and removing the sacrificial layer. | 10-04-2012 |
| 20140034128 | THIN SILICON SOLAR CELL AND METHOD OF MANUFACTURE - A method of fabricating a solar cell is disclosed. The method includes the steps of forming a sacrificial layer on a silicon substrate, forming a doped silicon layer atop the sacrificial substrate, forming a silicon film atop the doped silicon layer, forming a plurality of interdigitated contacts on the silicon film, contacting each of the plurality of interdigitated contacts with a metal contact, and removing the sacrificial layer. | 02-06-2014 |
| 20140096824 | PROCESS AND STRUCTURES FOR FABRICATION OF SOLAR CELLS - Contact holes of solar cells are formed by laser ablation to accommodate various solar cell designs. Use of a laser to form the contact holes is facilitated by replacing films formed on the diffusion regions with a film that has substantially uniform thickness. Contact holes may be formed to deep diffusion regions to increase the laser ablation process margins. The laser configuration may be tailored to form contact holes through dielectric films of varying thicknesses. | 04-10-2014 |
| 20140170800 | SOLAR CELL EMITTER REGION FABRICATION USING SILICON NANO-PARTICLES - Methods of fabricating solar cell emitter regions using silicon nano-particles and the resulting solar cells are described. In an example, a method of fabricating an emitter region of a solar cell includes forming a region of doped silicon nano-particles above a dielectric layer disposed above a surface of a substrate of the solar cell. A layer of silicon is formed on the region of doped silicon nano-particles. At least a portion of the layer of silicon is mixed with at least a portion of the region of doped silicon nano-particles to form a doped polycrystalline silicon layer disposed on the dielectric layer. | 06-19-2014 |
| 20140295609 | SOLAR CELL EMITTER REGION FABRICATION USING SILICON NANO-PARTICLES - Methods of fabricating solar cell emitter regions using silicon nano-particles and the resulting solar cells are described. In an example, a method of fabricating an emitter region of a solar cell includes forming a region of doped silicon nano-particles above a dielectric layer disposed above a surface of a substrate of the solar cell. A layer of silicon is formed on the region of doped silicon nano-particles. At least a portion of the layer of silicon is mixed with at least a portion of the region of doped silicon nano-particles to form a doped polycrystalline silicon layer disposed on the dielectric layer. | 10-02-2014 |
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| 20100283100 | SEMICONDUCTOR MEMORY COMPRISING DUAL CHARGE STORAGE NODES AND METHODS FOR ITS FABRICATION - A dual charge storage node memory device and methods for its fabrication are provided. In one embodiment a dielectric plug is formed comprising a first portion recessed into a semiconductor substrate and a second portion extending above the substrate. A layer of semiconductor material is formed overlying the second portion. A first layered structure is formed overlying a first side of the second portion of the dielectric plug, and a second layered structure is formed overlying a second side, each of the layered structures overlying the layer of semiconductor material and comprising a charge storage layer between first and second dielectric layers. Ions are implanted into the substrate to form a first bit line and second bit line, and a layer of conductive material is deposited and patterned to form a control gate overlying the dielectric plug and the first and second layered structures. | 11-11-2010 |
| 20110037115 | SYSTEM AND METHOD FOR IMPROVING MESA WIDTH IN A SEMICONDUCTOR DEVICE - A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench. | 02-17-2011 |
| 20140167128 | Memory Gate Landing Pad Made From Dummy Features - Embodiments described herein generally relate to landing gate pads for contacts and manufacturing methods therefor. A bridge is formed between two features to allow a contact to be disposed, at least partially, on the bridge. Landing the contact on the bridge avoids additional manufacturing steps to create a target for a contact. | 06-19-2014 |
| 20140167135 | Process Charging Protection for Split Gate Charge Trapping Flash - A semiconductor device and method of making such device is presented herein. The semiconductor device includes a plurality of memory cells, a plurality of p-n junctions, and a metal trace of a first metal layer. Each of the plurality of memory cells includes a first gate disposed over a first dielectric, a second gate disposed over a second dielectric and adjacent to a sidewall of the first gate, a first doped region in the substrate adjacent to the first gate, and a second doped region in the substrate adjacent to the second gate. The plurality of p-n junctions are electrically isolated from the doped regions of each memory cell. The metal trace extends along a single plane between a via to the second gate of at least one memory cell in the plurality of memory cells, and a via to a p-n junction within the plurality of p-n junctions. | 06-19-2014 |
| 20140167140 | Memory First Process Flow and Device - Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, a semiconductor device includes a memory gate disposed in a first region of the semiconductor device. The memory gate may include a first gate conductor layer disposed over a charge trapping dielectric. A select gate may be disposed in the first region of the semiconductor device adjacent to a sidewall of the memory gate. A sidewall dielectric may be disposed between the sidewall of the memory gate and the select gate. Additionally, the device may include a logic gate disposed in a second region of the semiconductor device that comprises the first gate conductor layer. | 06-19-2014 |
| 20140167141 | Charge Trapping Split Gate Embedded Flash Memory and Associated Methods - Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming an dielectric layer at a first region and at a second region of a semiconductor substrate. A gate conductor layer is disposed over the dielectric formed in the first and the second regions of the semiconductor substrate, and the second region is masked. A split gate memory cell is formed in the first region of the semiconductor substrate with a first gate length. The first region is then masked, and the second region is etched to define a logic gate that has a second gate length. The first and second gate lengths can be different. | 06-19-2014 |
| 20140167220 | THREE DIMENSIONAL CAPACITOR - Integrated capacitor structures and methods for fabricating same are provided. In an embodiment, the integrated capacitor structures exploit the capacitance that can be formed in a plane that is perpendicular to that of the substrate, resulting in three-dimensional capacitor structures. This allows for integrated capacitor structures with higher capacitance to be formed over relatively small substrate areas. Embodiments are suitable for use by charge pumps and can be fabricated to have more or less capacitance as desired by the application. | 06-19-2014 |
| 20140170843 | Charge Trapping Split Gate Device and Method of Fabricating Same - Embodiments provide a split gate device, methods for fabricating a split gate device, and integrated methods for fabricating a split gate device and a periphery device. In an embodiment, the split gate device is a charge trapping split gate device, which includes a charge trapping layer. In another embodiment, the split gate device is a non-volatile memory cell, which can be formed according to embodiments as standalone or embedded with a periphery device. | 06-19-2014 |
| 20140210012 | Manufacturing of FET Devices Having Lightly Doped Drain and Source Regions - Embodiments described herein generally relate to methods of manufacturing n-type lightly doped drains and p-type lightly doped drains. In one method, a photoresist mask is used to etch a transistor, and the mask is left in place (i.e., reused) to protect other devices and poly while a high energy implantation is performed in alignment with the photoresist mask, such that the implantation is adjacent to the etched transistor. One example of a high energy implantation is forming lightly doped source and drain regions. This technique of reusing a photoresist mask can be employed for creating lightly doped source and drain regions of one conductivity followed by using the technique a second time to create lightly doped source and drain regions of the complementary conductivity type. This may prevent use of at least one hard mask during manufacturing. | 07-31-2014 |
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| 20110124169 | METHODS OF SELECTIVELY DEPOSITING AN EPITAXIAL LAYER - Methods for selectively depositing an epitaxial layer are provided herein. In some embodiments, providing a substrate having a monocrystalline first surface and a non-monocrystalline second surface; exposing the substrate to a deposition gas to deposit a layer on the first and second surfaces, the layer comprising a first portion deposited on the first surfaces and a second portion deposited on the second surfaces; and exposing the substrate to an etching gas comprising a first gas comprising hydrogen and a halogen and a second gas comprising at least one of a Group III, IV, or V element to selectively etch the first portion of the layer at a slower rate than the second portion of the layer. In some embodiments, the etching gas comprises hydrogen chloride (HCl) and germane (GeH | 05-26-2011 |
| 20110209660 | METHODS AND APPARATUS FOR DEPOSITION PROCESSES - Methods and apparatus for deposition processes are provided herein. In some embodiments, an apparatus may include a substrate support comprising a susceptor plate having a pocket disposed in an upper surface of the susceptor plate and having a lip formed in the upper surface and circumscribing the pocket, the lip configured to support a substrate on the lip; and a plurality of vents extending from the pocket to the upper surface of the susceptor plate to exhaust gases trapped between the backside of the substrate and the pocket when a substrate is disposed on the lip. Methods of utilizing the inventive apparatus for depositing a layer on a substrate are also disclosed. | 09-01-2011 |
| 20110277934 | METHODS OF SELECTIVELY DEPOSITING AN EPITAXIAL LAYER - Apparatus for selectively depositing an epitaxial layer are provided herein. In some embodiments, an apparatus for processing a substrate may include a process chamber having a substrate support disposed therein; a deposition gas source coupled to the process chamber; an etching gas source coupled to the process chamber, the etching gas source including a hydrogen and halogen gas source and a germanium gas source; an energy control source to maintain the substrate at a temperature at up to 600 degrees Celsius; and an exhaust system coupled to the process chamber to control the pressure in the process chamber. | 11-17-2011 |
| 20120034761 | METHOD OF REMOVING CONTAMINANTS AND NATIVE OXIDES FROM A SUBSTRATE SURFACE - Embodiments of the present invention generally relate to methods for removing contaminants and native oxides from substrate surfaces. The methods generally include exposing a substrate having an oxide layer thereon to an oxidizing source. The oxidizing source oxidizes an upper portion of the substrate beneath the oxide layer to form an oxide layer having an increased thickness. The oxide layer with the increased thickness is then removed to expose a clean surface of the substrate. The removal of the oxide layer generally includes removal of contaminants present in and on the oxide layer, especially those contaminants present at the interface of the oxide layer and the substrate. An epitaxial layer may then be formed on the clean surface of the substrate. | 02-09-2012 |
| 20120193623 | CARBON ADDITION FOR LOW RESISTIVITY IN SITU DOPED SILICON EPITAXY - Embodiments of the present invention generally relate to methods of forming epitaxial layers and devices having epitaxial layers. The methods generally include forming a first epitaxial layer including phosphorus and carbon on a substrate, and then forming a second epitaxial layer including phosphorus and carbon on the first epitaxial layer. The second epitaxial layer has a lower phosphorus concentration than the first epitaxial layer, which allows for selective etching of the second epitaxial layer and undesired amorphous silicon or polysilicon deposited during the depositions. The substrate is then exposed to an etchant to remove the second epitaxial layer and undesired amorphous silicon or polysilicon. The carbon present in the first and second epitaxial layers reduces phosphorus diffusion, which allows for higher phosphorus doping concentrations. The increased phosphorus concentrations reduce the resistivity of the final device. The devices include epitaxial layers having a resistivity of less than about 0.381 milliohm-centimeters. | 08-02-2012 |
| 20120202338 | EPITAXY OF HIGH TENSILE SILICON ALLOY FOR TENSILE STRAIN APPLICATIONS - Embodiments of the present invention generally relate to methods for forming silicon epitaxial layers on semiconductor devices. The methods include forming a silicon epitaxial layer on a substrate at increased pressure and reduced temperature. The silicon epitaxial layer has a phosphorus concentration of about 1×10 | 08-09-2012 |
| 20120272898 | METHOD AND APPARATUS FOR GAS DELIVERY - Methods and apparatus for gas delivery are disclosed herein. In some embodiments, a gas delivery system includes an ampoule for storing a precursor in solid or liquid form, a first conduit coupled to the ampoule and having a first end coupled to a first gas source to draw a vapor of the precursor from the ampoule into the first conduit, a second conduit coupled to the first conduit at a first junction located downstream of the ampoule and having a first end coupled to a second gas source and a second end coupled to a process chamber, and a heat source configured to heat the ampoule and at least a first portion of the first conduit from the ampoule to the second conduit and to heat only a second portion of the second conduit, wherein the second portion of the second conduit includes the first junction. | 11-01-2012 |
| 20120273052 | METHOD AND APPARATUS FOR GAS DELIVERY - Methods and apparatus for gas delivery are disclosed herein. In some embodiments, a gas delivery system includes an ampoule for storing a precursor in solid or liquid form, a first conduit coupled to the ampoule and having a first end coupled to a first gas source to draw a vapor of the precursor from the ampoule into the first conduit, a second conduit coupled to the first conduit at a first junction located downstream of the ampoule and having a first end coupled to a second gas source and a second end coupled to a process chamber, and a heat source configured to heat the ampoule and at least a first portion of the first conduit from the ampoule to the second conduit and to heat only a second portion of the second conduit, wherein the second portion of the second conduit includes the first junction. | 11-01-2012 |
| 20130210221 | SELECTIVE EPITAXIAL GERMANIUM GROWTH ON SILICON-TRENCH FILL AND IN SITU DOPING - Methods and apparatus for forming a germanium containing film on a patterned substrate are described. The patterned substrate is a silicon, or silicon containing material, and may have a mask material formed on a surface thereof. The germanium containing material is formed selectively on exposed silicon in the recesses of the substrate, and an overburden of at least 50% is formed on the substrate. The germanium containing layer is thermally treated using pulsed laser radiation, which melts a portion of the overburden, but does not melt the germanium containing material in the recesses. The germanium containing material in the recesses is typically annealed, at least in part, by the thermal treatment. The overburden is then removed. | 08-15-2013 |
| 20130280891 | METHOD AND APPARATUS FOR GERMANIUM TIN ALLOY FORMATION BY THERMAL CVD - A method and apparatus for forming semiconductive semiconductor-metal alloy layers is described. A germanium precursor and a metal precursor are provided to a chamber, and an epitaxial layer of germanium-metal alloy, optionally including silicon, is formed on the substrate. The metal precursor is typically a metal halide, which may be provided by evaporating a liquid metal halide, subliming a solid metal halide, or by contacting a pure metal with a halogen gas. A group IV halide deposition control agent is used to provide selective deposition on semiconductive regions of the substrate relative to dielectric regions. The semiconductive semiconductor-metal alloy layers may be doped, for example with boron, phosphorus, and/or arsenic. The precursors may be provided through a showerhead or through a side entry point, and an exhaust system coupled to the chamber may be separately heated to manage condensation of exhaust components. | 10-24-2013 |
| 20130330911 | METHOD OF SEMICONDUCTOR FILM STABILIZATION - Embodiments of the invention generally relate to methods for forming silicon-germanium-tin alloy epitaxial layers, germanium-tin alloy epitaxial layers, and germanium epitaxial layers that may be doped with boron, phosphorus, arsenic, or other n-type or p-type dopants. The methods generally include positioning a substrate in a processing chamber. A germanium precursor gas is then introduced into the chamber concurrently with a stressor precursor gas, such as a tin precursor gas, to form an epitaxial layer. The flow of the germanium gas is then halted, and an etchant gas is introduced into the chamber. An etch back is then performed while in the presence of the stressor precursor gas used in the formation of the epitaxial film. The flow of the etchant gas is then stopped, and the cycle may then be repeated. In addition to or as an alternative to the etch back process, an annealing processing may be performed. | 12-12-2013 |
| 20140106547 | EPITAXY OF HIGH TENSILE SILICON ALLOY FOR TENSILE STRAIN APPLICATIONS - Embodiments of the present invention generally relate to methods for forming silicon epitaxial layers on semiconductor devices. The methods include forming a silicon epitaxial layer on a substrate at increased pressure and reduced temperature. The silicon epitaxial layer has a phosphorus concentration of about 1×10 | 04-17-2014 |
| 20150050800 | FIN FORMATION BY EPITAXIAL DEPOSITION - Methods of forming a fin structure for a field effect transistor are described. The methods may include the operations of patterning a mandrel on a surface of a substrate, and depositing an epitaxial layer of high-mobility channel material over exposed surfaces of the patterned mandrel. The epitaxial layer leaves a gap between adjacent columns of the patterned mandrel, and a dielectric material may be deposited in the gap between the adjacent columns of the patterned mandrel. The methods may also include planarizing the epitaxial layer to form a planarized epitaxial layer and exposing the columns of the patterned mandrel, and etching at least a portion of the exposed columns of the patterned mandrel and the dielectric material to expose at least a portion of the planarized epitaxial layer that forms the fin structure. | 02-19-2015 |
| 20150079803 | METHOD OF FORMING STRAIN-RELAXED BUFFER LAYERS - Implementations described herein generally relate to methods for relaxing strain in thin semiconductor films grown on another semiconductor substrate that has a different lattice constant. Strain relaxation typically involves forming a strain relaxed buffer layer on the semiconductor substrate for further growth of another semiconductor material on top. Whereas conventionally formed buffer layers are often thick, rough and/or defective, the strain relaxed buffer layers formed using the implementations described herein demonstrate improved surface morphology with minimal defects. | 03-19-2015 |
