Kim, Icheon
Ba Wool Kim, Icheon KR
Patent application number | Description | Published |
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20120001294 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first metal wiring which is formed over substructure; a first contact plug which is coupled to the first metal wiring and passes through a first interlayer insulating film provided over the substructure; a second metal wiring which is provided over the first interlayer insulating film and is coupled to the first contact plug; a second contact plug which is coupled to the second metal wiring and passes through a second interlayer insulating film which is provided over the first interlayer insulating film; and a fuse pattern and a data read fuse pattern which are coupled to the second contact plug and provided over the second interlayer insulating film. | 01-05-2012 |
Beom Yong Kim, Icheon KR
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20140097397 | RESISTIVE MEMORY DEVICE AND MEMORY APPARATUS AND DATA PROCESSING SYSTEM HAVING THE SAME - A resistive memory device includes a first electrode layer, a second electrode layer, and a first variable resistive layer and a second variable resistive layer stacked at least once between the first electrode layer and the second electrode layer. The first variable resistive material layer may include a metal nitride layer having a resistivity higher than that of the first electrode layer or the second electrode layer and less than or equal to that of an insulating material. | 04-10-2014 |
20140299830 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming an impurity layer over a first conductive layer; forming a first metal oxide layer over the impurity layer, wherein the first metal oxide layer includes oxygen at a lower ratio than a stoichiometric ratio; diffusing an impurity from the impurity layer into the first metal oxide layer to form a first doped metal oxide layer; forming a second metal oxide layer over the first doped metal oxide layer; and forming a second conductive layer over the second metal oxide layer. | 10-09-2014 |
20140301127 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME - A semiconductor device includes a first conductive layer, a second conductive layer spaced from the first conductive layer, a variable resistance layer interposed between the first and second conductive layers, and an impurity-doped layer provided over a side surface of the variable resistance layer. The variable resistance layer has a smaller width than the first and the second conductive layers. | 10-09-2014 |
20150138872 | ELECTRONIC DEVICE INCLUDING A MEMORY AND METHOD FOR FABRICATING THE SAME - An electronic device includes a semiconductor memory unit. The semiconductor memory unit includes first lines extending along a first direction; second lines extending along a second direction that intersects with the first direction; a silicon-added metal oxide layer disposed in each intersection region of the first lines and the second lines; a metal oxide layer that is disposed alternately with the silicon-added metal oxide layer in the first direction and that is disposed in a region between two adjacent second lines and over a corresponding one of the first lines over which the silicon-added metal oxide layer is disposed; and a silicon oxide layer that is disposed alternately with the silicon-added metal oxide layer in the second direction and that is disposed in a region between two first lines and under a corresponding one of the second lines under which the silicon-added metal oxide layer is disposed. | 05-21-2015 |
20150325789 | VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - Disclosed herein are a variable resistance memory device and a method of fabricating the same. The variable resistance memory device may include a first electrode; a second electrode; and a variable resistance layer configured to be interposed between the first electrode and the second electrode, wherein the variable resistance layer includes a Si-added metal oxide. | 11-12-2015 |
20150340608 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME - A semiconductor device includes a first conductive layer, a second conductive layer spaced from the first conductive layer, a variable resistance layer interposed between the first and second conductive layers, and an impurity-doped layer provided over a side surface of the variable resistance layer. The variable resistance layer has a smaller width than the first and the second conductive layers. | 11-26-2015 |
20160118442 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - Provided is an electronic device including a switching element, wherein the switching element may include a first electrode, a second electrode, a switching layer interposed between the first and second electrodes, and a first amorphous semiconductor layer interposed between the first electrode and the switching layer. | 04-28-2016 |
Doc Jin Kim, Icheon KR
Patent application number | Description | Published |
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20140332977 | SEMICONDUCTOR DEVICE - A semiconductor device includes a metal pad formed over a semiconductor substrate; a dummy metal pad spaced apart from the metal pad by an open region; and a Polymide Isoindro Quirazorindione (PIQ) layer formed to cover the open region and to define a pad open region by exposing a center part of the metal pad. The semiconductor device forms an additional open region at a region spaced apart from an edge part of the pad open region, preventing short-circuiting between the metal pad and the adjacent circuit line which might be caused by a crack generated at the edge of the pad open region when a probe is connected to the metal pad, and further preventing a defective semiconductor device from being generated. | 11-13-2014 |
Hyo-June Kim, Icheon KR
Patent application number | Description | Published |
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20140301127 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME - A semiconductor device includes a first conductive layer, a second conductive layer spaced from the first conductive layer, a variable resistance layer interposed between the first and second conductive layers, and an impurity-doped layer provided over a side surface of the variable resistance layer. The variable resistance layer has a smaller width than the first and the second conductive layers. | 10-09-2014 |
20150085559 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - According to embodiments, a semiconductor memory may include: a variable resistance pattern disposed over a substrate and extended in a first direction; first and second structures including a plurality of interlayer dielectric layers and a plurality of conductive layers which are alternately stacked over the substrate, and contacted with one side surface and the other side surface of the variable resistance pattern, respectively, wherein the first stacked structure has a line shape extended in a first direction and the second stacked structure has a pillar shape; and a pillar-shaped conductive pattern contacted with one side surface of the second stacked structure, which is not contacted with the variable resistance pattern. | 03-26-2015 |
20150089087 | ELECTRONIC DEVICE - A semiconductor memory may include: a first stacked structure including a first word line disposed over a substrate and extended in a first direction, a first bit line disposed over the first word line and extended in a second direction crossing the first direction, and a first variable resistance layer interposed between the first word line and the first bit line; and a second stacked structure including a second bit line disposed over the first stacked structure and extended in the second direction, a second word line disposed over the second bit line and extended in the first direction, and a second variable resistance layer interposed between the second word line and the second bit line; and a first selecting element layer interposed between the first bit line and the second bit line. | 03-26-2015 |
20150340608 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME - A semiconductor device includes a first conductive layer, a second conductive layer spaced from the first conductive layer, a variable resistance layer interposed between the first and second conductive layers, and an impurity-doped layer provided over a side surface of the variable resistance layer. The variable resistance layer has a smaller width than the first and the second conductive layers. | 11-26-2015 |
Hyun-Kyu Kim, Icheon KR
Patent application number | Description | Published |
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20150085559 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - According to embodiments, a semiconductor memory may include: a variable resistance pattern disposed over a substrate and extended in a first direction; first and second structures including a plurality of interlayer dielectric layers and a plurality of conductive layers which are alternately stacked over the substrate, and contacted with one side surface and the other side surface of the variable resistance pattern, respectively, wherein the first stacked structure has a line shape extended in a first direction and the second stacked structure has a pillar shape; and a pillar-shaped conductive pattern contacted with one side surface of the second stacked structure, which is not contacted with the variable resistance pattern. | 03-26-2015 |
20150089087 | ELECTRONIC DEVICE - A semiconductor memory may include: a first stacked structure including a first word line disposed over a substrate and extended in a first direction, a first bit line disposed over the first word line and extended in a second direction crossing the first direction, and a first variable resistance layer interposed between the first word line and the first bit line; and a second stacked structure including a second bit line disposed over the first stacked structure and extended in the second direction, a second word line disposed over the second bit line and extended in the first direction, and a second variable resistance layer interposed between the second word line and the second bit line; and a first selecting element layer interposed between the first bit line and the second bit line. | 03-26-2015 |
Jeong Youl Kim, Icheon KR
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20140349474 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device according to an embodiment of the present invention includes fuse patterns spaced apart from each other by a predetermined distance over a first interlayer insulation film; a second interlayer insulation film disposed between the fuse patterns over the first interlayer insulation film; and a capping film pattern formed over the fuse patterns and the second interlayer insulation films, the capping film pattern including a slot exposing the second interlayer insulation film. | 11-27-2014 |
Jong-Gi Kim, Icheon KR
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20160118442 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - Provided is an electronic device including a switching element, wherein the switching element may include a first electrode, a second electrode, a switching layer interposed between the first and second electrodes, and a first amorphous semiconductor layer interposed between the first electrode and the switching layer. | 04-28-2016 |
Jong Il Kim, Icheon KR
Patent application number | Description | Published |
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20140015018 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device having a dummy active region for metal ion gathering, which is capable of preventing device failure due to metal ion contamination, and a method of fabricating the same are provided. The semiconductor device includes active regions defined by an isolation layer in a semiconductor substrate and ion-implanted with an impurity, and a dummy active region ion-implanted with an impurity having a concentration higher than that of the impurity in the active region and configured to gather metal ions. | 01-16-2014 |
20150214108 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device having a dummy active region for metal ion gathering, which is capable of preventing device failure due to metal ion contamination, and a method of fabricating the same are provided. The semiconductor device includes active regions defined by an isolation layer in a semiconductor substrate and ion-implanted with an impurity, and a dummy active region ion-implanted with an impurity having a concentration higher than that of the impurity in the active region and configured to gather metal ions. | 07-30-2015 |
Kyu Sung Kim, Icheon KR
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20140177320 | RESISTIVE MEMORY DEVICE AND WRITE METHOD THEREOF - A method writes data in a resistive memory device in which paths for performing write operations to record first-state data and second-state data are controlled to cause current to flow in opposing directions in a resistive memory cell whose switching type has been determined. The method includes performing a write operation in a predetermined direction when writing the first-state data and second-state data, making a determination with respect to success in target data through verification, and attempting an additional write operation through a path reversed from a write path of corresponding data according to a result of the determination. | 06-26-2014 |
Nam Kyeong Kim, Icheon KR
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20140056074 | NONVOLATILE MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A nonvolatile memory includes a memory cell array including a plurality of nonvolatile memory cells connected to bit lines and word lines crossing the bit lines, a voltage driver configured to provide a word line voltage to the word lines and provide a first voltage during a precharging operation and a second voltage during a sensing operation, based on a voltage setting signal, and a page buffer unit configured to adjust a precharging level of a sensing node connected to a bit line of a page included in a selected memory block of the memory cell array using the first voltage and adjust a sensing level of the sensing node using the second voltage. | 02-27-2014 |
Oh Han Kim, Icheon KR
Patent application number | Description | Published |
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20090236756 | FLIP CHIP INTERCONNECTION SYSTEM - A flip chip interconnection system includes: providing a conductive lead coated with a protective coating; forming a groove through the protective coating to the conductive lead for controlling solder position on a portion of the conductive lead; and attaching a flip chip having a solderable conductive interconnect to the portion of the conductive lead. | 09-24-2009 |
20090243091 | MOCK BUMP SYSTEM FOR FLIP CHIP INTEGRATED CIRCUITS - A mock bump system includes: providing a first structure having an edge; and forming a mock bump near the edge. | 10-01-2009 |
20090321907 | STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM - A stacked integrated circuit package system includes: forming a recessed integrated circuit package system having a first encapsulation over a first integrated circuit and an interior cavity in the first encapsulation; forming a mountable integrated circuit package system having a second integrated circuit over a carrier; and mounting the recessed integrated circuit package system over the mountable integrated circuit package system with the second integrated circuit within the interior cavity and the first integrated circuit coupled with the carrier. | 12-31-2009 |
Sang Hyuk Kim, Icheon KR
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20140199850 | DRY-ETCH FOR SELECTIVE OXIDATION REMOVAL - Methods of selectively etching tungsten oxide relative to tungsten, silicon oxide, silicon nitride and/or titanium nitride are described. The methods include a remote plasma etch formed from a fluorine-containing precursor and/or hydrogen (H | 07-17-2014 |
20150311089 | DRY-ETCH FOR SELECTIVE OXIDATION REMOVAL - Methods of selectively etching tungsten oxide relative to tungsten, silicon oxide, silicon nitride and/or titanium nitride are described. The methods include a remote plasma etch formed from a fluorine-containing precursor and/or hydrogen (H | 10-29-2015 |
Sang-Jin Kim, Icheon KR
Patent application number | Description | Published |
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20140199850 | DRY-ETCH FOR SELECTIVE OXIDATION REMOVAL - Methods of selectively etching tungsten oxide relative to tungsten, silicon oxide, silicon nitride and/or titanium nitride are described. The methods include a remote plasma etch formed from a fluorine-containing precursor and/or hydrogen (H | 07-17-2014 |
20150311089 | DRY-ETCH FOR SELECTIVE OXIDATION REMOVAL - Methods of selectively etching tungsten oxide relative to tungsten, silicon oxide, silicon nitride and/or titanium nitride are described. The methods include a remote plasma etch formed from a fluorine-containing precursor and/or hydrogen (H | 10-29-2015 |
Seong-Hyun Kim, Icheon KR
Patent application number | Description | Published |
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20160005963 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - An electronic device includes a semiconductor memory that includes: an inter-layer dielectric layer including a hole over a substrate; a first nitride layer disposed on sidewalls of the hole; a selector disposed in a bottom portion of the hole and over the first nitride layer on the sidewalls of the hole; a stacked structure including a variable resistance pattern disposed over a lower structure including the selector; and a second nitride layer disposed in an upper portion and on sidewalls of the stacked structure. | 01-07-2016 |
Wan-Gee Kim, Icheon KR
Patent application number | Description | Published |
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20140158966 | VARIABLE RESISTANCE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a variable resistance memory device includes: forming a first metal oxide layer over a first electrode; performing a first implantation process using a first element to a first depth of the first metal oxide layer so as to reduce at least a portion of the first metal oxide layer and form a first oxygen-deficient metal oxide layer; forming a second electrode over the first metal oxide layer; forming a second metal oxide layer over the second electrode; performing a second implantation process using a second element to a second depth of the second metal oxide layer so as to reduce at least a portion of the second metal oxide layer and form a second oxygen-deficient metal oxide layer; and forming a third electrode over the second metal oxide layer. | 06-12-2014 |
20140301127 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME - A semiconductor device includes a first conductive layer, a second conductive layer spaced from the first conductive layer, a variable resistance layer interposed between the first and second conductive layers, and an impurity-doped layer provided over a side surface of the variable resistance layer. The variable resistance layer has a smaller width than the first and the second conductive layers. | 10-09-2014 |
20150070968 | MEMORY DEVICE HAVING A TUNNEL BARRIER LAYER IN A MEMORY CELL, AND ELECTRONIC DEVICE INCLUDING THE SAME - An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of first lines extending in a first direction, a plurality of second lines extending in a second direction crossing the first direction, a resistance variable layer interposed between the first lines and the second lines, a tunnel barrier layer interposed between the resistance variable layer and the first lines, and an intermediate electrode layer interposed between the resistance variable layer and the tunnel barrier layer. The tunnel barrier layer and the intermediate electrode layer overlap with at least two neighboring intersection regions of the first lines and the second lines. | 03-12-2015 |
20150340608 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME - A semiconductor device includes a first conductive layer, a second conductive layer spaced from the first conductive layer, a variable resistance layer interposed between the first and second conductive layers, and an impurity-doped layer provided over a side surface of the variable resistance layer. The variable resistance layer has a smaller width than the first and the second conductive layers. | 11-26-2015 |
20160049582 | MEMORY DEVICE HAVING A TUNNEL BARRIER LAYER IN A MEMORY CELL, AND ELECTRONIC DEVICE INCLUDING THE SAME - An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of first lines extending in a first direction, a plurality of second lines extending in a second direction crossing the first direction, a resistance variable layer interposed between the first lines and the second lines, a tunnel barrier layer interposed between the resistance variable layer and the first lines, and an intermediate electrode layer interposed between the resistance variable layer and the tunnel barrier layer. The tunnel barrier layer and the intermediate electrode layer overlap with at least two neighboring intersection regions of the first lines and the second lines. | 02-18-2016 |
Won Kyu Kim, Icheon KR
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20140017889 | METHOD FOR FORMING FINE PATTERN OF SEMICONDUCTOR DEVICE USING DOUBLE SPACER PATTERNING TECHNOLOGY - A method of forming a fine pattern of a semiconductor device using double SPT process, which is capable of implementing a line and space pattern having a uniform fine line width by applying a double SPT process including a negative SPT process, is provided. The method includes a first SPT process and a second SPT process and the second SPT process includes a Negative SPT process. | 01-16-2014 |
Young Bog Kim, Icheon KR
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20120280394 | SEMICONDUCTOR DEVICE WITH SEG FILM ACTIVE REGION - A semiconductor device and a method for manufacturing the same are provided. A barrier film is formed in a device separating structure, and the device separating structure is etched at a predetermined thickness to expose a semiconductor substrate. Then, a SEG film is grown to form an active region whose area is increased. As a result, a current driving power of a transistor located at a cell region and peripheral circuit regions is improved. | 11-08-2012 |
20150132897 | SEMICONDUCTOR DEVICE WITH SEG FILM ACTIVE REGION - A semiconductor device and a method for manufacturing the same are provided. A barrier film is formed in a device separating structure, and the device separating structure is etched at a predetermined thickness to expose a semiconductor substrate. | 05-14-2015 |