Patent application number | Description | Published |
20090085160 | Semiconductor Device Including Insulating Layer of Cubic System or Tetragonal System - Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode. | 04-02-2009 |
20090127611 | NON-VOLATILE MEMORY DEVICE AND MEMORY CARD AND SYSTEM INCLUDING THE SAME - A non-volatile memory device includes a semiconductor layer including source and drain regions and a channel region between the source and drain regions; a tunneling insulating layer on the channel region of the semiconductor layer; a charge storage layer on the tunneling insulating layer; a blocking insulating layer on the charge storage layer and including a first oxide layer with a first thickness, a high-k dielectric layer, and a second oxide layer with a second thickness different from the first thickness that are stacked sequentially on the charge storage layer; and a control gate on the blocking insulating layer. | 05-21-2009 |
20090159955 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A nonvolatile memory device includes a semiconductor substrate, a tunneling insulation layer on the semiconductor substrate, a charge storage layer on the tunneling insulation layer, an inter-electrode insulation layer on the charge storage layer, and a control gate electrode on the inter-electrode insulation layer. The inter-electrode insulation layer includes a high-k dielectric layer having a dielectric constant greater than that of a silicon nitride, and an interfacial layer between the charge storage layer and the high-k dielectric layer. The interfacial layer includes a silicon oxynitride layer. | 06-25-2009 |
20100072536 | Non-volatile memory device and method of manufacturing the same - In a non-volatile memory device and a method of manufacturing the non-volatile memory device, a tunnel insulating layer, a charge trapping layer, a dielectric layer and a conductive layer may be sequentially formed on a channel region of a substrate. The conductive layer may be patterned to form a gate electrode and spacers may be formed on sidewalls of the gate electrode. A dielectric layer pattern, a charge trapping layer pattern, and a tunnel insulating layer pattern may be formed on the channel region by an anisotropic etching process using the spacers as an etch mask. Sidewalls of the charge trapping layer pattern may be removed by an isotropic etching process to reduce the width thereof. Thus, the likelihood of lateral diffusion of electrons may be reduced or prevented in the charge trapping layer pattern and high temperature stress characteristics of the non-volatile memory device may be improved. | 03-25-2010 |
20100167554 | METHODS FORMING HIGH DIELECTRIC TARGET LAYER - In a method of forming a target layer having a uniform composition of constituent materials, a first precursor including a first central atom and a ligand is chemisorbed on a first reaction site of an object. The ligand or the first central atom is then removed to form a second reaction site. A second precursor including a second central atom is then chemisorbed on the second reaction site. | 07-01-2010 |
20100190320 | METHODS OF REMOVING WATER FROM SEMICONDUCTOR SUBSTRATES AND METHODS OF DEPOSITING ATOMIC LAYERS USING THE SAME - Provided are methods of removing water adsorbed or bonded to a surface of a semiconductor substrate, and methods of depositing an atomic layer using the method of removing water described herein. The method of removing water includes applying a chemical solvent to the surface of a semiconductor substrate, and removing the chemical solvent from the surface of the semiconductor substrate. | 07-29-2010 |
20110014770 | Methods of forming a dielectric thin film of a semiconductor device and methods of manufacturing a capacitor having the same - A method of forming a dielectric thin film of a semiconductor device, the method including supplying a first nuclear atom precursor source and a second nuclear atom precursor source having different thermal decomposition temperatures to a substrate and forming a chemical adsorption layer including first nuclear atoms and second nuclear atoms on the substrate. A reactant including oxygen atoms may be supplied to the substrate on which the chemical adsorption layer is formed. An atomic layer including an oxide of the first nuclear atoms and the second nuclear atoms may be formed on the chemical adsorption layer. | 01-20-2011 |
20120168904 | Semiconductor Device Including Insulating Layer of Cubic System or Tetragonal System - Provided is a semiconductor device including an insulating layer of a cubic system or a tetragonal system, having good electrical characteristics. The semiconductor device includes a semiconductor substrate including an active region, a transistor that is formed in the active region of the semiconductor substrate, an interlevel insulating layer that is formed on the semiconductor substrate and a contact plug that is formed in the interlevel insulating layer and that is electrically connected to the transistor. The semiconductor device may include a lower electrode that is formed on the interlevel insulating layer and that is electrically connected to the contact plug, an upper electrode that is formed on the lower electrode and an insulating layer of a cubic system or a tetragonal system including a metal silicate layer. The insulating layer may be formed between the lower electrode and the upper electrode. | 07-05-2012 |