Patent application number | Description | Published |
20090141546 | Method of operating a phase-change memory device - A method of operating a phase-change memory device including a phase-change layer and a unit applying a voltage to the phase-change layer is provided. The method includes applying a reset voltage to the phase-change layer, wherein the reset voltage includes at least two pulse voltages which are continuously applied. | 06-04-2009 |
20090196089 | Phase change material, phase change memory device including the same, and methods of manufacturing and operating the phase change memory device - Disclosed may be a phase change material alloy, a phase change memory device including the same, and methods of manufacturing and operating the phase change memory device. The phase change material alloy may include Si and Sb. The alloy may be a Si—O—Sb alloy further including O. The Si—O—Sb alloy may be Si | 08-06-2009 |
20090283738 | Phase-change memory using single element semimetallic layer - Provided is a phase-change memory using a single-element semimetallic thin film. The device includes a storage node having a phase-change material layer and a switching element connected to the storage node, wherein the storage node includes a single-element semimetallic thin film which is formed between an upper electrode and a lower electrode. Thus, the write speed of the phase-change memory can be increased compared with the case of a Ge—Sb—Te (GST) based material. | 11-19-2009 |
20110233698 | MAGNETIC MEMORY DEVICES - Provided is a magnetic memory device and a method of forming the same. A first magnetic conductive layer is disposed on a substrate. A first tunnel barrier layer including a first metallic element and a first non-metallic element is disposed on the first magnetic conductive layer. A second magnetic conductive layer is disposed on the first tunnel barrier layer. A content of an isotope of the first metallic element having a non-zero nuclear spin quantum number is lower than a natural state. | 09-29-2011 |
20120099371 | METHOD OF OPERATING A PHASE-CHANGE MEMORY DEVICE - A method of operating a phase-change memory device including a phase-change layer and a unit applying a voltage to the phase-change layer is provided. The method includes applying a reset voltage to the phase-change layer, wherein the reset voltage includes at least two pulse voltages which are continuously applied. | 04-26-2012 |
20130040408 | METHOD OF FABRICATING RESISTANCE VARIABLE MEMORY DEVICE AND DEVICES AND SYSTEMS FORMED THEREBY - An exemplary method of forming a variable resistance memory may include forming first source/drain regions in a substrate, forming gate line structures and conductive isolation patterns buried in the substrate with the first source/drain regions interposed therebetween, and forming lower contact plugs on the first source/drain regions. The forming of lower contact plugs may include forming a first interlayer insulating layer, including a first recess region exposing the first source/drain regions adjacent to each other in a first direction, forming a conductive layer in the first recess region, patterning the conductive layer to form preliminary conductive patterns spaced apart from each other in the first direction, and patterning the preliminary conductive patterns to form conductive patterns spaced apart from each other in a second direction substantially orthogonal to the first direction. | 02-14-2013 |
20130234267 | MAGNETIC DEVICE - A magnetic body structure including: a magnetic layer pattern; and a conductive pattern including a metallic glass alloy and covering at least a portion of the magnetic body structure. | 09-12-2013 |
20140038385 | NONVOLATILE MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - Nonvolatile memory devices and methods of fabricating the same, include, forming a transistor in a first region of a substrate, forming a contact which is connected to the transistor, forming an information storage portion, which is disposed two-dimensionally, in a second region of the substrate, sequentially forming a stop film and an interlayer insulating film which cover the contact and the information storage portion, forming a first trench, which exposes the stop film, on the contact, and forming a second trench which extends through the stop film to expose the contact, wherein a bottom surface of the first trench is lower than a bottom surface of the information storage portion. | 02-06-2014 |
20140117560 | Semiconductor Structures and Methods of Manufacturing the Same - A semiconductor device and methods of forming a semiconductor device are disclosed. In the methods, a layer, such as an insulating interlayer, is formed on a substrate. A first trench is formed in the layer, and a mask layer is formed in the first trench. The mask layer has a first thickness from a bottom surface of the first trench to the top of the mask layer. The mask layer is patterned to form a mask that at least partially exposes a sidewall of the first trench. A portion of the mask adjacent to the exposed sidewall of the first trench has a second thickness smaller than the first thickness. The layer is etched to form a second trench using the mask as an etching mask. The second trench is in fluid communication with the first trench. A conductive pattern is formed in the first trench and the second trench. | 05-01-2014 |
20140264516 | METHODS OF FORMING PATTERNS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME - An insulation layer is formed on a substrate. A first mask is formed on the insulation layer. The first mask includes a plurality of line patterns arranged in a second direction. The plurality of line patterns extend in a first direction substantially perpendicular to the second direction. A second mask is formed on the insulation layer and the first mask. The second mask includes an opening partially exposing the plurality of line patterns. The opening has an uneven boundary at one of a first end portion in the first direction and a second end portion in a third direction substantially opposite to the first direction. The insulation layer is partially removed using the first mask and the second mask as an etching mask, thereby forming a plurality of first trenches and second trenches. The plurality of first trenches and the second trenches are arranged in a staggered pattern. | 09-18-2014 |
20140377950 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, including forming a molding layer; forming a damascene mask layer and mask layer on the molding layer; forming a mask layer pattern by etching the mask layer; forming a damascene pattern by partially etching the damascene mask layer; forming a damascene mask layer on the mask layer pattern to bury the damascene pattern; forming a damascene pattern partially overlapping the damascene pattern by etching the damascene mask layer and the mask layer pattern; connecting the damascene pattern and the damascene pattern by removing a portion of the mask layer pattern exposed by the damascene pattern; forming a damascene mask layer on the damascene mask layer to bury the damascene pattern; and forming a trench under the damascene patterns by etching the damascene mask layers and the molding layer using remaining portions of the mask layer pattern. | 12-25-2014 |
20150017743 | MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - Memory devices and methods of fabricating the same include a substrate including a cell region and a peripheral circuit region, data storages on the cell region, first bit lines on and coupled to the data storages, first contacts coupled to peripheral transistors on the peripheral circuit region, and second bit lines on and coupled to the first contacts. The second bit lines may each have a lowermost surface lower than a lowermost surface of the data storages. | 01-15-2015 |
Patent application number | Description | Published |
20080209720 | Method and Apparatus for Manufacturing a Probe Card - In a method of manufacturing a probe card, a plurality of probe modules, including a sacrificial substrate and probes on the sacrificial substrate, is prepared. The probe modules are mutually aligned to form a probe module assembly having the aligned probe modules and a desired size. The probe module assembly is then attached to a probe substrate. Thus, the probe card having a large size may be manufactured. | 09-04-2008 |
20080290139 | Method of Bonding Probes and Method of Manufacturing a Probe Card Using the Same - In a method of manufacturing bonding probes, bump layer patterns are formed on terminals of a multi-layered substrate. A first wetting layer pattern having a wettability with respect to a solder paste, and a non-wetting layer pattern having a non-wettability with respect to the solder paste are formed on the bump layer patterns. The solder paste is formed on the first wetting layer and the non-wetting layer pattern. The probes, which make contact with an object, are bonded to the solder paste. The solder paste on the non-wetting layer pattern reflows along a surface of the first wetting layer pattern to form an adhesive layer on the first wetting layer pattern. Thus, a sufficient amount of the solder paste, which is required for bonding the probes, may be provided to firmly bond the probes. | 11-27-2008 |
20090128180 | Cantilever-Type Probe and Method of Fabricating the Same - Disclosed is a cantilever-type probe and methods of fabricating the same. The probe is comprised of a cantilever being longer lengthwise relative to the directions of width and height, and a tip extending from the bottom of the cantilever and formed at an end of the cantilever. A section of the tip parallel to the bottom of the cantilever is rectangular, having four sides slant to the lengthwise direction of the cantilever. | 05-21-2009 |
20090184727 | Space Transformer, Manufacturing Method of the Space Transformer and Probe Card Having the Space Transformer - Provided is a probe card of a semiconductor testing apparatus, including a printed circuit board to which an electrical signal is applied from external, a space transformer having a plurality of probes directly contacting with a test object, and interconnectors connecting the printed circuit board to the probes of the space transformer. The space transformer includes substrate pieces which the probes are installed on one sides of, and a combination member joining and unifying the substrate pieces together so as to form a large-area substrate with the substrate pieces on the same plane. This probe card is advantageous to improving flatness even with a large area, as well as testing semiconductor chips formed on a wafer in a lump. | 07-23-2009 |