Patent application number | Description | Published |
20100308884 | CLOCK RECEIVER IN SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF CONTROLLING THE SAME - A clock receiver in a semiconductor integrated circuit includes a first clock buffer configured to buffer an external clock to generate a low frequency buffered clock in response to a first operation signal; a second clock buffer configured to buffer the external clock to generate a high frequency buffered clock in response to a second operation signal; and an internal clock generating unit configured to receive the low frequency buffered clock and the high frequency buffered clock, to control states of the first operation signal and the second operation signal and to generate an internal clock. | 12-09-2010 |
20110128059 | DUTY CORRECTION CIRCUIT - A duty correction circuit is presented for use in compensating for a duty rate error brought about when a malfunction of a clock signal generator or a failure of a signal transmission line occurs. The duty correction circuit is configured to select one of differential signals as an input signal according to a duty rate. The duty correction circuit is also configured to combine the input signal and a signal obtained by delaying the input signal by a delay time adjusted in accordance to the duty rate. The duty correction circuit is also configured to generate the combined signal as a duty correction signal. | 06-02-2011 |
20110204951 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus for generating an internal voltage includes a control code output block and an internal voltage generation block. The control code output block is configured to output a variable code having a code value corresponding to a voltage level of an internal voltage. The internal voltage generation block is configured to compare the variable code to a setting code and controls the voltage level of the internal voltage according to the comparison. | 08-25-2011 |
20110241742 | DATA OUTPUT CONTROL CIRCUIT - A data output control circuit includes a DLL circuit and a delay detection unit. The DLL circuit is configured to generate a second internal clock by delaying a first internal clock generated from an external clock, compare a phase of the first internal clock with a phase of the second internal clock, and generate a DLL clock. The delay detection unit is configured to generate a sense signal whose logic level is changed according to a comparison result of a set time interval and a delay time interval during which the first internal clock is delayed in order to generate the second internal clock. | 10-06-2011 |
20110242905 | SEMICONDUCTOR MODULE INCLUDING MODULE CONTROL CIRCUIT AND METHOD FOR CONTROLLING THE SAME - A module control circuit includes an input unit configured to receive a plurality of data signals from a plurality of data input/output pins and output an identification signal and an internal command signal. A latch unit is configured to latch the identification signal in accordance with a first enable signal to output a first group identification signal, latch the identification signal in accordance with a second enable signal to output a second group identification signal, and latch the internal command signal in accordance with the second enable signal to output a group command signal. A comparator is configured to compare the first group identification signal with the second group identification signal, and generate a selection signal. A multiplexer is configured to select one of the group command signal and a module command signal as an input command in response to the selection signal. | 10-06-2011 |
20140176191 | COMPARATOR CIRCUIT AND SIGNAL COMPARISON METHOD - A comparator circuit includes a first comparator configured to store an offset during a first period, and to compare first and second input signals while compensating for the stored offset to generate a first comparison signal during a second period, a second comparator configured to compare the first and second input signals while compensating for an offset to generate a second comparison signal, and a compensation amount controller configured to control an offset compensation amount of the second comparator when the first and second comparison signals have different values. | 06-26-2014 |
20150378189 | LIGHT CONTROLLING APPARATUS, METHOD OF FABRICATING THE LIGHT CONTROLLING APPARATUS, AND TRANSPARENT DISPLAY DEVICE INCLUDING THE LIGHT CONTROLLING APPARATUS - A light controlling apparatus, a method of fabricating the light controlling apparatus, and a transparent display device including the light controlling apparatus are disclosed, in which light may be transmitted or shielded using a polymer dispersed liquid crystal (PDLC) layer and a guest-host liquid crystal (GHLC) layer, where the guest-host liquid crystal layer includes dichroic dyes. The light controlling apparatus includes first and second substrates facing each other; a first electrode on the first substrate; a second electrode on the second substrate; and a polymer dispersed liquid crystal (PDLC) layer and a guest-host liquid crystal (GHLC) layer between the first electrode and the second electrode, wherein the PDLC layer includes first liquid crystals having droplets, and the GHLC layer includes second liquid crystals and dichroic dyes. | 12-31-2015 |
20150378205 | LIGHT CONTROLLING APPARATUS AND TRANSPARENT DISPLAY INCLUDING THE SAME - A light controlling apparatus includes first and second substrates facing each other; a first electrode on the first substrate; a second electrode on the second substrate; and a liquid crystal layer between the first electrode and the second electrode, the liquid crystal layer including cholesteric liquid crystals, wherein the cholesteric liquid crystals have a focal conic state in a light shielding mode in case where no voltage is applied, and have a homeotropic state in a transparent mode in case where a voltage is applied. | 12-31-2015 |