Patent application number | Description | Published |
20080258277 | Semiconductor Device Comprising a Semiconductor Chip Stack and Method for Producing the Same - A semiconductor device includes a semiconductor chip stack having at least one lower semiconductor chip as a base of the semiconductor chip stack, and at least one upper semiconductor chip. An insulating intermediate plate is arranged between the semiconductor chips. Connecting elements wire the semiconductor chips, the intermediate plate and external terminals to one another. | 10-23-2008 |
20090051016 | ELECTRONIC COMPONENT WITH BUFFER LAYER - An electronic component includes a metal substrate, a semiconductor chip configured to be attached to the metal substrate, and a buffer layer positioned between the metal substrate and the semiconductor chip configured to mechanically decouple the semiconductor chip and the metal substrate. The buffer layer extends across less than an entire bottom surface of the semiconductor chip. | 02-26-2009 |
20100213613 | ARRANGEMENT FOR ELECTRICALLY CONNECTING SEMICONDUCTOR CIRCUIT ARRANGEMENTS TO AN EXTERNAL CONTACT DEVICE AND METHOD FOR PRODUCING THE SAME - An electrical connection arrangement between a semiconductor circuit arrangement and an external contact device, and to a method for producing the connection arrangement is disclosed. In one embodiment, a metallic layer is deposited onto at least one contact terminal and/or the contacts and the wire, the metallic layer protecting the contact terminal or the electrical connection against ambient influences and ensuring a high reliability. | 08-26-2010 |
20110285033 | Chip Carrier - Electronic circuit arrangement, includes a chip and a chip carrier having a substrate and a chip contact location. At least the chip contact location is provided with a soldering layer. The chip includes a bonding layer. A silver layer for eutectic bonding with the bonding layer is provided on the soldering layer in the region of the chip contact location. | 11-24-2011 |
20110291252 | METHOD AND SYSTEM FOR FORMING A THIN SEMICONDUCTOR DEVICE - A method and system for forming a thin semiconductor device are disclosed. In one embodiment, a lead frame is provided over a carrier. At least one semiconductor chip is provided on the lead frame and the at least one semiconductor chip is enclosed with an encapsulating material. The thickness of the at least one semiconductor chip and the encapsulating material are reduced. At least one through connection is formed in the encapsulating material and at least one electrical contact element is formed over the at least one semiconductor chip and the at least one through connection. | 12-01-2011 |
20120025384 | ELECTRONIC DEVICE AND METHOD FOR PRODUCTION - An electronic device and method for production is disclosed. One embodiment provides an integrated component having a first layer which is composed of copper or a copper alloy or which contains copper or a copper alloy, and having an electrically conductive second layer, whose material differs from the material of the first layer, and a connection apparatus which is arranged on the first layer and on the second layer. | 02-02-2012 |
20120061835 | DIE STRUCTURE, DIE ARRANGEMENT AND METHOD OF PROCESSING A DIE - A die structure includes a die and a metallization layer disposed over the front side of the die. The metallization layer includes copper. At least a part of the metallization layer has a rough surface profile. The part with the rough surface profile includes a wire bonding region, to which a wire bonding structure is to be bonded. | 03-15-2012 |
20120068364 | Device and Method for Manufacturing a Device - A device includes a semiconductor material having a first surface. A first material is applied to the first surface and a fiber material is embedded in the first material. | 03-22-2012 |
20120074553 | METHOD AND SYSTEM FOR IMPROVING RELIABILITY OF A SEMICONDUCTOR DEVICE - A method and a system for improving reliability of a semiconductor device are provided. In one embodiment, a semiconductor device is provided comprising a semiconductor chip, a metallization layer comprising a metallic material disposed over a surface of the semiconductor chip, and an alloy layer comprising the metallic material disposed over the metallization layer. | 03-29-2012 |
20120074568 | METHOD AND SYSTEM FOR MINIMIZING CARRIER STRESS OF A SEMICONDUCTOR DEVICE - A method and a system for minimizing carrier stress of a semiconductor device are provided. In one embodiment, a semiconductor device is provided comprising a carrier comprising a mesh coated with a metallic material, and a semiconductor chip disposed over the carrier. | 03-29-2012 |
20120267784 | Semiconductor Device and Bonding Wire - A semiconductor device includes a semiconductor chip, a contact pad of the semiconductor chip and a first layer arranged over the contact pad. The first layer includes niobium, tantalum or an alloy including niobium and tantalum. | 10-25-2012 |
20120292773 | Method for Producing a Metal Layer on a Substrate and Device - A method produces a metal layer on a semiconductor substrate. A metal layer is produced on the semiconductor substrate by depositing metal particles. The metal particles include cores made of a first metal material and shells surrounding the cores. The shells are made of a second metal material that is resistant to oxidation. | 11-22-2012 |
20120327614 | METHOD FOR ATTACHING A METAL SURFACE TO A CARRIER, A METHOD FOR ATTACHING A CHIP TO A CHIP CARRIER, A CHIP-PACKAGING MODULE AND A PACKAGING MODULE - A method for attaching a metal surface to a carrier is provided, the method including: forming a first polymer layer over the metal surface; forming a second polymer layer over a surface of the carrier; and bringing the first polymer layer into physical contact with the second polymer layer such that at least one of an interpenetrating polymer structure and an inter-diffusing polymer structure is formed between the first polymer layer and the second polymer layer. | 12-27-2012 |
20130001803 | METHOD FOR ATTACHING A METAL SURFACE TO A CARRIER, A METHOD FOR ATTACHING A CHIP TO A CHIP CARRIER, A CHIP-PACKAGING MODULE AND A PACKAGING MODULE - A method for attaching a metal surface to a carrier is provided, the method including: depositing a porous layer over at least one of a metal surface and a side of a carrier; and attaching the at least one of a metal surface and a side of a carrier to the porous layer by bringing a material into pores of the porous layer, resulting in the material forming an interconnection between the metal surface and the carrier. | 01-03-2013 |
20130021766 | Electronic Component - An electronic component includes an electrically conductive carrier. The electrically conductive carrier includes a carrier surface and a semiconductor chip includes a chip surface. One or both of the carrier surface and the chip surface include a non-planar structure. The chip is attached to the carrier with the chip surface facing towards the carrier surface so that a gap is provided between the chip surface and the carrier surface due to the non-planar structure of one or both of the carrier surface and the first chip surface. The electronic component further includes a first galvanically deposited metallic layer situated in the gap. | 01-24-2013 |
20130105977 | Electronic Device and Method for Fabricating an Electronic Device | 05-02-2013 |
20130113114 | Device Including Two Power Semiconductor Chips and Manufacturing Thereof - A device includes a first power semiconductor chip having a first face and a second face opposite to the first face with a first contact pad arranged on the first face. The first contact pad is an external contact pad. The device further includes a first contact clip attached to the second face of the first power semiconductor chip. A second power semiconductor chip is attached to the first contact clip, and a second contact clip is attached to the second power semiconductor chip. | 05-09-2013 |
20130127031 | CHIP-CARRIER, A METHOD FOR FORMING A CHIP-CARRIER AND A METHOD FOR FORMING A CHIP PACKAGE - Various embodiments provide a chip-carrier including, a chip-carrier surface configured to carry a first chip from a first chip bottom side, wherein a first chip top side of the first chip is configured above the chip-carrier surface; and at least one cavity extending into the chip-carrier from the chip-carrier surface; wherein the at least one cavity is configured to carry a second chip from a second chip bottom side, wherein a second chip top side of the second chip is substantially level with the first chip top side. The second chip is electrically insulated from the chip-carrier by an electrical insulation material inside the cavity. | 05-23-2013 |
20130134589 | CHIP-PACKAGE AND A METHOD FOR FORMING A CHIP-PACKAGE - A chip-package includes a chip-carrier configured to carry a chip, the chip arranged over a chip-carrier side, wherein the chip-carrier side is configured in electrical connection with a chip back side; an insulation material including: a first insulation portion formed over a first chip lateral side; a second insulation portion formed over a second chip lateral side, wherein the first chip lateral side and the second chip lateral side each abuts opposite edges of the chip back side; and a third insulation portion formed over at least part of a chip front side, the chip front side including one or more electrical contacts formed within the chip front side; wherein at least part of the first insulation portion is arranged over the chip-carrier side and wherein the first insulation portion is configured to extend in a direction perpendicular to the first chip lateral side further than the chip-carrier. | 05-30-2013 |
20130152696 | MICROMECHANICAL SEMICONDUCTOR SENSING DEVICE - Micromechanical semiconductor sensing device comprises a micromechanical sensing structure being configured to yield an electrical sensing signal, and a piezoresistive sensing device provided in the micromechanical sensing structure, said piezoresistive sensing device being arranged to sense a mechanical stress disturbing the electrical sensing signal and being configured to yield an electrical disturbance signal based on the sensed mechanical stress disturbing the electrical sensing signal. | 06-20-2013 |
20130249069 | CIRCUIT PACKAGE, AN ELECTRONIC CIRCUIT PACKAGE, AND METHODS FOR ENCAPSULATING AN ELECTRONIC CIRCUIT - A circuit package is provided, the circuit package including: an electronic circuit; a metal block next to the electronic circuit; encapsulation material between the electronic circuit and the metal block; a first metal layer structure electrically contacted to at least one first contact on a first side of the electronic circuit; a second metal layer structure electrically contacted to at least one second contact on a second side of the electronic circuit, wherein the second side is opposite to the first side; wherein the metal block is electrically contacted to the first metal layer structure and to the second metal layer structure by means of an electrically conductive medium; and wherein the electrically conductive medium includes a material different from the material of the first and second metal layer structures or has a material structure different from the material of the first and second metal layer structures. | 09-26-2013 |
20130264721 | Electronic Module - The electronic module includes a first carrier and a first semiconductor chip arranged on the first carrier. A second semiconductor chip is arranged above the first semiconductor chip. A material layer adheres the second semiconductor chip to the first carrier and encapsulates the first semiconductor chip. | 10-10-2013 |
20130277824 | Manufacturing Method for Semiconductor Device and Semiconductor Device - In a method of manufacturing a semiconductor device, a first semiconductor element is mounted on a carrier. A b-stage curable polymer is deposited on the carrier. A second semiconductor element is affixed on the polymer. | 10-24-2013 |
20130299848 | Semiconductor Packages and Methods of Formation Thereof - In one embodiment, a semiconductor package includes a vertical semiconductor chip having a first major surface on one side of the vertical semiconductor chip and a second major surface on an opposite side of the vertical semiconductor chip. The first major surface includes a first contact region and the second major surface includes a second contact region. The vertical semiconductor chip is configured to regulate flow of current from the first contact region to the second contact region along a current flow direction. A back side conductor is disposed at the second contact region of the second major surface. The semiconductor package further includes a first encapsulant in which the vertical semiconductor chip and the back side conductor are disposed. | 11-14-2013 |
20130328197 | ELECTRONIC DEVICE AND METHOD FOR PRODUCTION - An electronic device and method for production is disclosed. One embodiment provides an integrated component having a first layer which is composed of copper or a copper alloy or which contains copper or a copper alloy, and having an electrically conductive second layer, whose material differs from the material of the first layer, and a connection apparatus which is arranged on the first layer and on the second layer. | 12-12-2013 |
20130329365 | Electric Device Package and Method of Making an Electric Device Package - A system and method for manufacturing an electric device package are disclosed. An embodiment comprises a carrier, a component disposed on the carrier, the component having a first component contact pad, and a first electrical connection between the first component contact pad and a first carrier contact pad, wherein the first electrical connection comprises a first hollow space, the first hollow space comprising a first liquid. | 12-12-2013 |
20130341778 | Device Contact, Electric Device Package and Method of Manufacturing an Electric Device Package - An electric device and a method of making an electric device are disclosed. In one embodiment the electric device comprises a component comprising a component contact area and a carrier comprising a carrier contact area. The electric device further comprises a first conductive connection layer connecting the component contact area with the carrier contact area, wherein the first conductive connection layer overlies a first region of the component contact area and a second connection layer connecting the component contact area with the carrier contact area, wherein the second connection layer overlies a second region of the component contact area, and wherein the second connection layer comprises a polymer layer. | 12-26-2013 |
20140021638 | EMBEDDED INTEGRATED CIRCUIT PACKAGE AND METHOD FOR MANUFACTURING AN EMBEDDED INTEGRATED CIRCUIT PACKAGE - A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects. | 01-23-2014 |
20140027892 | Electric Device Package Comprising a Laminate and Method of Making an Electric Device Package Comprising a Laminate - A system and method for manufacturing an electric device package are disclosed. An embodiment comprises comprising a first carrier contact, a first electric component, the first electric component having a first top surface and a first bottom surface, the first electric component comprising a first component contact disposed on the first top surface, the first bottom surface being connected to the carrier and an connection element comprising a second electric component and an interconnect element, the connection element having a connection element top surface and a connection element bottom surface, wherein the connection element bottom surface comprises a first connection element contact and a second connection element contact, and wherein the first connection element contact is connected to the first component contact and the second connection element contact is connected to the first carrier contact. The packaged device further comprises an encapsulant encapsulating the first electric component. | 01-30-2014 |
20140042603 | Electronic Device and Method of Fabricating an Electronic Device - A semiconductor device includes an electrically conducting carrier and a semiconductor chip disposed over the carrier. The semiconductor device also includes a porous diffusion solder layer provided between the carrier and the semiconductor chip. | 02-13-2014 |
20140061878 | INTEGRATED CIRCUITS AND A METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT - An integrated circuit is provided. The integrated circuit includes: a chip and encapsulation material covering at least three sides of the chip, the encapsulation material being formed from adhesive material. The integrated circuit includes a carrier adhered to the chip by means of the encapsulation material. | 03-06-2014 |
20140076613 | Method of Electrophoretic Depositing (EPD) a Film on a System and System Thereof - A packaged component and a method for making a packaged component are disclosed. In an embodiment the packaged component includes a component carrier having a component carrier contact and a component disposed on the component carrier, the component having a component contact. The packaged component further includes a conductive connection element connecting the component carrier contact with the component contact, an insulating film disposed directly at least on one of a top surface of the component or the conductive connection element, and an encapsulant encapsulating the component carrier, the component and the enclosed conductive connection elements. | 03-20-2014 |
20140084302 | INTEGRATED CIRCUIT, A CHIP PACKAGE AND A METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT - An integrated circuit is provided, the integrated circuit including: a carrier including at least one electronic component and at least one contact area disposed on a first side of the carrier, wherein the at least one electronic component is electrically connected to the at least one contact area; an inorganic material layer wafer bonded to the first side of the carrier, wherein the carrier has a first coefficient of thermal expansion, and wherein the inorganic material layer has a second coefficient of thermal expansion, wherein the second coefficient of thermal expansion has a difference of less than 100% compared with the first coefficient of thermal expansion; and at least one contact via formed through the inorganic material layer, wherein the at least one contact via contacts the at least one contact area. | 03-27-2014 |
20140084433 | Semiconductor Device Having a Clip Contact - A semiconductor device comprises a carrier. Further, the semiconductor devices comprises a semiconductor chip comprising a first main surface and a second main surface opposite to the first main surface, wherein a first electrode is arranged on the first main surface and the semiconductor chip is mounted on the carrier with the second main surface facing the carrier. Further, an encapsulation body embedding the semiconductor chip is provided. The semiconductor device further comprises a contact clip, wherein the contact clip is an integral part having a bond portion bonded to the first electrode and having a terminal portion forming an external terminal of the semiconductor device. | 03-27-2014 |
20140117531 | SEMICONDUCTOR DEVICE WITH ENCAPSULANT - Described are techniques related to semiconductor devices that make use of encapsulant. In one implementation, a semiconductor device may be manufactured to include at least an encapsulant that includes at least glass particles. | 05-01-2014 |
20140126165 | Packaged Nano-Structured Component and Method of Making a Packaged Nano-Structured Component - An assembled component and a method for assembling a component are disclosed. In one embodiment the assembled component includes a component carrier, an attachment layer disposed on the component carrier and a component disposed on the attachment layer, the component having a nano-structured first main surface facing the component carrier. | 05-08-2014 |
20140138833 | Semiconductor Device Assembly Including a Chip Carrier, Semiconductor Wafer and Method of Manufacturing a Semiconductor Device - A semiconductor device includes a chip carrier and a semiconductor die with a semiconductor portion and a conductive structure. A soldered layer mechanically and electrically connects the chip carrier and the conductive structure at a soldering side of the semiconductor die. At the soldering side an outermost surface portion along an edge of the semiconductor die has a greater distance to the chip carrier than a central surface portion. The conductive structure covers the central surface portion and at least a section of an intermediate surface portion tilted to the central surface portion. Solder material is effectively prevented from coating such semiconductor surfaces that are prone to damages and solder-induced contamination is significantly reduced. | 05-22-2014 |
20140138841 | INTEGRATED CIRCUIT, A SEMICONDUCTOR DIE ARRANGEMENT AND A METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT - An integrated circuit is provided, the integrated circuit including: a chip having a first chip side and a second chip side opposite to the first chip side, the chip having at least one contact area on the second chip side; encapsulation material at least partially covering the chip; and at least one contact via comprising electrical conductive material contacting the at least one contact area and extending through the encapsulation material and through the chip between the first chip side and the second chip side. | 05-22-2014 |
20140138843 | Method for Fabricating an Electronic Component - A carrier and a semiconductor chip are provided. A connection layer is applied to a first main face of the semiconductor chip. The connection layer includes a plurality of depressions. A filler is applied to the connection layer or to the carrier. The semiconductor chip is attached to the carrier so that the connection layer is disposed between the semiconductor chip and the carrier. The semiconductor chip is affixed to the carrier. | 05-22-2014 |
20140151862 | EMBEDDED INTEGRATED CIRCUIT PACKAGE AND METHOD FOR MANUFACTURING AN EMBEDDED INTEGRATED CIRCUIT PACKAGE - A embedded integrated circuit package is provided, the embedded integrated circuit package including: at least one chip arranged over a chip carrier, the at least one chip including a plurality of chip contact pads; encapsulation material formed over the chip carrier and at least partially surrounding the at least one chip; a plurality of electrical interconnects formed through the encapsulation material, wherein each electrical interconnect is electrically connected to a chip contact pad; and a structure formed between the electrical interconnects of the embedded integrated circuit package, wherein the structure increases the creepage resistance between the electrical interconnects. | 06-05-2014 |
20140197527 | CHIP ARRANGEMENT AND A METHOD FOR MANUFACTURING A CHIP ARRANGEMENT - A chip arrangement is provided, the chip arrangement, including a carrier; a first chip electrically connected to the carrier; a ceramic layer disposed over the carrier; and a second chip disposed over the ceramic layer; wherein the ceramic layer has a porosity in the range from about 3% to about 70%. | 07-17-2014 |
20140197552 | CHIP ARRANGEMENT, A METHOD FOR MANUFACTURING A CHIP ARRANGEMENT, INTEGRATED CIRCUITS AND A METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT - A chip arrangement is provided, the chip arrangement, including a carrier; at least one chip electrically connected to a carrier top side; an encapsulation material at least partially surrounding the at least one chip and the carrier top side, wherein the encapsulation material is formed on one or more lateral sides of the carrier; and a ceramic material disposed on a carrier bottom side, and on at least one side of the encapsulation material. | 07-17-2014 |
20140218885 | Device Including a Semiconductor Chip and Wires - A device includes a carrier, a first semiconductor chip arranged over the carrier and a first electrically conductive element arranged over the carrier. The device further includes a first wire electrically coupled to the first electrically conductive element and a second wire electrically coupled to the first electrically conductive element and to the first semiconductor chip. The first electrically conductive element is configured to forward an electrical signal between the first wire and the second wire. | 08-07-2014 |
20140239466 | Electronic Device - An electronic device includes a first transistor device with first contact elements, a second transistor device with second contact elements, and an electrical connection member with a first main face and a second main face opposite to the first main face. The first transistor device is disposed on the first main face of the electrical connection member and the second transistor device is disposed on the second main face of the electrical connection member. One of the first contact elements is electrically connected with one of the second contact elements by a part of the electrical connection member. | 08-28-2014 |
20140240945 | Multi-Die Package with Separate Inter-Die Interconnects - A first electrode at a first side of a first semiconductor die is connected to a first conductive region of a substrate. A first electrode at a first side of a second semiconductor die is connected to a second conductive region of the substrate. Each die has a second electrode at an opposing second side of the respective die. A first metal layer extends from a periphery region of the substrate to over the first die. The first metal layer has a generally rectangular cross-sectional area and connects one of the conductive regions in the periphery region of the substrate to the second electrode of the first die. A second metal layer separate from the first metal layer extends over the first and second dies. The second metal layer has a generally rectangular cross-sectional area and connects the second electrodes of the first and second dies. | 08-28-2014 |
20140246766 | Semiconductor Chip Package - The semiconductor chip package comprises a carrier, a semiconductor chip comprising a first main face and a second main face opposite to the first main face, chip contact elements disposed on one or more of the first or second main faces of the semiconductor chip, an encapsulation layer covering the first main face of the semiconductor chip, the encapsulation layer comprising a first main face facing the carrier and a second main face remote from the carrier, first contact elements disposed on the second main face of the encapsulation layer, each one of the first contact elements being connected to one of the chip contact elements, and second contact elements disposed on the first main face of the encapsulation layer, each one of the second contact elements being connected to one of the chip contact elements. | 09-04-2014 |
20140264919 | CHIP ARRANGEMENT, WAFER ARRANGEMENT AND METHOD OF MANUFACTURING THE SAME - Various embodiments provide a chip arrangement. The chip arrangement may include a first chip having a first chip side and a second chip side opposite the first chip side and at least one contact on its second chip side; a second chip having a first chip side and a second chip side opposite the first chip side and at least one contact on its first chip side; wherein the second chip side of the first chip and the second chip side of the second chip are facing each other; a first electrically conductive structure extending from the at least one contact of the first chip from the second chip side of the first chip through the first chip to the first chip side of the first chip; and a second electrically conductive structure. | 09-18-2014 |
20140264950 | CHIP ARRANGEMENT AND A METHOD OF MANUFACTURING A CHIP ARRANGEMENT - In various embodiments, a chip arrangement is provided. The chip arrangement may include a chip carrier and a chip mounted on the chip carrier. The chip may include at least two chip contacts and an insulating adhesive between the chip and the chip carrier to adhere the chip to the chip carrier. The at least two chip contacts may be electrically coupled to the chip carrier. | 09-18-2014 |
20140301039 | PACKAGE AND A METHOD OF MANUFACTURING THE SAME - In various embodiments, a package may be provided. The package may include a chip carrier. The package may further include a chip arranged over the chip carrier. The package may also include encapsulation material encapsulating the chip and partially the chip carrier. A coolant receiving recess may be provided over the chip in the encapsulation material, wherein the coolant receiving recess is configured to receive coolant. | 10-09-2014 |
20140312394 | Semiconductor Device Including a Material to Absorb Thermal Energy - A semiconductor device includes a semiconductor chip and a first material including molecules that are configured to absorb thermal energy by reversibly changing a spatial molecular structure of the molecules. | 10-23-2014 |
20140353808 | Packaged Semiconductor Device - Disclosed is a packaged device, comprising a carrier comprising a first carrier contact, a first electrical component having a first top surface and a first bottom surface, the first electrical component comprising a first component contact disposed on the first top surface, the first bottom surface being connected to the carrier, an embedded system comprising a second electrical component having a second top surface, an interconnect element, and a first connecting element, the embedded system having a system bottom surface, wherein the system bottom surface comprises a first system contact, wherein the second top surface comprises a first component contact, and wherein the first system contact is connected to the first component contact by the interconnect element and the first component contact of the second electrical component is connected to the first carrier contact by means of the first connecting element. | 12-04-2014 |
20150028448 | Chip Package with Embedded Passive Component - A chip package includes an electrically conducting chip carrier and at least one first semiconductor chip attached to the electrically conducting chip carrier. The chip package further includes a passive component. The electrically conducting chip carrier, the at least one first semiconductor chip, and the passive component are embedded in an insulating laminate structure. | 01-29-2015 |
20150028487 | Chip Package with Passives - A chip package device includes an electrically conducting chip carrier, at least one semiconductor chip attached to the electrically conducting chip carrier, and an insulating laminate structure embedding the chip carrier, the at least one semiconductor chip and a passive electronic device. The passive electronic device includes a first structured electrically conducting layer, the first structured electrically conducting layer extending over a surface of the laminate structure. | 01-29-2015 |
20150035170 | MULTICHIP DEVICE INCLUDING A SUBSTRATE - A device includes a substrate including an electrically insulating core, a first electrically conductive material arranged over a first main surface of the substrate, and a second electrically conductive material arranged over a second main surface of the substrate opposite to the first main surface. The device further includes an electrically conductive connection extending from the first main surface to the second main surface and electrically coupling the first electrically conductive material and the second electrically conductive material, a first semiconductor chip arranged over the first main surface and electrically coupled to the first electrically conductive material, and a second semiconductor chip arranged over the second main surface and electrically coupled to the second electrically conductive material. | 02-05-2015 |
20150060872 | Encapsulated Semiconductor Device - A semiconductor device includes a carrier and a semiconductor chip disposed over the carrier. The semiconductor chip has a first surface and a second surface opposite to the first surface, wherein the second surface faces the carrier. Further, the semiconductor device includes a pre-encapsulant covering at least partially the second surface of the semiconductor chip and at least partially a side wall surface of the semiconductor chip. The pre-encapsulant has a thermal conductivity of equal to or greater than 10 W/(m·K) and a specific heat capacity of equal to or greater than 0.2 J/(g·K). | 03-05-2015 |
20150076672 | METHOD OF MANUFACTURING A CHIP PACKAGE, CHIP PACKAGE, METHOD OF MANUFACTURING A CHIP ASSEMBLY AND CHIP ASSEMBLY - A method of manufacturing a chip package is provided. The method may include electrically contacting at least one first chip, the first chip including a first side and a second side opposite the first side, with its second side to an electrically conductive carrier. An insulating layer is formed over at least a part of the electrically conductive carrier and over at least a part of the first side of the chip. At least one second chip is arranged over the insulating layer. An encapsulating material is formed over the first chip and the second chip. Electrical contacts are formed through the encapsulation material to at least one contact of the at least one first chip and to at least one contact of the at least one second chip. | 03-19-2015 |
20150077941 | Electronic Power Device and Method of Fabricating an Electronic Power Device - An electronic device comprises a power module comprising a first main surface and a second main surface opposite to the first main surface, wherein at least a portion of the first main surface is configured as a heat dissipating surface without electrical power terminal functionality. The electronic device comprises a porous metal layer arranged on the portion of the first main surface. | 03-19-2015 |