Patent application number | Description | Published |
20130111107 | TIER IDENTIFICATION (TID) FOR TIERED MEMORY CHARACTERISTICS | 05-02-2013 |
20130290462 | DATA CACHING USING LOCAL AND REMOTE MEMORY - A system and method for retrieving cached data are disclosed herein. The system includes a cache server including a local memory and a table residing on the local memory, wherein the table is used to identify data objects corresponding to cached data. The system also includes the data objects residing on the local memory, wherein the data objects contain pointers to the cached data. The system further includes a remote memory communicatively coupled to the cache server through an Input-Output (I/O) connection, wherein the cached data resides on the remote memory. | 10-31-2013 |
20130290643 | USING A CACHE IN A DISAGGREGATED MEMORY ARCHITECTURE - Example caches in a disaggregated memory architecture are disclosed. An example apparatus includes a cache to store a first key in association with a first pointer to a location at a remote memory. The location stores a first value corresponding to the first key. The example apparatus includes a receiver to receive a plurality of key-value pairs from the remote memory based on the first key. The first value specifies the key-value pairs for retrieval from the remote memory. | 10-31-2013 |
20140040528 | RECONFIGURABLE CROSSBAR NETWORKS - Reconfigurable crossbar networks, and devices, systems and methods, including hardware in the form of logic (e.g. application specific integrated circuits (ASICS)), and software in the form of machine readable instructions stored on machine readable media (e.g., flash, non-volatile memory, etc.), which implement the same, are provided. An example of a reconfigurable crossbar network includes a crossbar. A plurality of endpoints is coupled to the crossbar. The plurality of endpoints is grouped into regions at design time of the crossbar network. A plurality of regional interconnects are provided. Each regional interconnect connects a group of endpoints within a given region. | 02-06-2014 |
20140215158 | Executing Requests from Processing Elements with Stacked Memory Devices - Executing requests from processing elements with stacked memory devices includes receiving a request from a processing element, determining which of multiple memory devices contains information pertaining to the request, forwarding the request to a selected memory device of the memory devices, and responding to the processing element with the information in response to receiving the information from the selected memory device. | 07-31-2014 |
20140215160 | METHOD OF USING A BUFFER WITHIN AN INDEXING ACCELERATOR DURING PERIODS OF INACTIVITY - A method of using a buffer within an indexing accelerator during periods of inactivity, comprising flushing indexing specific data located in the buffer, disabling a controller within the indexing accelerator, handing control of the buffer over to a higher level cache, and selecting one of a number of operation modes of the buffer. An indexing accelerator, comprising a controller and a buffer communicatively coupled to the controller, in which, during periods of inactivity, the controller is disabled and a buffer operating mode among a number of operating modes is chosen under which the buffer will be used. | 07-31-2014 |
20140215260 | MEMCACHED SERVER REPLICATION - According to an example, data for a memcached server is replicated to a memcached replication server. Data operations for the memcached server may be filtered for backing up data to the memcached replication server. | 07-31-2014 |
20140325160 | CACHING CIRCUIT WITH PREDETERMINED HASH TABLE ARRANGEMENT - Disclosed herein are an apparatus, an integrated circuit, and method to cache objects. At least one hash table of a circuit comprises a predetermined arrangement that maximizes cache memory space and minimizes a number of cache memory transactions. The circuit handles requests by a remote device to obtain or cache an object. | 10-30-2014 |
20150089285 | CHECKPOINTING USING FPGA - Methods, systems, and computer-readable and executable instructions are provided for checkpointing using a field programmable gate array (FPGA). Checkpointing using FPGA can include checkpointing data within a region of a server's contents to memory and monitoring the checkpointed data using the FPGA. | 03-26-2015 |