Patent application number | Description | Published |
20120231729 | SPS RECEIVER WITH ADJUSTABLE LINEARITY - A satellite positioning system (SPS) receiver that can provide good performance with low power consumption is described. The SPS receiver may be operated in one of multiple modes, which may be associated with different bias current settings for the SPS receiver. One of the modes may be selected based on output power level of a transmitter co-located with the SPS receiver. The bias current of an LNA, a mixer, and/or an LO generator within the SPS receiver may be set based on the selected mode. In one design, a first (e.g., lower power) mode may be selected for the SPS receiver if the transmitter output power level is below a switch point. A second (e.g., high linearity) mode may be selected if the transmitter output power level is above the switch point. The second mode is associated with more bias current for the SPS receiver than the first mode. | 09-13-2012 |
20140028411 | BUFFER INPUT IMPEDANCE COMPENSATION IN A REFERENCE CLOCK SIGNAL BUFFER - A system for managing a reference clock signal includes an XO; a signal buffer coupled to the XO and configured to drive a reference clock signal generated by the XO; and a first IC coupled to the signal buffer. The first IC includes an XO input buffer configured to receive the reference clock signal, to switch between an enabled, operational state and a disabled state, and to have a first operational impedance while in the enabled state; an impedance equivalence circuit configured to be in an enabled, operational state when the XO input buffer is in its disabled state and vice versa and to have a second operational impedance while in the enabled state that is equivalent to the first operational impedance; and a control mechanism configured to switch the XO input buffer and the impedance equivalence circuit between the enabled state and the disabled state. | 01-30-2014 |
20140097905 | SPS RECEIVER WITH ADJUSTABLE LINEARITY - A device includes a low noise amplifier (LNA) for amplifying an input signal, with the LNA including a first transistor configured to receive the input signal, a second transistor configured to receive a bias current and forming a current mirror for the first transistor, and an operational amplifier (op amp) operative to generate a bias voltage for the first and second transistors to match operating points of the first and second transistors. | 04-10-2014 |
20140099885 | SPS RECEIVER WITH ADJUSTABLE LINEARITY - A method of selecting a mode for an SPS receiver includes selecting either a first mode or a second mode for the SPS receiver based on a comparison between an output power of a communications transceiver and a mode switch point wherein the mode switch point is a power value. The first mode corresponds to a first bias current value of the SPS receiver, the second mode corresponds to a second bias current value of the SPS receiver, and the first bias current value is different from the second bias current value. | 04-10-2014 |
20140162570 | RFIC CONFIGURATION FOR REDUCED ANTENNA TRACE LOSS - An RFIC configuration for reduced antenna trace loss is disclosed. In an exemplary embodiment, an apparatus includes a primary RFIC and a secondary RFIC that is configured to receive analog signals from at least two antennas. The secondary RFIC is configured to process selected analog signals received from at least one antenna to generate an analog output that is input to the primary RFIC. | 06-12-2014 |
20150214985 | Tunable Radio Frequency (RF) Front-End Architecture Using Filter Having Adjustable Inductance And Capacitance - A device includes an adjustable capacitance and a switchable inductance coupled to the adjustable capacitance and configured as a tunable resonant circuit, the switchable inductance comprising a tapped structure having a first inductance and a second inductance. | 07-30-2015 |
20150282091 | Method for DSDS/DSDA Idle Power Optimization by Adaptive RF Power Retention and Delta Programming - Various embodiments in the disclosure provide methods implemented by a processor executing on a mobile communication device to dynamically determining whether the power saved by powering down the RF chain between the end of the last reception activities and the beginning of the next reception activities will exceed the power expended to reinitialize the RF chain's components and registers for the next reception activities. Based on this determination, the device processor may configure the RF chain either to power down fully, as in conventional implementations, or to enter a low-power mode in which power is maintained to the power rails supplying the memory registers storing RF communication data, thereby avoiding the power surge of restarting the registers and part of the power drain associated with writing the communication data back into the registers. In some embodiments, the mobile communication device may be a multi-SIM device. | 10-01-2015 |
20150349907 | Reconfigurable Multi-Mode Transceiver - Reconfiguring a transceiver design using a plurality of frequency synthesizers and a plurality of carrier aggregation (CA) receiver (Rx) and transmitter (Tx) chains, the method including: connecting a first frequency synthesizer to a first CA Tx chain; connecting the plurality of frequency synthesizers to the plurality of CA Rx chains, wherein a second frequency synthesizer of the plurality of frequency synthesizers is connected as a shared synthesizer to a first CA Rx chain and a second CA Tx chain. | 12-03-2015 |