Patent application number | Description | Published |
20090083472 | DESIGN STRUCTURE FOR A MEMORY SWITCHING DATA PROCESSING SYSTEM - A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a memory switching data processing system is provided. The memory switching data processing system includes one or more central processing units (‘CPUs’); random access memory organized in at least two banks of memory modules; one or more memory buses providing communications paths for data among the CPUs and the memory modules; and a flexibly configurable memory bus switch comprising a first configuration adapting the first CPU to a first bank of memory modules and a second CPU to a second bank of memory modules and a second configuration adapting the first CPU to both the first bank of memory modules and the second bank of memory modules. | 03-26-2009 |
20090083529 | Memory Switching Data Processing System - A memory switching data processing system including one or more central processing units (‘CPUs’); random access memory organized in at least two banks of memory modules; one or more memory buses providing communications paths for data among the CPUs and the memory modules; and a flexibly configurable memory bus switch comprising a first configuration adapting the first CPU to a first bank of memory modules and a second CPU to a second bank of memory modules and a second configuration adapting the first CPU to both the first bank of memory modules and the second bank of memory modules. | 03-26-2009 |
20090133010 | VIRTUALIZED BLADE FLASH WITH MANAGEMENT MODULE - The invention is directed to providing a virtualized blade flash with a management module in a blade server. A method of configuring a blade server according to an embodiment of the invention includes: providing a plurality of blades, wherein each blade comprising: a service processor; a chip set; an at least one central processing unit (CPU); providing a management module in communication with each of the plurality of blades; and adding a virtual flash store at the management module. | 05-21-2009 |
20090219835 | Optimizing A Physical Data Communications Topology Between A Plurality Of Computing Nodes - Methods, apparatus, and products are disclosed for optimizing a physical data communications topology between a plurality of computing nodes, the physical data communications topology including physical links configured to connect the plurality of nodes for data communications, that include carrying out repeatedly at a predetermined pace: detecting network packets transmitted through the links between each pair of nodes in the physical data communications topology, each network packet characterized by one or more packet attributes; assigning, to each network packet, a packet weight in dependence upon the packet attributes for that network packet; determining, for each pair of nodes in the physical data communications topology, a node pair traffic weight in dependence upon the packet weights assigned to the network packets transferred between that pair of nodes; and reconfiguring the physical links between each pair of nodes in dependence upon the node pair traffic weights. | 09-03-2009 |
20090281761 | Detecting An Increase In Thermal Resistance Of A Heat Sink In A Computer System - Methods, apparatus, and products for detecting an increase in thermal resistance of a heat sink in a computer system, the heat sink dissipating heat for a component of the computer system, the computer system including a fan controlling airflow across the heat sink, the computer system also including a temperature monitoring device, including: measuring, by a monitoring module through use of the temperature monitoring device during operation of the computer system, thermal resistance of the heat sink; determining whether the measured thermal resistance of the heat sink is greater than a threshold thermal resistance, the threshold thermal resistance stored in a thermal profile in non-volatile memory, and if the measured thermal resistance of the heat sink is greater than the threshold thermal resistance, notifying a system administrator. | 11-12-2009 |
20100008376 | METHODS, SYSTEMS AND COMPUTER PROGRAM PRODUCTS FOR PACKET PRIORITIZATION BASED ON DELIVERY TIME EXPECTATION - Methods, systems and computer program products for packet prioritization based on delivery time expectation. Exemplary embodiments include receiving a packet for routing, estimating a TimeToDestination for the packet, the estimating performed by a Internet Control Message Protocol, reading a TimeToDeliver field from each the Internet Protocol Header of the packet to extract data on when the packet needs to be at the destination, determining a MaxQueueDelay for the packet, the MaxQueueDelay calculated by subtracting the TimeToDeliver from the TimeToDestination, passing a lower priority packet if the lower priority packet has a lower MaxQueueDelay, and decrementing the TimeToDeliver by an amount of time the network router has had the packet in the queue before passing the packet to a next router, thereby communicating to the next router how much time is left before the packet must be delivered. | 01-14-2010 |
20120213066 | Optimizing A Physical Data Communications Topology Between A Plurality Of Computing Nodes - Methods, apparatus, and products are disclosed for optimizing a physical data communications topology between a plurality of computing nodes, the physical data communications topology including physical links configured to connect the plurality of nodes for data communications, that include carrying out repeatedly at a predetermined pace: detecting network packets transmitted through the links between each pair of nodes in the physical data communications topology, each network packet characterized by one or more packet attributes; assigning, to each network packet, a packet weight in dependence upon the packet attributes for that network packet; determining, for each pair of nodes in the physical data communications topology, a node pair traffic weight in dependence upon the packet weights assigned to the network packets transferred between that pair of nodes; and reconfiguring the physical links between each pair of nodes in dependence upon the node pair traffic weights. | 08-23-2012 |
20130159809 | Error Detection And Correction Of A Data Transmission - Error detection and correction of a data transmission, including: receiving a block of data, where the block includes a predefined number of words, with each word including a parity bit, where the block of data also an error-correcting code (ECC); determining, for each word in dependence upon the parity bit of the word, whether the word of the block includes a parity error; committing each word that does not include a parity error, if only one word of the block includes a parity error: correcting the one word that includes the parity error through use of the ECC of the block and committing the corrected word. | 06-20-2013 |
20130159810 | Error Detection And Correction Of A Data Transmission - Error detection and correction of a data transmission, including: receiving a block of data, where the block includes a predefined number of words, with each word including a parity bit, where the block of data also an error-correcting code (ECC); determining, for each word in dependence upon the parity bit of the word, whether the word of the block includes a parity error; committing each word that does not include a parity error, if only one word of the block includes a parity error: correcting the one word that includes the parity error through use of the ECC of the block and committing the corrected word. | 06-20-2013 |
20140280539 | Dynamically Managing Social Networking Groups - Methods, apparatuses, and computer program products for dynamically managing social networking groups according to embodiments of the present invention are provided. A particular embodiment includes detecting a predetermined number of user devices within a specified physical area; and in response to detecting the predetermined number of user devices within the specified physical area, creating a social networking group corresponding to the specified physical area. Another embodiment includes detecting a predetermined number of user devices exiting a specified physical area, each user device associated with a user belonging to a social networking group corresponding to the specified physical area; and in response to detecting the predetermined number of user devices exiting the specified physical area, destroying the social networking group after a duration following the detection of the predetermined number of users of the social networking group exiting the specified physical area. | 09-18-2014 |
20140280544 | Dynamically Managing Social Networking Groups - Methods, apparatuses, and computer program products for dynamically managing social networking groups according to embodiments of the present invention are provided. A particular embodiment includes detecting a predetermined number of user devices within a specified physical area; and in response to detecting the predetermined number of user devices within the specified physical area, creating a social networking group corresponding to the specified physical area. Another embodiment includes detecting a predetermined number of user devices exiting a specified physical area, each user device associated with a user belonging to a social networking group corresponding to the specified physical area; and in response to detecting the predetermined number of user devices exiting the specified physical area, destroying the social networking group after a duration following the detection of the predetermined number of users of the social networking group exiting the specified physical area. | 09-18-2014 |
20150056838 | CABLE CONNECTOR - Embodiments provide for a cable connector for coupling a cable with a device having a mating connector. The cable connector includes a cable connector body having a device end, a cable end, a bottom side, and a pivot point on the bottom side between the device and cable ends. Also, the cable connector includes a strut having a first strut end pivotally coupled with the pivot point and a second strut end. The strut is operable to rotate between a retracted position and an actuated position. The second strut end is adapted to engage the device on a surface of the device below the mating connector in the actuated position. | 02-26-2015 |
Patent application number | Description | Published |
20090016019 | AIRFLOW CONTROL AND DUST REMOVAL FOR ELECTRONIC SYSTEMS - Airflow control and dust removal systems and methods are disclosed. In one embodiment, a plurality of blade servers is mounted in a chassis. A blower generates airflow through the chassis. Air enters the chassis uniformly across the blade servers and flows in parallel through the servers. An airflow directing mechanism is provided for allowing airflow through a selected one of the blade servers while reducing or closing airflow to the other blade servers, to individually clean and remove dust from the selected blade server. The airflow directing mechanism may include a movable vane actuated by a rotary or linear solenoid to selectively block airflow ports of the servers. The vane may be held in a closed position, assisted by an electromagnet. The airflow directing mechanism may alternatively comprise a rolled shade having a pattern of openings. The position of the rolled shade may be controlled to align openings in the shade with airflow ports in the servers, to control which servers airflow may pass through. | 01-15-2009 |
20090021270 | CAPACITIVE DETECTION OF DUST ACCUMULATION IN A HEAT SINK - A system and method for electronically detecting the accumulation of dust within a computer system using a capacitive dust sensor. The dust detection system may be implemented on a smaller computer, such as an individual PC, or in a more expansive system, such as a rack-based server system (“rack system”) having multiple servers and other hardware devices. In one embodiment, each server in a rack system includes a capacitive sensor responsive to the accumulation of dust. The capacitive sensor may include one or more capacitive plates integral with a heatsink. As dust collects on the capacitive plates, the capacitance increases. When a capacitance setpoint is reached, indicating the dust has reached a critical level, an alert is generated. The alerts may be received by a management console for the attention of a system administrator. Each alert may contain the identity of the server generating the alert, so that the system administrator knows which server(s) are to be removed for cleaning. | 01-22-2009 |
20090045967 | CAPACITIVE DETECTION OF DUST ACCUMULATION USING MICROCONTROLLER COMPONENT LEADS - A system and method are used for electronically detecting the accumulation of dust within a computer system using a capacitive dust sensor. The dust detection system may be implemented on a smaller computer, such as an individual PC, or in a more expansive system, such as a rack-based server system (“rack system”) having multiple servers and other hardware devices. In one embodiment, each server in a rack system includes a capacitive sensor responsive to the accumulation of dust. The capacitive sensor may include one or more capacitive plates integral with a heatsink. As dust collects on the capacitive plates, the capacitance increases. When a capacitance setpoint is reached, indicating the dust has reached a critical level, an alert is generated. The alerts may be received by a management console for the attention of a system administrator. Each alert may contain the identity of the server generating the alert, so that the system administrator knows which server(s) are to be removed for cleaning. | 02-19-2009 |
20090088008 | METHOD FOR HORIZONTAL INSTALLATION OF LGA SOCKETED CHIPS - Method and apparatus for installing a processor into electronic communication with a socket. The land grid array socket connector includes a socket housing secured to a circuit board and an array of upwardly extending pins for electronic communication with contact pads on the processor. The socket connector provides a carriage configured to receiving the processor through a lateral opening and support a perimeter edge of the processor. A mechanical linkage couples the carriage and the socket housing for substantially vertically translating the processor relative to the socket. A plurality of alignment features upwardly extends from the socket housing along the perimeter of the array of pins. Each of the alignment features has an inwardly-facing tapered surface for registering the edge of the processor and biasing the processor into a position where the array of contact pads are aligned with the array of pins as the processor is lowered. | 04-02-2009 |
20090234936 | Dual-Band Communication Of Management Traffic In A Blade Server System - In one embodiment, a communication system for a multi-blade server system includes a multi-drop serial bus network interconnecting a management module with each of a plurality of servers in a multi-server chassis. A first transceiver subsystem is configured for communicating over the serial bus network between the management module and each server within a first frequency band. A second transceiver subsystem is configured for simultaneously communicating over the serial bus network between the management module and the servers within a second frequency band higher than the first frequency band. A first signal-filtering subsystem substantially filters out signals in the second frequency band from the first transceiver subsystem. A second signal-filtering subsystem substantially filters out the signals in the first frequency band from the second transceiver subsystem. | 09-17-2009 |
Patent application number | Description | Published |
20100032766 | Bipolar Junction Transistor with a Reduced Collector-Substrate Capacitance - A process for forming a bipolar junction transistor (BJT) in a semiconductor substrate and a BJT formed according to the process. A buried isolation region is formed underlying BJT structures to isolate the BJT structures from the p-type semi-conductor substrate. To reduce capacitance between a BJT subcollector and the buried isolation region, prior to implanting the subcollector spaced-apart structures are formed on a surface of the substrate. The subcollector is formed by implanting ions through the spaced-apart structures and through a region intermediate the spaced-apart structures. The formed BJT subcollector therefore comprises a body portion and end portions extending therefrom, with the end portions disposed at a shallower depth than the body portion, since the ions implanting the end portions must pass through the spaced-apart structures. The shallower depth of the end portions reduces the capacitance. | 02-11-2010 |
20120139363 | RECONFIGURABLE RF SWITCH DIE - A radio frequency (RF) switch die which includes an antenna port, a plurality of RF ports, a switch fabric for selectively coupling one or more of the RF ports to the antenna port, and control circuitry that is adapted to, in a first mode, direct the switch fabric to couple any one of the plurality of RF ports individually to the antenna port, and in a second mode, couple a selected group of the RF ports to the antenna port. The RF switch die may include M number of RF ports, and be relatively easily reconfigured to provide N number of RF ports, wherein N is less than M. Groups of RF ports may be coupled together to form coupled RF ports that offer different electrical characteristics than non-coupled RF ports. | 06-07-2012 |
20120238230 | RF SYSTEM FOR REDUCING INTERMODULATION (IM) PRODUCTS - An RF system for reducing intermodulation (IM) products is disclosed. The RF system includes a first nonlinear element and a second nonlinear element, wherein the second nonlinear element generates inherent IM products and the first nonlinear element is adapted to generate compensating IM products. Alternatively, the first nonlinear element generates inherent IM products and the second nonlinear element is adapted to generate compensating IM products. The amplitudes of the compensating IM products are substantially equal to amplitudes of the inherent IM products. The RF system further includes a phase shifter that is adapted to provide a phase shift that results in around 180° of phase shift between the inherent IM products and the compensating IM products. The phase shifter is coupled between the first nonlinear element and the second nonlinear element. | 09-20-2012 |
20140210436 | LOW NOISE RADIO FREQUENCY SWITCHING CIRCUITRY - Radio frequency (RF) switching circuitry includes support circuitry for maintaining one or more RF switching elements in either an ON or OFF state. The support circuitry includes a negative charge pump adapted to quickly generate a negative voltage during a “boost” mode of operation, and maintain the negative voltage during a normal mode of operation. The negative charge pump includes an oscillator adapted to generate a high frequency oscillating signal for driving the charge pump during the boost mode of operation and a low frequency oscillating signal for driving the charge pump during the normal mode of operation. By generating the high frequency oscillating signal only during a boost mode of operation, spurious noise coupled to the RF switch circuitry is minimized during a normal mode of operation. | 07-31-2014 |
20140220911 | DEDICATED SHUNT SWITCH WITH IMPROVED GROUND - Antenna tuning switch circuitry includes an input port, a shunt switch, control circuitry, and an integrated ground. The shunt switch is coupled between the input port and the integrated ground. The control circuitry includes a control signal input port, a switch driver output port coupled to the shunt switch, and a ground connection port coupled to the integrated ground. The shunt switches, the RF input ports, the control circuitry, and the integrated ground are monolithically integrated on a single semiconductor die. The antenna tuning switch circuitry is adapted to selectively couple the input port to the integrated ground in order to alter one or more operating parameters of an attached antenna. By monolithically integrating the shunt switch together with the control circuitry and the integrated ground, the ON state impedance and the parasitic OFF state impedance of the antenna tuning switch circuitry can be significantly improved. | 08-07-2014 |
20140242760 | SEMICONDUCTOR RADIO FREQUENCY SWITCH WITH BODY CONTACT - The present disclosure relates to a radio frequency (RF) switch that includes multiple body-contacted field effect transistor (FET) elements coupled in series. The FET elements may be formed using a thin-film semiconductor device layer, which is part of a thin-film semiconductor die. Conduction paths between the FET elements through the thin-film semiconductor device layer and through a substrate of the thin-film semiconductor die may be substantially eliminated by using insulating materials. Elimination of the conduction paths allows an RF signal across the RF switch to be divided across the series coupled FET elements, such that each FET element is subjected to only a portion of the RF signal. Further, each FET element is body-contacted and may receive reverse body biasing when the RF switch is in an OFF state, thereby reducing an OFF state drain-to-source capacitance of each FET element. | 08-28-2014 |
20140252566 | SILICON-ON-DUAL PLASTIC (SODP) TECHNOLOGY AND METHODS OF MANUFACTURING THE SAME - A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a semiconductor stack structure having a first surface and a second surface. A first polymer having a high thermal conductivity and a high electrical resistivity is disposed on the first surface of the semiconductor stack structure. An exemplary method includes providing the semiconductor stack structure with the second surface in direct contact with a wafer handle. A next step involves removing the wafer handle to expose the second surface of the semiconductor stack structure. A following step includes disposing a second polymer having high thermal conductivity and high electrical resistivity directly onto the second surface of the semiconductor stack structure. Additional methods apply silicon nitride layers on the first surface and second surface of the semiconductor stack structure before disposing the first polymer and second polymer to realize the semiconductor device. | 09-11-2014 |
20140252567 | PATTERNED SILICON-ON-PLASTIC (SOP) TECHNOLOGY AND METHODS OF MANUFACTURING THE SAME - A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a semiconductor stack structure attached to a wafer handle having at least one aperture that extends through the wafer handle to an exposed portion of the semiconductor stack structure. A thermally conductive and electrically resistive polymer substantially fills the at least one aperture and contacts the exposed portion of the semiconductor stack structure. One method for manufacturing the semiconductor device includes forming patterned apertures in the wafer handle to expose a portion of the semiconductor stack structure. The patterned apertures may or may not be aligned with sections of RF circuitry making up the semiconductor stack structure. A following step includes contacting the exposed portion of the semiconductor stack structure with a polymer and substantially filling the patterned apertures with the polymer, wherein the polymer is thermally conductive and electrically resistive. | 09-11-2014 |
20140266415 | HARMONIC CANCELLATION CIRCUIT FOR AN RF SWITCH BRANCH - Disclosed is a harmonic cancellation circuit for an RF switch branch having a first transistor with a first gate terminal and a first body terminal, a second transistor having a second gate terminal coupled to the first body terminal, and having a second body terminal coupled to the first gate terminal. Also included is a first resistor coupled between a first coupling node and the second body terminal, and a second resistor coupled between a second coupling node and the first body terminal, wherein the first transistor and second transistor are adapted to generate an inverse phase third harmonic signal relative to a third harmonic signal generated by the RF switch branch, such that the inverse phase third harmonic signal is output through the first resistor and the second resistor to the RF switch branch to reduce the third harmonic signal. | 09-18-2014 |
20140306324 | SEMICONDUCTOR DEVICE WITH A POLYMER SUBSTRATE AND METHODS OF MANUFACTURING THE SAME - A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a semiconductor stack structure having a first surface and a second surface. A polymer substrate having a high thermal conductivity and a high electrical resistivity is disposed onto the first surface of the semiconductor stack structure. One method includes providing the semiconductor stack structure with the first surface in direct contact with a wafer handle. A next step involves removing the wafer handle to expose the first surface of the semiconductor stack structure. A following step includes disposing a polymer substrate having high thermal conductivity and high electrical resistivity directly onto the first surface of the semiconductor stack structure. | 10-16-2014 |
20140335801 | TECHNIQUE TO REDUCE THE THIRD HARMONIC OF AN ON-STATE RF SWITCH - RF switching circuitry includes an RF switch coupled between an input node and an output node. Distortion compensation circuitry is coupled in parallel with the RF switch between the input node and the output node. The RF switch is configured to selectively pass an RF signal from the input node to the output node based on a first switching control signal. The distortion compensation circuitry is configured to boost a portion of the RF signal that is being compressed by the RF switch when the amplitude of the RF signal is above a predetermined threshold by selectively injecting current into one of the input node or the output node. Boosting a portion of the RF signal that is being compressed by the RF switch allows a signal passing through the RF switch to remain substantially linear, thereby improving the performance of the RF switching circuitry. | 11-13-2014 |
20140361839 | NONLINEAR CAPACITANCE LINEARIZATION - An apparatus, which includes a first electronic device, a first nonlinear capacitance compensation circuit, and a capacitance compensation control circuit, is disclosed. The first electronic device has a first nonlinear capacitance and is coupled to the first nonlinear capacitance compensation circuit, which has a first compensation capacitance and receives a first compensation control signal. The capacitance compensation control circuit adjusts the first compensation capacitance using the first compensation control signal to at least partially linearize the first nonlinear capacitance. | 12-11-2014 |
20150054698 | ANTENNA TUNING CIRCUITRY WITH REDUCED INTERFERENCE - Antenna tuning circuitry includes an antenna tuning node, an antenna tuning switch, and a resonant tuning circuit. The antenna tuning node is coupled to a resonant conduction element of an antenna. The antenna tuning switch and the resonant tuning circuit are coupled in series between the antenna tuning switch and the antenna tuning node, such that the resonant tuning circuit is between the antenna tuning node and the antenna tuning switch. The resonant tuning circuit is configured to resonate at one or more harmonic frequencies generated by the antenna tuning switch such that a high impedance path is formed between the antenna tuning switch and the antenna tuning node at harmonic frequencies generated by the antenna tuning switch. Accordingly, harmonic interference generated by the antenna tuning switch is prevented from reaching the antenna, while simultaneously allowing for tuning of the antenna. | 02-26-2015 |