Patent application number | Description | Published |
20090137981 | METHODS OF TREATING A BLOOD VESSEL - Described herein are methods for treating a blood vessel. In an embodiment, the method of treating a blood vessel comprises providing at least one manipulable tool in a blood vessel, depositing a non-solid polymerizable material into a deposition area of the vessel, wherein the polymerizable liquid hardens over time upon contact with blood in the blood vessel, and altering the shape of the polymerizable material while it hardens by manipulating the tool. | 05-28-2009 |
20090246262 | EASILY APPLIED FIELD DRESSING FOR WOUNDS - A method for treating wounds by adhering a wound dressing to a wound with a polymerizable alkyl cyanoacrylate composition, such that the wound dressing and cyanoacrylate composition seal the wound to inhibit bleeding and infection. The dressing may be in the form of a mitten. Also disclosed is injection of polymerizable cyanoacrylate into puncture wounds to seal the wounds and inhibit bleeding. | 10-01-2009 |
20090257976 | SINGLE VIAL FORMULATION FOR MEDICAL GRADE CYANOACRYLATE - Alkyl cyanoacrylate compositions and methods for making those compositions, utilizing high purity monomeric starting materials, formed into more viscous oligomers, and combined with a plasticizer and inhibitor to provide a single-container, storage stable medical cyanoacrylate. | 10-15-2009 |
20100152828 | DEVICES AND METHODS FOR ACCESSING AND TREATING AN ANEURYSM - Devices for treating aneurysms are disclosed. The devices are adapted and configured to modify blood flow at the aneurysm. More specifically, the invention discloses devices for treating cerebral aneurysms using devices adapted and configured to be delivered to a blood vessel in the brain on a distal tip of a microcatheter. The aneurysm devices comprise: a device adapted to be delivered to a blood vessel aneurysm on a distal tip of a catheter and further adapted to modify blood flow at the aneurysm. | 06-17-2010 |
20120191129 | Emergency wound treatment device and method - An emergency medical device and method is provided for treatment of open wounds by enhancing clotting and arresting hemorrhaging, particularly in the area of the neck, abdomen, chest or groin. The devices includes an elongated delivery tube for insertion into a wound cavity and subsequent delivery of a space filling, sponge-like mass containing a polymerizable liquid sealant that polymerizes upon contact with body fluids after which the delivery tube is removed. | 07-26-2012 |
20130089505 | SINGLE VIAL FORMULATION FOR MEDICAL GRADE CYANOACRYLATE - Alkyl cyanoacrylate compositions and methods for making those compositions, utilizing high purity monomeric starting materials, formed into more viscous oligomers, and combined with a plasticizer and inhibitor to provide a single-container, storage stable medical cyanoacrylate. | 04-11-2013 |
Patent application number | Description | Published |
20120197797 | PENDING ATM TRANSACTIONS - In general terms, embodiments of the present invention relate to methods and apparatuses for initiating pending ATM transactions on a mobile device and for completing those pending ATM transactions at an ATM. For example, in some embodiments, a method is provided that includes: (a) initiating a pending ATM transaction on a mobile device, where the initiating the pending ATM transaction is based at least partially on a user of the mobile device inputting one or more inputs into the mobile device, and where the initiating the pending ATM transaction occurs before the user arrives at an ATM for completing the pending ATM transaction; (b) storing, on the mobile device, transaction information associated with the pending ATM transaction; (c) transferring the transaction information from the mobile device directly to the ATM, where the transferring the transaction information occurs after the user arrives at the ATM for completing the pending ATM transaction; (d) receiving, at the ATM, the transaction information associated with the pending ATM transaction; and (e) completing, at the ATM, the pending ATM transaction based at least partially on the transaction information. | 08-02-2012 |
20120197798 | PENDING ATM AUTHENTICATIONS - In general terms, embodiments of the present invention relate to methods and apparatuses for initiating pending ATM authentications on a mobile device and for completing those pending ATM authentications at an ATM. For example, in some embodiments, a method is provided that includes: (a) initiating a pending ATM authentication on a mobile device, where the initiating the pending ATM authentication is based at least partially on a user of the mobile device inputting one or more inputs into the mobile device, and where the initiating the pending ATM authentication occurs before the user arrives at an ATM for completing the pending ATM authentication; (b) storing, on the mobile device, authentication information associated with the pending ATM authentication; (c) transferring the authentication information from the mobile device directly to the ATM, where the transferring the authentication information occurs after the user arrives at the ATM for completing the pending ATM authentication; (d) receiving, at the ATM, the authentication information associated with the pending ATM authentication; and (e) completing, at the ATM, the pending ATM authentication based at least partially on the authentication information. | 08-02-2012 |
20130005253 | PENDING ATM TRANSACTIONS - Embodiments of the present invention relate to methods and apparatuses for initiating pending ATM transactions on a mobile device and for completing those pending ATM transactions at an ATM. In some embodiments, a method is provided that includes: (a) initiating, by a user, a pending ATM transaction on a mobile device, where the initiating the pending ATM transaction occurs before the user arrives at an ATM for completing the pending ATM transaction; (b) storing, on the mobile device, transaction information associated with the pending ATM transaction; (c) transferring the transaction information from the mobile device directly to the ATM, where the transferring the transaction information occurs after the user arrives at the ATM for completing the pending ATM transaction; (d) receiving, at the ATM, the transaction information associated with the pending ATM transaction; and (e) completing, at the ATM, the pending ATM transaction based on the transaction information. | 01-03-2013 |
Patent application number | Description | Published |
20130069171 | Controlled Fin-Merging for Fin Type FET Devices - A placement of non-planar FET devices is disclosed, which includes non-planar devices that have electrodes, and the electrodes contain fins and an epitaxial layer which merges the fins together. The non-planar devices are so placed that their gate structures are in a parallel configuration separated from one another by a first distance, and the fins of differing non-planar devices line up in essentially straight lines. The electrodes of differing FET devices are separated from one another by a cut defined by opposing facets of the electrodes, with the opposing facets also defining the width of the cut. The width of the cut is smaller than one fifth of the first distance which separates the gate structures. | 03-21-2013 |
20140103455 | FET Devices with Oxide Spacers - Transistors including oxide spacers and methods of forming the same. Embodiments include planar FETs including a gate on a semiconductor substrate, oxide spacers on the gate sidewalls, and source or drain regions at least partially in the substrate offset from the gate by the oxide spacers. Other embodiments include finFETs including a fin on an insulator layer, a gate formed over the fin, a first source or drain region on a first end of the fin, a second source or drain region on a second end of the fin, and oxide spacers on the gate sidewalls separating the first source or drain region and the second source or drain from the gate. Embodiments further include methods of forming transistors with oxide spacers including forming a transistor including sacrificial spacers, removing the sacrificial spacers to form recess regions, and forming oxide spacers in the recess regions. | 04-17-2014 |
20140151803 | Inducing Channel Stress in Semiconductor-on-Insulator Devices by Base Substrate Oxidation - Embodiments include semiconductor-on-insulator (SOI) substrates having SOI layers strained by oxidation of the base substrate layer and methods of forming the same. The method may include forming a strained channel region in a semiconductor-on-insulator (SOI) substrate including a buried insulator (BOX) layer above a base substrate layer and a SOI layer above the BOX layer by first etching the SOI layer and the BOX layer to form a first isolation recess region and a second isolation recess region. A portion of the SOI layer between the first isolation recess region and the second isolation recess region defines a channel region in the SOI layer. A portion of the base substrate layer below the first isolation recess region and below the second isolation recess region may then be oxidized to form a first oxide region and a second oxide region, respectively, that apply compressive strain to the channel region. | 06-05-2014 |
20140206181 | THREE DIMENSIONAL FET DEVICES HAVING DIFFERENT DEVICE WIDTHS - A method of manufacturing a three dimensional FET device structure includes: providing a substrate having a semiconductor layer on an insulator layer; forming three dimensional fins in the semiconductor layer; applying a masking material to a first fin while exposing a second fin; applying a hydrogen atmosphere to the substrate and exposed second fin, the hydrogen atmosphere causing the exposed second fin to reflow and change shape; removing the masking material from the first fin; and forming a gate to wrap around each of the first and second fins. The first and second fins are formed having a device width such that the first fin having a first device width and a second fin having a second device width with the first device width being different than the second device width. | 07-24-2014 |
20140278296 | SELECTIVE IMPORTANCE SAMPLING - The present disclosure relates generally to the field of selective importance sampling. In various examples, selective importance sampling may be implemented in the form of methods and/or algorithms. | 09-18-2014 |
20140278309 | SELECTIVE IMPORTANCE SAMPLING - The present disclosure relates generally to the field of selective importance sampling. In various examples, selective importance sampling may be implemented in the form of systems and/or algorithms. | 09-18-2014 |
20140361338 | REDUCED RESISTANCE SiGe FinFET DEVICES AND METHOD OF FORMING SAME - A method for forming a fin field-effect transistor (FinFET) device, comprises forming a plurality of silicon fins on a substrate, depositing silicon germanium (SiGe) on the plurality of fins, forming a gate region by forming a dummy gate stack on a predetermined area of the fins including the SiGe, removing the SiGe from an area of the fins not covered by the dummy gate stack, forming a merged region in the area of the fins not covered by the dummy gate stack to form a source drain region, removing the dummy gate stack to expose the remaining SiGe in the gate region, mixing the SiGe with the silicon fins in the gate region to form SiGe fins, and depositing a gate dielectric and gate metal on the SiGe fins. | 12-11-2014 |
20140361368 | REDUCED RESISTANCE SiGe FinFET DEVICES AND METHOD OF FORMING SAME - A method for forming a fin field-effect transistor (FinFET) device, comprises forming a plurality of silicon fins on a substrate, depositing silicon germanium (SiGe) on the plurality of fins, forming a gate region by forming a dummy gate stack on a predetermined area of the fins including the SiGe, removing the SiGe from an area of the fins not covered by the dummy gate stack, forming a merged region in the area of the fins not covered by the dummy gate stack to form a source drain region, removing the dummy gate stack to expose the remaining SiGe in the gate region, mixing the SiGe with the silicon fins in the gate region to form SiGe fins, and depositing a gate dielectric and gate metal on the SiGe fins. | 12-11-2014 |
20150064853 | INTEGRATED CIRCUIT INCLUDING DRAM AND SRAM/LOGIC - An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region. | 03-05-2015 |
20150069527 | FINFET DEVICE HAVING A MERGED SOURCE DRAIN REGION UNDER CONTACT AREAS AND UNMERGED FINS BETWEEN CONTACT AREAS, AND A METHOD OF MANUFACTURING SAME - A method for manufacturing a fin field-effect transistor (FinFET) device, comprises forming a plurality of fins on a substrate, forming a plurality of gate regions on portions of the fins, wherein the gate regions are spaced apart from each other, forming spacers on each respective gate region, epitaxially growing a first epitaxy region on each of the fins, stopping growth of the first epitaxy regions prior to merging of the first epitaxy regions between adjacent fins, forming a dielectric layer on the substrate including the fins and first epitaxy regions, removing the dielectric layer and first epitaxy regions from the fins at one or more portions between adjacent gate regions to form one or more contact area trenches, and epitaxially growing a second epitaxy region on each of the fins in the one or more contact area trenches, wherein the second epitaxy regions on adjacent fins merge with each other. | 03-12-2015 |
20150129982 | FinFET DEVICE INCLUDING FINS HAVING A SMALLER THICKNESS IN A CHANNEL REGION, AND A METHOD OF MANUFACTURING SAME - A method for manufacturing a fin field-effect transistor (FinFET) device, comprises forming a plurality of fins on a substrate to a first thickness, forming a sacrificial gate stack on portions of the fins, forming source drain junctions using ion implantation, forming a dielectric layer on the substrate, removing the sacrificial gate stack to expose the portions of the fins, thinning the exposed portions of the fins to a second thickness less than the first thickness, and forming a gate stack on the thinned exposed portions of the fins to replace the removed sacrificial gate stack. | 05-14-2015 |
20150179789 | FinFET DEVICE HAVING A MERGE SOURCE DRAIN REGION UNDER CONTACT AREAS AND UNMERGED FINS BETWEEN CONTACT AREAS, AND A METHOD OF MANUFACTURING SAME - A method for manufacturing a fin field-effect transistor (FinFET) device, comprises forming a plurality of fins on a substrate, forming a plurality of gate regions on portions of the fins, wherein the gate regions are spaced apart from each other, forming spacers on each respective gate region, epitaxially growing a first epitaxy region on each of the fins, stopping growth of the first epitaxy regions prior to merging of the first epitaxy regions between adjacent fins, forming a dielectric layer on the substrate including the fins and first epitaxy regions, removing the dielectric layer and first epitaxy regions from the fins at one or more portions between adjacent gate regions to form one or more contact area trenches, and epitaxially growing a second epitaxy region on each of the fins in the one or more contact area trenches, wherein the second epitaxy regions on adjacent fins merge with each other. | 06-25-2015 |
20150206953 | METHOD AND STRUCTURE TO ENHANCE GATE INDUCED STRAIN EFFECT IN MULTIGATE DEVICE - A FinFet formed by depositing a thin layer of polycrystalline silicon followed by depositing a stress containing material, including a high Ge percentage silicon germanium film and/or a high stress W film on top of a polycrystalline silicon film. Freeing space between fins allows stressor films to be deposited closer to the transistor channel, improving the proximity of the stress containing material to the transistor channel and enhancing the stress coupling efficiency by defining a ratio between stress level in the stressor film and stress transferred to the channel for a mobility enhancement. The stress level is enhanced by patterning by removing the n-type workfunction metal from the p-FinFET. After stripping off the soft or hard mask, the p-type workfunction metal is deposited in the n- and p-FinFET regions. The freed space specifically for p-FinFet between the fins achieves an even higher stressor coupling to further boost the carrier mobility. | 07-23-2015 |
20150228489 | MOSFET WITH WORK FUNCTION ADJUSTED METAL BACKGATE - An SOI substrate, a semiconductor device, and a method of backgate work function tuning. The substrate and the device have a plurality of metal backgate regions wherein at least two regions have different work functions. The method includes forming a mask on a substrate and implanting a metal backgate interposed between a buried oxide and bulk regions of the substrate thereby producing at least two metal backgate regions having different doses of impurity and different work functions. The work function regions can be aligned such that each transistor has different threshold voltage. When a top gate electrode serves as the mask, a metal backgate with a first work function under the channel region and a second work function under the source/drain regions is formed. The implant can be tilted to shift the work function regions relative to the mask. | 08-13-2015 |
20150236021 | Structure to Enhance Gate Induced Strain Effect in Multigate Devices - A FinFet device structure provided with a thin layer of polycrystalline silicon having stress containing material, including a high Ge percentage silicon germanium film and/or a high stress W film on top of a polycrystalline silicon film. Space between the fins enables the stressor films to be positioned closer to the transistor channel. The improved proximity of the stress containing material to the transistor channel and the enhanced stress couple the efficiency defines a ratio between the stress level in the stressor film and stress transfer to the channel for mobility enhancement. The stress level is further enhanced by patterning by removal of the n-type workfunction metal from the p-FinFET. Following the stripping off the soft or hard mask, the p-type workfunction metal ends positioned in the n- and p-FinFET regions. The freed space specifically for p-FinFet between the fins achieves an even higher stressor coupling to further boost the carrier mobility. | 08-20-2015 |
20150263041 | MOSFET WITH WORK FUNCTION ADJUSTED METAL BACKGATE - An SOI substrate, a semiconductor device, and a method of backgate work function tuning. The substrate and the device have a plurality of metal backgate regions wherein at least two regions have different work functions. The method includes forming a mask on a substrate and implanting a metal backgate interposed between a buried oxide and bulk regions of the substrate thereby producing at least two metal backgate regions having different doses of impurity and different work functions. The work function regions can be aligned such that each transistor has different threshold voltage. When a top gate electrode serves as the mask, a metal backgate with a first work function under the channel region and a second work function under the source/drain regions is formed. The implant can be tilted to shift the work function regions relative to the mask. | 09-17-2015 |
20150287743 | MULTI-HEIGHT FIN FIELD EFFECT TRANSISTORS - Semiconductor fins are formed on a top surface of a substrate. A dielectric material is deposited on the top surfaces of the semiconductor fins and the substrate by an anisotropic deposition. A dielectric material layer on the top surface of the substrate is patterned so that the remaining portion of the dielectric material layer laterally surrounds each bottom portion of at least one semiconductor fin, while not contacting at least one second semiconductor fin. Dielectric material portions on the top surfaces of the semiconductor fins may be optionally removed. Each first semiconductor fin has a lesser channel height than the at least one second semiconductor fin. The first and second semiconductor fins can be employed to provide fin field effect transistors having different channel heights. | 10-08-2015 |
20150287809 | MULTI-HEIGHT FIN FIELD EFFECT TRANSISTORS - Semiconductor fins are formed on a top surface of a substrate. A dielectric material is deposited on the top surfaces of the semiconductor fins and the substrate by an anisotropic deposition. A dielectric material layer on the top surface of the substrate is patterned so that the remaining portion of the dielectric material layer laterally surrounds each bottom portion of at least one semiconductor fin, while not contacting at least one second semiconductor fin. Dielectric material portions on the top surfaces of the semiconductor fins may be optionally removed. Each first semiconductor fin has a lesser channel height than the at least one second semiconductor fin. The first and second semiconductor fins can be employed to provide fin field effect transistors having different channel heights. | 10-08-2015 |
20150287810 | SiGe FINFET WITH IMPROVED JUNCTION DOPING CONTROL - A semiconductor device and a method for fabricating the device. The method includes: providing a FinFET having a source/drain region, at least one SiGe fin, a silicon substrate, a local oxide layer is formed on the silicon substrate, a gate structure is formed on the at least one SiGe fin and the local oxide layer, the gate structure is encapsulated by a gate hard mask and sidewall spacer layers; recessing the at least one SiGe fin in the source/drain region to the sidewall spacer layers and the silicon substrate layer; recessing the local oxide layer in the source/drain region to the sidewall spacer layer and the silicon substrate; growing a n-doped silicon layer on the silicon substrate; growing a p-doped silicon layer or p-doped SiGe layer on the n-doped silicon layer; and forming a silicide layer on the p-doped silicon layer or p-doped SiGe layer. | 10-08-2015 |
20150303281 | FINFET DEVICE WITH VERTICAL SILICIDE ON RECESSED SOURCE/DRAIN EPITAXY REGIONS - A method of forming a semiconductor device that includes forming a fin structure from a semiconductor substrate, and forming a gate structure on a channel region portion of the fin structure. A source region and a drain region are formed on a source region portion and a drain region portion of the fin structure on opposing sides of the channel portion of the fin structure. At least one sidewall of the source region portion and the drain region portion of the fin structure is exposed. A metal semiconductor alloy is formed on the at least one sidewall of the source region portion and the drain region portion of the fin structure that is exposed. | 10-22-2015 |
20150318218 | SEMICONDUCTOR DEVICE INCLUDING GATE CHANNEL HAVING ADJUSTED THRESHOLD VOLTAGE - A semiconductor device includes at least one first semiconductor fin formed on an nFET region of a semiconductor device and at least one second semiconductor fin formed on a pFET region. The at least one first semiconductor fin has an nFET channel region interposed between a pair of nFET source/drain regions. The at least one second semiconductor fin has a pFET channel region interposed between a pair of pFET source/drain regions. The an epitaxial liner is formed on only the pFET channel region of the at least one second semiconductor fin such that a first threshold voltage of the nFET channel region is different than a second threshold voltage of the pFET channel. | 11-05-2015 |
20150318307 | SEMICONDUCTOR DEVICE INCLUDING GATE CHANNEL HAVING ADJUSTED THRESHOLD VOLTAGE - A semiconductor device includes at least one first semiconductor fin formed on an nFET region of a semiconductor device and at least one second semiconductor fin formed on a pFET region. The at least one first semiconductor fin has an nFET channel region interposed between a pair of nFET source/drain regions. The at least one second semiconductor fin has a pFET channel region interposed between a pair of pFET source/drain regions. The an epitaxial liner is formed on only the pFET channel region of the at least one second semiconductor fin such that a first threshold voltage of the nFET channel region is different than a second threshold voltage of the pFET channel. | 11-05-2015 |
20160079419 | STRAINED SEMICONDUCTOR TRAMPOLINE - A method of forming a strained trampoline including: forming a strain inducing layer on a semiconductor-on-insulator (SOI), the SOI having a semiconductor layer on an insulator layer and the insulator layer is on a handle substrate; forming a opening through the semiconductor layer and the insulator layer using a patterned hardmask; forming a trampoline support in the opening; forming a trench through the strain inducing layer and through the semiconductor layer exposing a portion of the insulator layer, a strained trampoline is a portion of the semiconductor layer with a boundary defined by the trampoline support and the trench; and removing the insulator layer through the trench, where the strained trampoline is supported by the trampoline support. | 03-17-2016 |
20160111340 | SEMICONDUCTOR DEVICE INCLUDING GATE CHANNEL HAVING ADJUSTED THRESHOLD VOLTAGE - A semiconductor device includes at least one first semiconductor fin formed on an nFET region of a semiconductor device and at least one second semiconductor fin formed on a pFET region. The at least one first semiconductor fin has an nFET channel region interposed between a pair of nFET source/drain regions. The at least one second semiconductor fin has a pFET channel region interposed between a pair of pFET source/drain regions. The an epitaxial liner is formed on only the pFET channel region of the at least one second semiconductor fin such that a first threshold voltage of the nFET channel region is different than a second threshold voltage of the pFET channel. | 04-21-2016 |