Patent application number | Description | Published |
20080217144 | Impact sensing switch - An impact switch includes a housing having a wall including at least two electrically conductive contact elements spaced apart from one another. The switch includes an inertial body having a conductive surface disposed in a tapered aperture and electrically connecting the contact elements to one another in a switch closed condition. An impact switch for rapidly firing an explosive device is provided. | 09-11-2008 |
20080246136 | Chips having rear contacts connected by through vias to front contacts - A microelectronic unit is provided in which front and rear surfaces of a semiconductor element may define a thin region which has a first thickness and a thicker region having a thickness at least about twice the first thickness. A semiconductor device may be present at the front surface, with a plurality of first conductive contacts at the front surface connected to the device. A plurality of conductive vias may extend from the rear surface through the thin region of the semiconductor element to the first conductive contacts. A plurality of second conductive contacts can be exposed at an exterior of the semiconductor element. A plurality of conductive traces may connect the second conductive contacts to the conductive vias. | 10-09-2008 |
20080277775 | Ultra-thin near-hermetic package based on rainier - A microelectronic package including a dielectric layer having top and bottom surfaces, the dielectric layer having terminals exposed at the bottom surface; a metallic wall bonded to the dielectric layer and projecting upwardly from the top surface of the dielectric layer and surrounding a region of the top surface; a metallic lid bonded to the wall and extending over the region of the top surface so that the lid, the wall and the dielectric layer cooperatively define an enclosed space; and a microelectronic element disposed within the space and electrically connected to the terminals. | 11-13-2008 |
20090008795 | Stackable microelectronic device carriers, stacked device carriers and methods of making the same - A method of manufacturing a microelectronic package. The method includes the steps of attaching at least one microelectronic element to a tape having upper terminals projecting upwardly from an upper surface of a dielectric layer, so that top surfaces of the terminals are disposed coplanar with or above a top surface of the microelectronic element after the attaching step, electrically connecting the microelectronic element to at least some of the upper terminals; and further includes the step of applying an encapsulant to cover at least a portion of the upper surface of the dielectric layer, leaving the upper terminals surfaces of the terminals exposed. | 01-08-2009 |
20090023249 | Wire bonded wafer level cavity package - A microelectronic device includes a chip having a front surface and a rear surface, the front surface having an active region and a plurality of contacts exposed at the front surface outside of the active region. The device further includes a lid overlying the front surface. The lid has edges bounding the lid, at least one of the edges including one or more outer portions and one or more recesses extending laterally inwardly from the outer portions, with the contacts being aligned with the recesses and exposed through them. | 01-22-2009 |
20090162975 | Method of forming a wafer level package - A method is provided for forming a microelectronic package at a wafer level. Such method can include providing a semiconductor wafer having a surface with a pattern of electrical contacts thereon. An interposer component can be provided which has a compliant dielectric layer bonded to a conductive layer. A pattern of holes can be formed through the compliant dielectric layer and the conductive layer which corresponds to the pattern of electrical contacts. The compliant dielectric layer can be contacted with the semiconductor wafer surface so that the pattern of holes is in an aligned position with the pattern of contacts and the compliant dielectric layer and the semiconductor wafer surface then bonded in the aligned position to unite the semiconductor wafer and the interposer component to form a wafer level semiconductor package. The wafer level semiconductor package can be diced to form individual semiconductor chip packages. | 06-25-2009 |
20100225006 | CHIPS HAVING REAR CONTACTS CONNECTED BY THROUGH VIAS TO FRONT CONTACTS - A microelectronic unit is provided in which front and rear surfaces of a semiconductor element may define a thin region which has a first thickness and a thicker region having a thickness at least about twice the first thickness. A semiconductor device may be present at the front surface, with a plurality of first conductive contacts at the front surface connected to the device. A plurality of conductive vias may extend from the rear surface through the thin region of the semiconductor element to the first conductive contacts. A plurality of second conductive contacts can be exposed at an exterior of the semiconductor element. A plurality of conductive traces may connect the second conductive contacts to the conductive vias. | 09-09-2010 |
20100242269 | COMPACT LENS TURRET ASSEMBLY - An electronic camera module incorporates a sensor unit ( | 09-30-2010 |
20130065390 | CHIPS HAVING REAR CONTACTS CONNECTED BY THROUGH VIAS TO FRONT CONTACTS - A method of fabricating a microelectronic unit can include providing a semiconductor element having front and rear surfaces, a plurality of conductive pads each having a top surface exposed at the front surface and a bottom surface remote from the top surface, and a first opening extending from the rear surface towards the front surface. The method can also include forming at least one second opening extending from the first opening towards the bottom surface of a respective one of the pads. The method can also include forming a conductive via, a conductive interconnect, and a contact, the conductive via in registration with and in contact with the conductive pad and extending within the second opening, the contact exposed at an exterior of the microelectronic unit, the conductive interconnect electrically connecting the conductive via with the contact and extending away from the via at least partly within the first opening. | 03-14-2013 |
20130316501 | ULTRA-THIN NEAR-HERMETIC PACKAGE BASED ON RAINIER - A microelectronic package including a dielectric layer having top and bottom surfaces, the dielectric layer having terminals exposed at the bottom surface; a metallic wall bonded to the dielectric layer and projecting upwardly from the top surface of the dielectric layer and surrounding a region of the top surface; a metallic lid bonded to the wall and extending over the region of the top surface so that the lid, the wall and the dielectric layer cooperatively define an enclosed space; and a microelectronic element disposed within the space and electrically connected to the terminals. | 11-28-2013 |