Kazuyuki Sakata
Kazuyuki Sakata, Tokyo JP
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20080237848 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device which makes equalization of wirings between address system chips easy and reduce the influence of crosstalk noise and capacitive coupling noise among data system wirings for connecting the chips. There are mounted, on a module board, a plurality of stacked memory chips which a data processor chip simultaneously accesses. Address system bonding pads to which a plurality of memory chips correspond are commonly coupled by a wire to a bonding lead at one end of the module board wiring whose other end is coupled by a wire to an address system bonding pads of the data processor. Data system bonding pads of the data processor chip are individually coupled to data system bonding pads of the memory chip. With respect to an arrangement of the plurality of data system bonding pads of the data processor chip, an arrangement of the data system bonding pads to which the memory chip, coupled by the data system wiring, corresponds is made such that memory chips are disposed in an alternating sequence. | 10-02-2008 |
20100244238 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device which makes equalization of wirings between address system chips easy and reduce the influence of crosstalk noise and capacitive coupling noise among data system wirings for connecting the chips. There are mounted, on a module board, a plurality of stacked memory chips which a data processor chip simultaneously accesses. Address system bonding pads to which a plurality of memory chips correspond are commonly coupled by a wire to a bonding lead at one end of the module board wiring whose other end is coupled by a wire to an address system bonding pads of the data processor. Data system bonding pads of the data processor chip are individually coupled to data system bonding pads of the memory chip. With respect to an arrangement of the plurality of data system bonding pads of the data processor chip, an arrangement of the data system bonding pads to which the memory chip, coupled by the data system wiring, corresponds is made such that memory chips are disposed in an alternating sequence. | 09-30-2010 |
20110127671 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device which makes equalization of wirings between address system chips easy and reduce the influence of crosstalk noise and capacitive coupling noise among data system wirings for connecting the chips. There are mounted, on a module board, a plurality of stacked memory chips which a data processor chip simultaneously accesses. Address system bonding pads to which a plurality of memory chips correspond are commonly coupled by a wire to a bonding lead at one end of the module board wiring whose other end is coupled by a wire to an address system bonding pads of the data processor. Data system bonding pads of the data processor chip are individually coupled to data system bonding pads of the memory chip. With respect to an arrangement of the plurality of data system bonding pads of the data processor chip, an arrangement of the data system bonding pads to which the memory chip, coupled by the data system wiring, corresponds is made such that memory chips are disposed in an alternating sequence. | 06-02-2011 |
Kazuyuki Sakata, Hiroshima JP
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20090145827 | Water Treatment System - A first treatment tank ( | 06-11-2009 |
20090266763 | Water Treatment Apparatus and Water Treatment Method | 10-29-2009 |
Kazuyuki Sakata, Hiroshima-Ken JP
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20090152193 | DRAINAGE WATER-TREATING METHOD AND DRAINAGE WATER-TREATING APPARATUS - Drainage water containing an organofluorine compound is introduced into a raw tank ( | 06-18-2009 |
20090250396 | DRAINAGE WATER-TREATING METHOD AND DRAINAGE WATER-TREATING APPARATUS - Drainage water containing organofluorine compounds is introduced into a micro-nano-babble generation tank ( | 10-08-2009 |
Kazuyuki Sakata, Fukuyama-Shi JP
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20080264843 | Manufacturing method, manufacturing device, and application device for liquid containing micro-nano bubbles - The application device for liquid containing micro-nano bubbles generates micro-nano bubbles in a wide size distribution with use of a submerged pump-type micro-nano bubble generator and a spiral flow-type micro-nano bubble generator. A micro-nano bubble generating aid metering pump is controlled by a bubble level meter and a level controller, so that the supply amount of a micro-nano bubble generating aid is controlled in response to the level of bubbles from a fluid level. The supply amount of a micro-nano bubble generating aid is also controlled by a turbidimeter and a controller in response to the turbidity of the liquid in a micro-nano bubble generation tank, while the amount of air supplied to the submerged pump-type micro-nano bubble generator is controlled in response to the turbidity of the liquid. Therefore, the device can produce a large amount of various micro-nano bubbles in a wide size distribution more economically. | 10-30-2008 |
20090101573 | Waste water treatment apparatus and waste water treatment method - In waste water treatment apparatus and method, a mineral mixing tank receives biologically treated water, sludge which is generated by biological treatment, and mineral sludge which contains calcium and so on from a settling tank. A mineral pump returns the sludge and the treated water from the mineral mixing tank to a raw water tank. An air-lift pump circulates treatment water between a reaeration tank having a semi-anaerobic section and a denitrification tank. In circulation of the treatment water between the reaeration tank and the denitrification tank, the semi-anaerobic section alleviates the change of environment for microorganisms and thereby realizes the environment easy to propagate for the microorganisms. The air-lift pump allows the agitation with low energy consumption even when the microorganisms are cultured up to a high concentration thereof. | 04-23-2009 |
Kazuyuki Sakata, Kodaira JP
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20080276112 | SEMICONDUCTOR INTEGRATED CIRCUIT - A memory interface circuit is connectable to a DDR-SDRAM which outputs read data in synchronization with a data strobe signal together with the data strobe signal. A clock generator generates internal clock signals and memory clock signals supplied to the DDR-SDRAM. The memory interface circuit determines a delay of arrival of the data strobe signal relative to the corresponding internal clock signal by using a data strobe signal inputted in a read cycle with respect to the DDR-SDRAM, samples the arrived read data, based on a signal obtained by shifting the phase of the arrived data strobe signal, and synchronizes the sampled read data to the corresponding internal clock signal on the basis of the result of determination of the arrival delay. | 11-06-2008 |
Kazuyuki Sakata, Kawachinagano JP
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20130005712 | COMPOSITION FOR NOXIOUS ORGANISMS-CONTROLLING AGENT AND METHOD FOR USING THE SAME - The present invention relates to a composition for noxious organisms-controlling agent having a synergistic effect and a method for using said composition, which comprises, as active ingredients thereof, one or more compounds selected from the phthalamide derivatives represented by general formula (I) being useful as an insecticide or acaricide and one or more compounds selected from the compounds having insecticidal, acaricidal or nematocidal activity: | 01-03-2013 |