Patent application number | Description | Published |
20090039336 | SEMICONDUCTOR DEVICE - The performance of a semiconductor device capable of storing information is improved. A memory layer of a memory element is formed by a first layer at a bottom electrode side and a second layer at a top electrode side. The first layer contains 20-70 atom % of at least one element of a first element group of Cu, Ag, Au, Al, Zn, and Cd, contains 3-40 atom % of at least one element of a second element group of V, Nb, Ta, Cr, Mo, W, Ti, Zr, Hf, Fe, Co, Ni, Pt, Pd, Rh, Ir, Ru, Os, and lanthanoid elements, and contains 20-60 atom % of at least one element of a third element group of S, Se, and Te. The second layer contains 5-50 atom % of at least one element of the first element group, 10-50 atom % of at least one element of the second element group, and 30-70 atom % of oxygen. | 02-12-2009 |
20090242868 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A solid electrolyte memory involves a problem that stable rewriting is difficult since the amount of ions in the solid electrolyte and the shape of the electrode are changed by repeating rewriting. In a semiconductor device in which information is stored or the circuit connection is changed by the change of resistance of the solid electrolyte layer, the solid electrolyte layer includes a composition, for example, of Cu—Ta—S and an ion supply layer in adjacent or close therewith as Cu—Ta—O, in which ions supplied from the ion supply layer form a conduction path in the solid electrolyte layer thereby making it possible to store information by the level of the resistance and applying the electric pulse to change the resistance, in which the ion supply layer includes crystals having, for example, a compositional ratio of: Cu—Ta—O=1:2:6 and rewriting operation can be performed stably. | 10-01-2009 |
20090262568 | SEMICONDUCTOR MEMORY DEVICE - A resistance variable memory reduces the nonuniformity of resistance values after programming, so that a rewrite operation can be performed on a memory cell at high speed. A reference resistor is connected in series with the resistance variable memory cell, and a sensor amplifier detects whether the potential at an intermediate node between the memory cell and the reference resistor exceeds a given threshold voltage, so as to stop the write operation based on a detection result. | 10-22-2009 |
20090273961 | SEMICONDUCTOR DEVICE - A technique for increasing rewriting current without increasing a power supply voltage and also reducing location dependency inside a memory array of a resistive state after the rewriting is provided in a resistance change memory in which the resistance value of a memory cell changes between logical values “1” and “0”. In the resistance change memory, bit lines are formed into a layered structure, the bit line select switches for connecting to the global bit line are provided at both ends of the local bit line, and a control method of the bit line select switches is changed in the writing and the reading, thereby realizing the optimum array configurations for each of them. More specifically, in the writing and the reading, two current paths are provided in parallel by turning ON the bit line select switches simultaneously. | 11-05-2009 |
20110044092 | SEMICONDUCTOR MEMORY DEVICE - A resistance variable memory reduces the nonuniformity of resistance values after programming, so that a rewrite operation can be performed on a memory cell at high speed. A reference resistor is connected in series with the resistance variable memory cell, and a sensor amplifier detects whether the potential at an intermediate node between the memory cell and the reference resistor exceeds a given threshold voltage, so as to stop the write operation based on a detection result. | 02-24-2011 |
20120092921 | SEMICONDUCTOR DEVICE - A technique for increasing rewriting current without increasing a power supply voltage and also reducing location dependency inside a memory array of a resistive state after the rewriting is provided in a resistance change memory in which the resistance value of a memory cell changes between logical values “1” and “0”. In the resistance change memory, bit lines are formed into a layered structure, the bit line select switches for connecting to the global bit line are provided at both ends of the local bit line, and a control method of the bit line select switches is changed in the writing and the reading, thereby realizing the optimum array configurations for each of them. More specifically, in the writing and the reading, two current paths are provided in parallel by turning ON the bit line select switches simultaneously. | 04-19-2012 |
Patent application number | Description | Published |
20110135878 | Dispersoid having metal-oxygen bonds, metal oxide film, and monomolecular film - Dispersoids having metal-oxygen groups that are suitable for the production of metal oxide thin-films at a low temperature of 200° C. or below and for the production of homogeneous organic-inorganic hybrid materials. The dispersoid having metal-oxygen bonds may be obtained by mixing a metal compound having at least three hydrolyzable groups with at least 0.5 mole but less than 2 moles of water per mole of the metal compound in an organic solvent, in the absence of an acid, a base, and/or a dispersion stabilizer, and at a temperature at or below the temperature at which the metal compound begins to hydrolyze, then raising the temperature to at least the temperature at which hydrolysis begins. | 06-09-2011 |
20120082793 | DISPERSOID HAVING METAL-OXYGEN BONDS, METAL OXIDE FILM, AND MONOMOLECULAR FILM - Dispersoids having metal-oxygen groups that are suitable for the production of metal oxide thin-films at a low temperature of 200° C. or below and for the production of homogeneous organic-inorganic hybrid materials. The dispersoid having metal-oxygen bonds may be obtained by mixing a metal compound having at least three hydrolyzable groups with at least 0.5 mole but less than 2 moles of water per mole of the metal compound in an organic solvent, in the absence of an acid, a base, and/or a dispersion stabilizer, and at a temperature at or below the temperature at which the metal compound begins to hydrolyze, then raising the temperature to at least the temperature at which hydrolysis begins. | 04-05-2012 |
Patent application number | Description | Published |
20110164460 | Semiconductor device and method of controlling the same - A semiconductor device includes a delay buffer, and a pipeline control circuit. The pipeline control circuit controls the delay buffer to hold read data from outputting to a read/write bus for each of banks based on a read command to the each bank while the pipeline control circuit controlling the delay buffer to output write data to the read/write bus, when a next command to the each bank is a write command for the write data. The read/write bus is common to the banks. | 07-07-2011 |
20110176379 | SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CELL ARRAY OF OPEN BIT LINE TYPE AND CONTROL METHOD THEREOF - A semiconductor memory device includes: first and second bit lines of an open bit-line system; a sense amplifier that amplifies a potential difference between the first and second bit lines; a pair of first and second local data lines corresponding to the first and second bit lines, respectively; and a write amplifier circuit. The write amplifier circuit changes a potential of the second local data line without changing a potential of the first local data line at a time of writing data for the first bit line, and changes a potential of the first local data line without changing a potential of the second local data line at a time of writing data for the second bit line. | 07-21-2011 |
20130082404 | SEMICONDUCTOR DEVICE AND MEMORY SYSTEM - A semiconductor device is disclosed in which a plurality of memory cores are provided on a semiconductor chip. Each of the memory cores comprises: first and second circuit regions and a first and second through electrode groups. a first power supply is supplied in the first circuit region in which a data bus for parallel data is driven, and a second power supply separated from the first power supply is supplied in the second circuit region in which the parallel data and serial data are bidirectionally converted. The first through electrode group includes through electrodes supplying the first power supply to the first circuit region, and the second through electrode group includes through electrodes supplying the second power supply to the second circuit region. | 04-04-2013 |
20130328187 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device which includes a plurality of first through-substrate vias that are used to supply power from a first power supply and that penetrate through a substrate structure, and a plurality of second through-substrate vias that are used to supply power from a second power supply different from the first power supply and that penetrate through a substrate structure. The semiconductor device also includes a through-substrate via string composed by the first and second through-substrate vias, in which the first through-substrate vias are located adjacent to one another and the second through-substrate vias are also located adjacent to one another. The through-substrate via string is disposed in the substrate structure for extending in a first direction. | 12-12-2013 |
20140154790 | BIOMOLECULE INFORMATION ANALYSIS DEVICE - Provided is a device that, on the basis of a measurement result of a current that has a low value and a wide distribution, identifies the composition of biological molecules passing through a nanoparticle path. This biomolecule information analysis device obtains a current value by applying an electrical field to biomolecules passing through a gap between a first electrode and a second electrode, and identifies the structure of the biomolecules by integrating the current value and making a comparison with a reference value (see FIG. | 06-05-2014 |
20140169111 | DEVICE INCLUDING A PLURALITY OF MEMORY BANKS AND A PIPELINE CONTROL CIRCUIT CONFIGURED TO EXECUTE A COMMAND ON THE PLURALITY OF MEMORY BANKS - A method for carrying out read and write operations in a synchronous memory device having a shared I/O, includes receiving a read command directed to a first internal memory bank during a first timeslot, activating the first internal memory bank to access read data at a read address requested by the read command, receiving a write command directed to a second internal memory bank during a second timeslot later than the first timeslot, determining whether a data collision between the read data for output to the shared I/O with normal read latency and write data to be received on the shared I/O with normal write latency would occur, and receiving the write data on the shared I/O with the normal write latency during a third timeslot later than the second timeslot. | 06-19-2014 |
Patent application number | Description | Published |
20110194361 | SEMICONDUCTOR DEVICE - An array configuration capable of supplying a necessary and sufficient current in a small area is achieved and a reference cell configuration suitable to temperature characteristics of a TMR element is achieved. In a memory using inversion of spin transfer switching, a plurality of program drivers are arranged separately along one global bit line, and one sense amplifier is provided to one global bit line. A reference cell to which “1” and “0” are programmed is shared by two arrays and a sense amplifier. | 08-11-2011 |
20120267792 | SEMICONDUCTOR DEVICE - A stacked device includes a plurality of semiconductor chips connected to each other by through electrodes. The same number of through electrodes are included in each of paths extending from a first power source terminal through each of circuit elements formed for the semiconductor chips to a second power source terminal. | 10-25-2012 |
20130033928 | SEMICONDUCTOR STORAGE DEVICE AND DATA PROCESSING METHOD - Since a nonvolatile RAM allows random reading and writing operations, an erasing mode is unnecessary. From the system side, however, it is desirable to have the erasing mode because of its nonvolatile characteristic. Moreover, the erasing operation is desirably carried out at high speed with low power consumption. Therefore, memory cell arrays COA and DTA containing a plurality of memory cells MC each having a magnetoresistive element are provided, a series of data is written to the memory cell arrays COA and DTA, and at the time of erasing, an erasing operation is carried out by writing predetermined data only to the memory cell array COA. | 02-07-2013 |
20130044537 | MAGNETIC MEMORY, METHOD OF MANUFACTURING THE SAME, AND METHOD OF DRIVING THE SAME - There is provided a magnetic memory with using a magnetoresistive effect element of a spin-injection magnetization reversal type, in which a multi-value operation is possible and whose manufacturing and operation are simple. A preferred aim of this is solved by providing two or more magnetoresistive effect elements which are electrically connected in series to each other and by selecting one of the series-connected elements depending on a direction of a current carried in the series-connected elements, a magnitude thereof, and an order of the current thereof for performing the writing operation. For example, it is solved by differentiating plane area sizes of the respective magnetoresistive effect elements which have the same film structure from each other so as to differentiate resistance change amounts caused by respective magnetization reversal and threshold current values required for respective magnetization reversal from each other. | 02-21-2013 |
20130058156 | MAGNETIC MEMORY CELL AND MAGNETIC RANDOM ACCESS MEMORY - A relation between a drive current of a selection transistor of a magnetic memory and a threshold magnetization switching current of the magnetoresistance effect element is optimized. In order to optimize the relation between the drive current of the selection transistor and the threshold magnetization switching current of the magnetoresistance effect element | 03-07-2013 |
20150036423 | SEMICONDUCTOR DEVICE - An array configuration capable of supplying a necessary and sufficient current in a small area is achieved and a reference cell configuration suitable to temperature characteristics of a TMR element is achieved. In a memory using inversion of spin transfer switching, a plurality of program drivers are arranged separately along one global bit line, and one sense amplifier is provided to one global bit line. A reference cell to which “1” and “0” are programmed is shared by two arrays and a sense amplifier. | 02-05-2015 |
Patent application number | Description | Published |
20120004349 | Epoxy resin composition, curing agent, and curing accelerator - The present invention provides a liquid curable epoxy resin composition that has excellent storage stability and curing properties and provides a cured product having excellent properties, particularly, excellent organic solvent resistance. For that purpose, a clathrate containing a carboxylic acid compound and at least one selected from the group consisting of an imidazole compound represented by formula (I), wherein R | 01-05-2012 |
20120004377 | CLATHRATE, CURING AGENT, CURE ACCELERATOR, EPOXY RESIN COMPOSITION, AND EPOXY RESIN COMPOSITION FOR ENCAPSULATION OF SEMICONDUCTOR - It is an object of the present invention to provide a clathrate that suppresses a curing reaction at low temperature to promote an improvement in storage stability (one-component stability), and can effectively cure a resin by heating treatment. A clathrate suitable for the clathrate is a clathrate containing (b1) at least one selected from the group consisting of an aliphatic polyvalent carboxylic acid, 5-nitroisophthalic acid, 5-tert-butylisophthalic acid, 5-hydroxyisophthalic acid, isophthalic acid, and benzophenone-4,4′-dicarboxylic acid; and (b2) at least one selected from the group consisting of an imidazole compound represented by the following formula (I), and 1,8-diazabicyclo[5.4.0]undecene-7, at a molar ratio of 1:1. | 01-05-2012 |
Patent application number | Description | Published |
20120196991 | COMPOSITION FOR FORMATION OF CURED EPOXY RESIN, AND CURED PRODUCTS THEREOF - An object of the present invention is to provide a composition for the formation of a cured epoxy resin, wherein the composition can suppress a curing reaction at a low temperature to thereby enhance one-pack stability, and can also be subjected to a heating treatment to thereby effectively cure a resin. The present invention provides a composition for the formation of a cured epoxy resin, the composition comprising the following components (A), (B) and (C):
| 08-02-2012 |
20130059942 | CURABLE POWDER COATING COMPOSITION, AND CURED PRODUCT OF SAME - Disclosed is an epoxy or epoxy-polyester curable powder coating composition which can form a favorable cured coating film excellent in adhesion and solvent resistance and is excellent in storage stability. The curable powder coating composition of the present invention contains the following component (A) and component (B): (A) an epoxy resin or an epoxy-polyester hybrid resin; and (B) a clathrate complex which contains (b1) at least one selected from the group consisting of a carboxylic acid compound and a tetrakisphenol compound represented by the following formula (I), and (b2) at least one selected from compounds represented by formula (II). The carboxylic acid compound preferably includes an aromatic carboxylic acid. | 03-07-2013 |
20130158231 | LIQUID CURABLE EPOXY RESIN COMPOSITION AND ADHESIVE AGENT CONTAINING SAME - An object of the present invention is to provide a curable epoxy resin composition containing an epoxy resin, wherein the composition is excellent in storage stability and curing characteristics and provides a cured product excellent in characteristics, particularly organic solvent resistance; an adhesive agent consisting of the composition; and an adhesive agent consisting of a curable epoxy resin composition excellent in adhesive strength. The curable epoxy resin composition of the present invention is a liquid curable epoxy resin composition containing the following (A) and (B): (A) an epoxy resin or an epoxy-polyester hybrid resin; and (B) a clathrate containing the following (b1) and (b2): (b1) at least one compound selected from the group consisting of a carboxylic acid compound represented by the formula A(COOH) | 06-20-2013 |