Patent application number | Description | Published |
20100273806 | TETRAHYDROCYCLOPENTA[B]INDOL-3-YL CARBOXYLIC ACID DERIVATIVES USEFUL IN THE TREATMENT OF AUTOIMMUNE AND INFLAMMATORY DISORDERS - The present invention relates to certain (1,2,4-oxadiazol-3-yl)-1,2,3,4-tetrahydrocyclo-penta[b]indol-3-yl carboxylic acid derivatives of Formula (Ia) and pharmaceutically acceptable salts thereof, which exhibit useful pharmacological properties, for example, as agonists of the S1P1 receptor. Also provided by the present invention are pharmaceutical compositions containing compounds of the invention, and methods of using the compounds and compositions of the invention in the treatment of S1P1 associated disorders, for example, psoriasis, rheumatoid arthritis, Crohn's disease, transplant rejection, multiple sclerosis, systemic lupus erythematosus, ulcerative colitis, type I diabetes, acne, microbial infections or diseases and viral infections or diseases. | 10-28-2010 |
20100292233 | DIHYDRO-1H-PYRROLO[1,2-A]INDOL-1-YL CARBOXYLIC ACID DERIVATIVES WHICH ACT AS S1P1 AGONISTS - The present invention relates to certain (1,2,4-oxadiazol-3-yl)-2,3-dihydro-1H-pyrrolo[1,2-a]indol-1-yl carboxylic acid derivatives of Formula (Ia) and pharmaceutically acceptable salts thereof, which exhibit useful pharmacological properties, for example, as agonists of the S1P1 receptor. Also provided by the present invention are pharmaceutical compositions containing compounds of the invention, and methods of using the compounds and compositions of the invention in the treatment of S1P1 associated disorders, for example, psoriasis, rheumatoid arthritis, Crohn's disease, transplant rejection, multiple sclerosis, systemic lupus erythematosus, ulcerative colitis, type I diabetes, sepsis, myocardial infarction, ischemic stroke, acne, microbial infections or diseases and viral infections or diseases. | 11-18-2010 |
20110160243 | SUBSTITUTED TRICYCLIC ACID DERIVATIVES AS S1P1 RECEPTOR AGONISTS USEFUL IN THE TREATMENT OF AUTOIMMUNE AND INFLAMMATORY DISORDERS - The present invention relates to certain substituted tricyclic acid derivatives of Formula (I) and pharmaceutically acceptable salts thereof, which exhibit useful pharmacological properties, for example, as agonists of the S1P1 receptor. Also provided by the present invention are pharmaceutical compositions containing compounds of the invention, and methods of using the compounds and compositions of the invention in the treatment of S1P1-associated disorders, for example, psoriasis, rheumatoid arthritis, Crohn's disease, transplant rejection, multiple sclerosis, systemic lupus erythematosus, ulcerative colitis, type I diabetes, acne, myocardial ischemia-reperfusion injury, hypertensive nephropathy, glomerulosclerosis, gastritis, polymyositis, thyroiditis, vitiligo, hepatitis, biliary cirrhosis, microbial infections and associated diseases, viral infections and associated diseases, diseases and disorders mediated by lymphocytes, auto immune diseases, inflammatory diseases, and cancer. | 06-30-2011 |
20130184307 | SUBSTITUTED TRICYCLIC ACID DERIVATIVES AS S1P1 RECEPTOR AGONISTS USEFUL IN THE TREATMENT OF AUTOIMMUNE AND INFLAMMATORY DISORDERS - The present invention relates to certain substituted tricyclic acid derivatives of Formula (I) and pharmaceutically acceptable salts thereof, which exhibit useful pharmacological properties, for example, as agonists of the S1P1 receptor. | 07-18-2013 |
Patent application number | Description | Published |
20080201595 | INTELLIGENT POWER CONTROL - An intelligent power control system for intelligently controlling startup and shutdown sequences of IT equipment to reduce peak power requirements is provided. The intelligent power control system sends an indication to power up to a power module connected to an electronic device. The system monitors the power consumption of the electronic device during startup, and determines when the electronic device has reached a peak level of power consumption. The system then powers up other devices based on the power consumption characteristics of each preceding device. The system may use similar techniques when shutting down devices or transitioning devices from a low-power state to a normal power state. Thus, the intelligent power control system establishes an order and timing for powering up or down electronic devices that improves the power consumption characteristics of the electronic devices and reduces the power requirements of the electronic devices allowing smaller, lighter, and less expensive power supplies and battery backup systems to be used. | 08-21-2008 |
20100260157 | MOBILE BROADBAND COMMUNICATIONS SYSTEM, SUCH AS A DEPLOYABLE SELF-CONTAINED PORTABLE SYSTEM - Systems and methods for establishing IT services in edge environments are described. In some examples, the system comprises a transportable housing capable of being carried by personnel, a plurality of commercial off-the-shelf components contained in the housing and coupled together and configured to provide the broadband communications network, a software management system operatively coupled to the plurality of components, a network connection subsystem defined by at least a first portion of the plurality of components and configured to establish access to the broadband communications network, and a connection subsystem defined by at least a second portion of the plurality of components and that provides a user with a connection to the broadband communications network via the network connection subsystem | 10-14-2010 |
20130070610 | MOBILE COMMUNICATIONS SYSTEM, SUCH AS A DEPLOYABLE SELF-CONTAINED PORTABLE SYSTEM - Systems and methods for establishing IT services in edge environments are described. In some examples, the system comprises a transportable housing capable of being carried by personnel, a plurality of commercial off-the-shelf components contained in the housing and coupled together and configured to provide the broadband communications network, a software management system operatively coupled to the plurality of components, a network connection subsystem defined by at least a first portion of the plurality of components and configured to establish access to the broadband communications network, and a connection subsystem defined by at least a second portion of the plurality of components and that provides a user with a connection to the broadband communications network via the network connection subsystem | 03-21-2013 |
Patent application number | Description | Published |
20100131227 | SYSTEM AND METHOD OF CORRELATING THE ORIENTATION OF A TRI-AXIAL ACCELEROMETER - A system and method for analyzing a device that includes a mass configured for motion. The system includes a tri-axial accelerometer disposed to detect acceleration vectors of the device and to output three channels of acceleration data, and a user interface receiving the three channels of acceleration data. The user interface is configured to correlate the three channels of acceleration data with a reference frame defined by three orthogonal axes intersecting at a vertex, and includes a display and a selector. The display shows sets of options that represent dispositions of the device with respect to gravity, placements of the tri-axial accelerometer with respect to the device, and orientations of the tri-axial accelerometer with respect to the device. The selector selects one device disposition option, one tri-axial accelerometer placement option, and one tri-axial accelerometer orientation option. | 05-27-2010 |
20120024063 | System And Method Of Correlating The Orientation Of A Tri-Axial Accelerometer - A system and method for analyzing a device that includes a mass configured for motion. The system includes a tri-axial accelerometer disposed to detect acceleration vectors of the device and to output three channels of acceleration data, and a user interface receiving the three channels of acceleration data. The user interface is configured to correlate the three channels of acceleration data with a reference frame defined by three orthogonal axes intersecting at a vertex, and includes a display and a selector. The display shows sets of options that represent dispositions of the device with respect to gravity, placements of the tri-axial accelerometer with respect to the device, and orientations of the tri-axial accelerometer with respect to the device. The selector selects one device disposition option, one tri-axial accelerometer placement option, and one tri-axial accelerometer orientation option. | 02-02-2012 |
Patent application number | Description | Published |
20110147839 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Multi-gate metal oxide silicon transistors and methods of making multi-gate metal oxide silicon transistors are provided. The multi-gate metal oxide silicon transistor contains a bulk silicon substrate containing one or more convex portions between shallow trench regions; one or more dielectric portions over the convex portions; one or more silicon fins over the dielectric portions; a shallow trench isolation layer in the shallow trench isolation regions; and a gate electrode. The upper surface of the shallow trench isolation layer can be located below the upper surface of the convex portion, or the upper surface of the shallow trench isolation layer can be located between the lower surface and the upper surface of first dielectric layer. The multi-gate metal oxide silicon transistor can contain second spacers adjacent to side surfaces of the convex portions in a source/drain region. | 06-23-2011 |
20110260282 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHODS - Methods of making fins and semiconductor structures containing fins are provided. The methods involve forming a multi-layer structure over fins and isolation materials and performing a multi-stage etching process to remove upper portions of the multi-layer structure and upper portions of isolation materials. Upper portions of the fins are exposed by removing the upper portions of the isolation materials via the multi-stage etching process. A stage of the multi-stage etching process removes an upper layer of the multi-layer structure and an upper portion of the isolation materials, and the stage can be terminated about at the same time when the upper surface of the underlying layer of the multi-layer structure is exposed. | 10-27-2011 |
20110298058 | FACETED EPI SHAPE AND HALF-WRAP AROUND SILICIDE IN S/D MERGED FINFET - FinFETs and methods of making. FinFETs are provided. The FinFET contains two or more fins over a semiconductor substrate; two or more epitaxial layers over side surfaces of the fins; and metal-semiconductor compounds over an upper surfaces of the epitaxial layers. The fin has side surfaces that are substantially vertical relative to the upper surface of the semiconductor substrate. The epitaxial layer has an upper surface that extends at an oblique angle with respect to the side surface of the fin. The FinFET can contain a contact over the metal-semiconductor compounds. | 12-08-2011 |
20120193751 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING - Methods of making fins and semiconductor structures containing fins are provided. The methods involve forming a multi-layer structure over a semiconductor substrate. The multi-layer structure comprises a first layer over the semiconductor substrate, a second layer over the first layer, and a third layer over the second layer. The method also comprises removing upper portions of the semiconductor substrate and portions of the multi-layer structure to form fins of the semiconductor substrate and portions of the multi-layer structure. Further, the method comprises selectively oxidizing the first layer while oxidization of the second layer and the third layer is less than the oxidization of the first layer. The oxidation can be performed before gap fill recess or after gap fill recess. | 08-02-2012 |
Patent application number | Description | Published |
20090174036 | PLASMA CURING OF PATTERNING MATERIALS FOR AGGRESSIVELY SCALED FEATURES - A methodology is disclosed that enables the fabrication of semiconductor devices (i.e., STI structures, gates, and interconnects) with significantly reduced line edge roughness (LER) and line width roughness (LEW) post lithography patterning. The inventive methodology entails the use of an inert species containing plasma tuned to enhanced its' vacuum ultra violet (VUV) emissions post lithography and/or post one of the etch processes of a given feature (on an identical etch platform) to entice increased crosslinking of one or more patterning materials, thus enabling increased etch resistance and reduced LER and LEW post etching processing. | 07-09-2009 |
20100224943 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHODS WITH USING NON-PLANAR TYPE OF TRANSISTORS - Static random access memory cells and methods of making static random access memory cells are provided. The static random access memory cells contain two non-planar pass-gate transistors, two non-planar pull-up transistors, two non-planar pull-down transistors. A portion of a fin of the non-planar pull-up transistor is electrically connected to a portion of a fin of the non-planar pull-down transistor by an assist-bar. The methods involve forming an assist-fin between fins of a non-planar pull-up transistor and a non-planar pull-down transistor and between gate electrodes, and widening a width of the assist-fin to form the assist-bar so that a portion of the fin of non-planar pull-up transistor is electrically connected to a portion of the fin of non-planar pull-down transistor via the assist-bar. | 09-09-2010 |
20120108016 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHODS WITH USING NON-PLANAR TYPE OF TRANSISTORS - Static random access memory cells and methods of making static random access memory cells are provided. The static random access memory cells contain two non-planar pass-gate transistors, two non-planar pull-up transistors, two non-planar pull-down transistors. A portion of a fin of the non-planar pull-up transistor is electrically connected to a portion of a fin of the non-planar pull-down transistor by an assist-bar. The methods involve forming an assist-fin between fins of a non-planar pull-up transistor and a non-planar pull-down transistor and between gate electrodes, and widening a width of the assist-fin to form the assist-bar so that a portion of the fin of non-planar pull-up transistor is electrically connected to a portion of the fin of non-planar pull-down transistor via the assist-bar. | 05-03-2012 |
Patent application number | Description | Published |
20120000888 | METHODS AND APPARATUS FOR RADIO FREQUENCY (RF) PLASMA PROCESSING - Methods and apparatus for minimizing reflected radio frequency (RF) energy are provided herein. In some embodiments, an apparatus may include a first RF energy source having frequency tuning to provide a first RF energy, a first matching network coupled to the first RF energy source, one or more sensors to provide first data corresponding to a first magnitude and a first phase of a first impedance of the first RF energy, wherein the first magnitude is equal a first resistance defined as a first voltage divided by a first current and the first phase is equal to a first phase difference between the first voltage and the first current, and a controller adapted to control a first value of a first variable element of the first matching network based upon the first magnitude and to control a first frequency provided by the first RF energy source based upon the first phase. | 01-05-2012 |
20140342570 | ETCH PROCESS HAVING ADAPTIVE CONTROL WITH ETCH DEPTH OF PRESSURE AND POWER - The disclosure concerns a plasma-enhanced etch process in which chamber pressure and/or RF power level is ramped throughout the etch process. | 11-20-2014 |
20150072530 | METHODS FOR ETCHING MATERIALS USING SYNCHRONIZED RF PULSES - Embodiments of the present invention provide methods for etching a material layer using synchronized RF pulses. In one embodiment, a method includes providing a gas mixture into a processing chamber, applying a first RF source power at a first time point to the processing chamber to form a plasma in the gas mixture, applying a first RF bias power at a second time point to the processing chamber to perform an etching process on the substrate, turning off the first RF bias power at a third time point while continuously maintaining the first RF source power on from the first time point through the second and the third time points, and turning off the first RF source power at a fourth time point while continuously providing the gas mixture to the processing chamber from the first time point through the second, third and fourth time points. | 03-12-2015 |