Patent application number | Description | Published |
20090019550 | TRUSTED HARDCOPY DOCUMENT - A trusted hardcopy document is generated using a two-part confirmation number including a private part and a public part. A public part of the confirmation number is received at a first party creating the trusted hardcopy document. The private part of the confirmation number is sent to an owner of the trusted hardcopy document by a trusted party and is not sent to the first party creating the trusted hardcopy document. A human-readable form and a machine readable form of the public part of the confirmation number are printed on the trusted hardcopy document. | 01-15-2009 |
20100080391 | Auditing Data Integrity - Various approaches are described for auditing integrity of stored data. In one approach, a data set is provided from a client to a storage provider, and the data set is stored at a first storage arrangement by the storage provider. An auditor determines whether the data set stored at the first storage arrangement is corrupt without reliance on any part of the data set and any derivative of any part of the data set stored by the client. While the auditor is determining whether the data set stored at the first storage arrangement is corrupt, the auditor is prevented from being exposed to information specified by the data set. The auditor outputs data indicative of data corruption in response to determining that the data set stored at the first storage arrangement is corrupt. | 04-01-2010 |
20100198871 | INTUITIVE FILE SHARING WITH TRANSPARENT SECURITY - A file sharing system includes authorization-based security to control access to shared files; and a synchronizer which uses the authorization-based security to monitor the shared files for changes and propagating the changes according to sharing relationships. A method for file sharing includes using authorization-based security to control access to a shared file; and monitoring the shared file for changes using a synchronizer which incorporates the authorization-based security to access the shared file. | 08-05-2010 |
20110270979 | Reducing Propagation Of Message Floods In Computer Networks - A computer network ( | 11-03-2011 |
20130046979 | PROTECTING THE INFORMATION ENCODED IN A BLOOM FILTER USING ENCODED BITS OF DATA - Illustrated is a system and method that includes identifying data stored as an entry in a list. The system and method also includes truncating the entry to create a truncated entry. It further includes transforming the truncated entry into a hash, the hash used to set an index position value within a Bloom filter. The system and method also includes an interface module to transmit the Bloom filter. | 02-21-2013 |
20130086655 | PASSWORD CHANGING - In one example, a computing device generates a new password for accessing a user account and/or computing system and inspires a change of an existing password for the user account and/or computing system to the new password. Thereafter, the computing device detects occurrence of a condition to trigger another change of the password for the user account and/or computing system and, responsively, inspires another change of the password for the user account and/or computing system. | 04-04-2013 |
20130177157 | ENCRYPTION KEY MANAGEMENT - An encryption key fragment is divided into a number of encryption key fragments. Requests to store different ones of the encryption key fragments are transmitted to different computer memory storage systems. An individual request to store an encryption key fragment includes one of the encryption key fragments and bears an access control hallmark for regulating access to the encryption key fragment. | 07-11-2013 |
20130290780 | RECOVERY SEGMENTS - In one example, a method for implementing recovery segments includes sending an application message from a parent process executed by a first computing device to a child process executed by a second computing device and identifying a dependency created by the application message. This identified dependency is included in a dependence set of the child process and saved. A checkpoint is generated by the parent process and a checkpoint message that includes dependency information is sent from the parent process to the child process. The child process modifies the dependence set according to the dependency information and generates a second checkpoint that is saved in nonvolatile memory of the second computing device. Upon occurrence of a failure of the parent process, the child process reverts to a most recent checkpoint generated by the child process that does not include the effects of processing an orphan message. | 10-31-2013 |
20140040898 | DISTRIBUTED TRANSACTION PROCESSING - A system includes an initiator and processing nodes. The initiator distributes portions of a transaction among the processing nodes. Each processing node has at least one downstream neighbor to which the processing node sends commit messages. The commit messages include a commit status of the processing node. The downstream neighbor is also a processing node. | 02-06-2014 |
20140310453 | SHIFTABLE MEMORY SUPPORTING ATOMIC OPERATION - A shiftable memory supporting atomic operation employs built-in shifting capability to shift a contiguous subset of data from a first location to a second location within memory during an atomic operation. The shiftable memory includes the memory to store data. The memory has the built-in shifting capability. The shiftable memory further includes an atomic primitive defined on the memory to operate on the contiguous subset. | 10-16-2014 |
20140359705 | Granting Permission to Use an Object Remotely with a Context Preserving Mechanism - Granting permission to use an object remotely with a context preserving mechanism includes selecting an object stored at a first electronic location based on user input, granting permission to a subject to use the object remotely by selecting the subject based on the user input, and visually depicting a sharing relationship with the subject in response to using the object based on the user input. | 12-04-2014 |
20150046644 | SHIFTABLE MEMORY DEFRAGMENTATION - Shiftable memory that supports defragmentation includes a memory having built-in shifting capability, and a memory defragmenter to shift a page of data representing a contiguous subset of data stored in the memory from a first location to a second location within the memory to be adjacent to another page of stored data. A method of memory defragmentation includes defining an array in memory cells of the shiftable memory and performing a memory defragmentation using the built-in shifting capability of the shiftable memory to shift a data page stored in the array. | 02-12-2015 |
Patent application number | Description | Published |
20150370621 | METHODS AND APPARATUS FOR USING SMART ENVIRONMENT DEVICES VIA APPLICATION PROGRAM INTERFACES - Systems and Methods disclosed herein relate to providing a message to an application programming interface (API). The message includes a request for data from a data model, a submission of data to the data model, or both; and a host selection between: a representational state transfer (REST) host and a subscription-based application programming interface (API) host, wherein the REST host receives REST-based messages and the subscription-based API host receives messages in accordance with a standard of the subscription-based API host; wherein the request for data, the submission of data, or both are configured to create, delete, modify, or any combination thereof data related to a smart-device environment structure, a thermostat, a hazard detector, or any combination thereof stored in a data model accessible by the API. | 12-24-2015 |
20150372833 | METHODS AND APPARATUS FOR USING SMART ENVIRONMENT DEVICES VIA APPLICATION PROGRAM INTERFACES - Systems and Methods disclosed herein relate to provisioning vendor information to associate vendor data access rights, vendor data writing rights, or both, of a data model comprising information related to one or more smart-devices, one or more smart-device environment structures comprising the one or more smart-devices, or any combination thereof with the vendor; provisioning a particular electronic device type of the vendor by providing information about the particular electronic device type to a service that interprets this information to understand subsequent data submissions of the particular electronic device, wherein the provisioning of the particular electronic device is associated with the vendor; pairing the particular electronic device with a system hosting the data model by registering the particular electronic device with the system hosting the data model; and sending the subsequent data submissions from the one or more smart-devices to the service. | 12-24-2015 |
20150372834 | METHODS AND APPARATUS FOR USING SMART ENVIRONMENT DEVICES VIA APPLICATION PROGRAM INTERFACES - In one embodiment, one or more non-transitory, tangible, machine-readable media includes instructions to send one or more requests to retrieve, access, view, subscribe, or modify data in a data model representative of one or more smart environments. The data model includes a metadata object that includes an access token used to identify which user the data is associated with in the data model, a devices object that includes information related to one or more electronic devices, and a structures object that includes one or more references to the one or more electronic devices in the one or more smart environments. | 12-24-2015 |
Patent application number | Description | Published |
20090160482 | Formation of a hybrid integrated circuit device - Formation of a hybrid integrated circuit device ( | 06-25-2009 |
20100127782 | Common Centroid Electrostatic Discharge Protection for Integrated Circuit Devices - A method of protecting a circuit design implemented within an integrated circuit (IC) from electrostatic discharge (ESD) can include positioning a device array pair comprising first and second device arrays on the IC to share a common centroid, wherein the first and second device arrays are matched. An ESD diode array pair comprising first and second ESD diode arrays can be positioned on the IC adjacent to a first perimeter encompassing the first and second device arrays, wherein the first and second ESD diode arrays share the common centroid and are matched. A cathode terminal of each ESD diode of the first ESD diode array can be coupled to an input of the first device array, and a cathode terminal of each ESD diode of the second ESD diode array can be coupled to an input of the second device array. | 05-27-2010 |
20100188787 | METHOD AND APPARATUS TO REDUCE FOOTPRINT OF ESD PROTECTION WITHIN AN INTEGRATED CIRCUIT - An input/output (“I/O”) circuit has a first N-channel metal-oxide semiconductor (“NMOS”) field-effect transistor (“FET”) coupled to the input pin with a silicide block. A first P-channel metal-oxide semiconductor (“PMOS”) FET is directly connected to the input pin, with its N-well electrically coupled to an ESD well bias circuit. An NMOS low-voltage differential signal (“LVDS”) driver is also directly connected to the input pin, and has cascaded NMOS FETs. The first NMOS FET of the LVDS driver is fabricated within a first P-tap guard ring electrically coupled to ground and an N-well guard ring coupled to the ESD well bias. The second NMOS FET of the LVDS driver is fabricated within a second P-tap guard ring electrically coupled to ground. | 07-29-2010 |
20110026173 | ENHANCED IMMUNITY FROM ELECTROSTATIC DISCHARGE - Enhanced electrostatic discharge (“ESD”) protection for an integrated circuit is described. An embodiment relates generally to a circuit for protection against ESD. The circuit has an input/output node and a driver. The driver has a first transistor and a second transistor. A first source/drain node of the first transistor is coupled to the input/output node. A second source/drain node of the first transistor forms a first interior node capable of accumulating charge when electrically floating. A first current flow control circuit is coupled to a discharge node and the second source/drain node of the first transistor. The first current flow control circuit is electrically oriented in a bias direction for allowing accumulated charge to discharge from the first interior node via the first current flow control circuit to the discharge node. | 02-03-2011 |
20110058290 | SHARED ELECTROSTATIC DISCHARGE PROTECTION FOR INTEGRATED CIRCUIT OUTPUT DRIVERS - A system for protecting metal oxide semiconductor field effect transistor (MOSFET) output drivers within an integrated circuit (IC) from an electrostatic discharge (ESD) includes a first MOSFET output driver and a second MOSFET output driver positioned within a common IC diffusion material. The system includes a contact ring coupled to the common IC diffusion material and arranged along an outer edge of a perimeter surrounding the MOSFET output drivers. A centroid of each MOSFET output driver is common with a centroid of the perimeter surrounding both MOSFET output drivers. Each MOSFET output driver has a value of substrate resistance (R | 03-10-2011 |
20110113401 | T-COIL NETWORK DESIGN FOR IMPROVED BANDWIDTH AND ELECTROSTATIC DISCHARGE IMMUNITY - A method of generating a circuit design comprising a T-coil network includes determining inductance for inductors and a parasitic bridge capacitance of the T-coil network. The parasitic bridge capacitance is compared with a load capacitance metric that depends upon parasitic capacitance of a load coupled to an output of the T-coil network. An amount of electrostatic discharge (ESD) protection of the circuit design that is coupled to the output of the T-coil network and/or a parameter of the inductors of the T-coil network is selectively adjusted according to the comparison. The circuit design, which can specify inductance of the inductors, the amount of ESD protection, and/or the width of windings of the inductors, is outputted. | 05-12-2011 |
20110147949 | HYBRID INTEGRATED CIRCUIT DEVICE - An embodiment of a method to form a hybrid integrated circuit device is described. This embodiment of the method comprises: forming a first die using a first lithography, where the first die is on a substrate; and forming a second die using a second lithography, where the second die is on the first die. The first lithography used to form the first die is a larger lithography than the second lithography used to form the second die. The first die is an IO die. | 06-23-2011 |
20120002392 | ELECTRO-STATIC DISCHARGE PROTECTION FOR DIE OF A MULTI-CHIP MODULE - Electro-static discharge (“ESD”) protection for a die of a multi-chip module is described. A contact has an externally exposed surface after formation of the die and prior to assembly of the multi-chip module. The contact is for a die-to-die interconnect of the multi-chip module. The contact is for an internal node of the multi-chip module after the assembly of the multi-chip module. A driver circuit is coupled to the contact and has a first input impedance. A discharge circuit is coupled to the contact for electrostatic discharge protection of the driver circuit and has a first forward bias impedance associated with a first discharge path. The first forward bias impedance is a fraction of the first input impedance. | 01-05-2012 |
20120188671 | T-COIL NETWORK DESIGN FOR IMPROVED BANDWIDTH AND ELECTROSTATIC DISCHARGE IMMUNITY - An embodiment of a circuit is described that includes a first inductor comprising a first end and a second end, where the first end of the first inductor forms an input node of the circuit. The embodiment of the circuit further includes a second inductor comprising a first end and a second end, where the second end of the first inductor is coupled to the first end of the second inductor forming an output node of the circuit; a resistor coupled to the second end of the second inductor; and an electrostatic discharge structure coupled to the output node and configured to provide an amount of electrostatic discharge protection, where the amount of electrostatic discharge protection is based on a parasitic bridge capacitance and a load capacitance metric. | 07-26-2012 |
20120248569 | INTERPOSER HAVING AN INDUCTOR - An embodiment of a multichip module is disclosed. For this embodiment of a multichip module, a semiconductor die and an interposer are included. The interposer has conductive layers, dielectric layers, and a substrate. Internal interconnect structures couple the semiconductor die to the interposer. External interconnect structures are for coupling the interposer to an external device. A first inductor includes at least a portion of one or more of the conductive layers of the interposer. A first end of the first inductor is coupled to an internal interconnect structure of the internal interconnect structures. A second end of the first inductor is coupled to an external interconnect structure of the external interconnect structures. | 10-04-2012 |
20130020675 | INDUCTIVE STRUCTURE FORMED USING THROUGH SILICON VIAS - An inductor for an integrated circuit can include a first turn comprising a first through silicon via (TSV) coupled to a second TSV. The inductor can include a third TSV coupled to the second TSV. | 01-24-2013 |
20130215541 | HIGH VOLTAGE RC-CLAMP FOR ELECTROSTATIC DISCHARGE (ESD) PROTECTION - In accordance with some embodiments, an electrostatic discharge (ESD) protection circuit for high-voltage power rails includes an RC-triggered clamp having an RC-circuit having a resistor coupled between a first node and a second node, and a capacitor coupled between the second node and a third node. The RC-triggered clamp also has a transistor with a first source/drain, a gate, and a second source/drain, wherein the first source/drain is coupled to the first node, and the second source/drain is coupled to the third node. The RC-triggered clamp also has an inverter, wherein an input of the inverter is coupled to the second node, and an output of the inverter is coupled to the gate of the transistor. The ESD protection circuit also includes one or more forward-biased diodes coupled in series between a supply node and the first node. | 08-22-2013 |
20140048887 | INTEGRATED CIRCUIT HAVING IMPROVED RADIATION IMMUNITY - An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; an n-well formed on the substrate; a p-well formed on the substrate; and a p-tap formed in the p-well adjacent to the n-well, wherein the p-tap extends between circuit elements formed in the n-well and circuit elements formed in the p-well, and is coupled to a ground potential. A method of forming an integrated circuit having improved radiation immunity is also described. | 02-20-2014 |
20140145293 | INTEGRATED CIRCUIT HAVING IMPROVED RADIATION IMMUNITY - An integrated circuit having improved radiation immunity is described. The integrated circuit comprises a substrate; a P-well formed on the substrate and having N-type transistors of a memory cell; and an N-well formed on the substrate and having P-type transistors of the memory cell; wherein the N-well has minimal dimensions for accommodating the P-type transistors. | 05-29-2014 |
20140198416 | CIRCUIT FOR AND METHOD OF ENABLING THE DISCHARGE OF ELECTRIC CHARGE IN AN INTEGRATED CIRCUIT - A circuit for enabling the discharge of electric charge in an integrated circuit is described. The circuit comprises an input/output pad coupled to a first node; a first diode coupled between the first node and a ground node; a transistor coupled in parallel with the first diode between the first node and ground node; and a resistor coupled between a body portion of the transistor and the ground node. A method of enabling the discharge of electric charge is also described. | 07-17-2014 |
20150069577 | REMOVAL OF ELECTROSTATIC CHARGES FROM INTERPOSER FOR DIE ATTACHMENT - A wafer includes a first interposer having a first patterned metal layer and a second interposer having a second patterned metal layer. The wafer includes a metal connection in a scribe region of the wafer that electrically couples the first patterned metal layer of the first interposer with the second patterned metal layer of the second interposer forming a global wafer network. The wafer further includes a probe pad located in the scribe region that is electrically coupled to the global wafer network. | 03-12-2015 |