Patent application number | Description | Published |
20090276330 | Low-Power Subsystem for Portable Computers - A low power subsystem for a portable computer is described. In one example, the portable computer includes a computer system and low power multimedia center. The computer system includes a central processing unit, a system memory, a mass storage device, and a user interface, the computer system having a low-power mode in which the CPU, system memory, and user interface are inactive. The low-power multimedia center includes a low power processor coupled to the mass storage device, a low power memory coupled to the low power processor, a miniature display to display multimedia from the mass storage device, and an external user interface coupled to the processor, independent of the computer system to control the displaying of multimedia. | 11-05-2009 |
20110059772 | Method and Device for Communicating Data - A wireless device is disclosed. The wireless device includes a wireless communication module, a data storage module, and a controller for controlling the storage and/or retrieval of data from the data storage module. The wireless communication module communicates with each of a plurality of remote devices and the data storage module defines a first storage area and a second storage area. The controller controls the communication of data between the first storage area and the remote device, and the second storage area and the remote device dependent upon access rights associated with the remote device. The first storage area typically defines a public storage area with which data is exchanged in a relatively free manner, and the second storage area typically defines a private storage area with which data is exchanged in a relatively restricted manner. | 03-10-2011 |
Patent application number | Description | Published |
20090019185 | Non Main CPU/OS Based Operational Environment - A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state. | 01-15-2009 |
20090083554 | DYNAMIC CORE SWAPPING - An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level. | 03-26-2009 |
20100083013 | Various Methods and Apparatuses for Power States in a Controller - Various methods, apparatuses, and systems are described in which a chipset controller has circuitry to control communications with a peripheral device in a computing device. The chipset controller has logic configured 1) to detect a plug-in event when the peripheral device connects to the chipset controller and 2) to transition the chipset controller from a low power consumption state to a higher power consumption state based on the logic detecting the plug-in event. | 04-01-2010 |
20100164968 | HYBRID GRAPHICS DISPLAY POWER MANAGEMENT - Some embodiments describe techniques that relate to hybrid graphics display power management. In one embodiment, data corresponding to one or more image frames of a video stream are stored in a local frame buffer. A display device (e.g., an LCD) may then be driven based on the stored data in the local frame buffer or a video stream from a graphics controller. Other embodiments are also described. | 07-01-2010 |
20120210036 | NON MAIN CPU/OS BASED OPERATIONAL ENVIRONMENT - A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state. | 08-16-2012 |
20130297909 | DYNAMIC CORE SWAPPING - An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a program at a first performance level. The first core stops executing the program when a triggering event occurs. A second core has a second instruction set compatible with the first instruction set and has a second performance level different than the first performance level. The second core is in a power down state when the first core is executing the program. A circuit powers up the second core after the first core stops executing the program such that the second core continues executing the program at the second performance level. | 11-07-2013 |
20130346664 | NON MAIN CPU/OS BASED OPERATIONAL ENVIRONMENT - A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state. | 12-26-2013 |
20140185156 | POWER CONSERVATION BASED ON HARD DISK ROTATIONAL INERTIA - Various embodiments are generally directed recurringly cycling the driving of a platter media of a hard drive with a motor, allowing rotation of the platter media to slow only to a threshold rotational speed to balance power conservation with delays in accessing data. A method comprises driving platter media of a hard drive to rotate at a selected normal rotational speed, retrieving data stored on the platter media when the platter media rotates at the normal rotational speed, ceasing to drive the platter media to rotate to allow the platter media to rotate under rotational inertia imparted to the platter media, monitoring a current rotational speed of the platter media, and resuming driving the platter media to rotate based on the current rotational speed falling to a lower threshold rotational speed selected to be less than the normal rotational speed. Other embodiments are described and claimed. | 07-03-2014 |
Patent application number | Description | Published |
20080244287 | Platform communication protocol - A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state. | 10-02-2008 |
20090077307 | DRAM selective self refresh - In some embodiments, an electronic apparatus comprises a communication interface, an input/output interface, a processor, and logic to collect, in the electronic apparatus, a first identifier associated with a first communication device and second identifier associated with a second communication device, logic to establish a communication connection between the electronic apparatus and the first communication device, and logic to initiate, in the electronic apparatus, a connection request for a communication connection between the first communication device and the second communication device. Other embodiments may be described. | 03-19-2009 |
20090083561 | Dynamic power management of dimms - In some embodiments, an electronic apparatus comprises a processor, at least one non-volatile memory module, and logic to activate a first DIMM while placing at least a second DIMM in a sleep mode, assign operating system memory to grow from a first location in a first DIMM device, assign application memory to grow from a second location in the first DIMM device, mark at least one DIMM boundary in the first DIMM device, generate a page fault when at least one of the operating system memory or the application memory crosses the DIMM boundary; and in response to the page fault, activate at least a second DIMM in the plurality of DIMMs in the electronic device. | 03-26-2009 |
20090089606 | Opportunistic initiation of data traffic - A method for trafficking data based at least in part on a power condition of a system resource. In one embodiment of the invention, a data trafficking device initiates data traffic in response to a detecting of an indication of the power condition. In another embodiment of the invention, the detected indication is independent of any data traffic of the data trafficking device. | 04-02-2009 |
20090172270 | DEVICE, SYSTEM, AND METHOD OF MEMORY ALLOCATION - Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System. | 07-02-2009 |
20100080218 | Protocol extensions in a display port compatible interface - Contents of extension packets of a DisplayPort specification are described that can permit a computer to control a target device. In one example, an extension packet controls the target device in at least one of power consumption, image rendering, and register updating. | 04-01-2010 |
20110047326 | DRAM SELECTIVE SELF REFRESH - In some embodiments, an electronic apparatus comprises a communication interface, an input/output interface, a processor, and logic to collect, in the electronic apparatus, a first identifier associated with a first communication device and second identifier associated with a second communication device, logic to establish a communication connection between the electronic apparatus and the first communication device, and logic to initiate, in the electronic apparatus, a connection request for a communication connection between the first communication device and the second communication device. Other embodiments may be described. | 02-24-2011 |
20110047395 | Platform Communication Protocol - A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state. | 02-24-2011 |
20110196998 | PROTOCOL EXTENSIONS IN A DISPLAY PORT COMPATIBLE INTERFACE - A computer can control a target device using a packet format described herein. In one example, an extension packet controls the target device in at least one of power consumption, image rendering, and register updating. | 08-11-2011 |
20120089772 | DEVICE, SYSTEM, AND METHOD OF MEMORY ALLOCATION - Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System. | 04-12-2012 |
20120117285 | PROTOCOL EXTENSIONS IN A DISPLAY PORT COMPATIBLE INTERFACE - A computer can control a target device using a packet format described herein. In one example, an extension packet controls the target device in at least one of power consumption, image rendering, and register updating. | 05-10-2012 |
20140115248 | DEVICE, SYSTEM, AND METHOD OF MEMORY ALLOCATION - Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random Access Memory (DRAM) units to store data, wherein each DRAM unit includes a plurality of banks and each bank is divided into a plurality of sub-banks; and a memory management unit to allocate a set of interleaved sub-banks of said DIMM to a memory page of an Operating System, wherein a combined memory size of the set of interleaved sub-banks is equal to a size of the memory page of the Operating System. | 04-24-2014 |