Patent application number | Description | Published |
20120095885 | Global Treasury Monitoring System - A global treasury monitoring system can provide a single centralized system of record for maintaining and updating global treasury limits to enable an organization to consistently allocate, apply and manage such limits across multiple types of platforms. Through a single system of record for the management of global treasury limits, an organization may comprehensively assess its risk exposure at any given time and make adjustments to limits on a real-time basis in response to rapidly-changing market conditions. The global treasury monitoring system can provide an organization with the ability to access, evaluate and reconfigure recorded treasury limits in real-time through various graphical user-interfaces (GUIs) accessible to users at various global locations. As treasury limits are utilized the system may update the availability of such limits so that an organization's risk exposure may be constantly monitored and assessed. The system also provides an organization with additional flexibility in programming a client's treasury limits to match the client's various liquidity needs around the globe while also managing the amount of the risk that the organization is willing to take on to attain appropriate returns. | 04-19-2012 |
20120095913 | Overdraft Payment Balance Exception Processing - A system for managing and processing exceptions to shared global treasury limits across multiple different platforms can be utilized by an organization to eliminate inconsistent client experiences and increase overall operating efficiency. A management and processing system can decision transactions of clients (e.g., customers, users, members, account-holders, clients, etc.) through a combination of straight-through and manual processes that are utilized according to select qualifying criteria. The system provides for auto-decisioning of low-risk, low-amount transactions while enabling authorized users to manually decision and otherwise manage transactions through various workflow-driven graphical user interfaces (GUIs). The GUIs can be configured to allow transaction approvers to standardize workflow for manual processing and approval of transactions that cannot be entirely decisioned by, or are exempt from, automated straight-through processing and can further be configured to provide users with numerous viewing, reporting, routing, tracking and decision override capabilities. | 04-19-2012 |
Patent application number | Description | Published |
20100137159 | Simple Tests for Rapid Detection of Canine Parvovirus Antigen and Antibodies - Slide agglutination tests (SATs) and slide inhibition tests (SITs) provide rapid detection, quantitation and strain identification of red blood cell (RBC) agglutinating viruses such as canine parvovirus (CPV) in biological samples. The tests are rapid, low-cost, and easy to use. These tests do not require any expensive equipment and can thus be used to monitor infections and antibody titers under field conditions. The tests can be modified to detect results using fluorescence (FSAT). FSAT is useful for rapid high-throughput screening (HTS) of libraries of small molecules and/or chemical compounds to identify antiviral compounds useful for the treatment of diseases caused by emerging hemaglutinating viruses that infect animals and humans. | 06-03-2010 |
20100196420 | IMMUNOGENIC COMPOSITIONS, VACCINES AND DIAGNOSTICS BASED ON CANINE DISTEMPER VIRUSES CIRCULATING IN NORTH AMERICAN DOGS - Immunogenic compositions and broad-spectrum vaccines containing newly identified isolates of canine distemper virus (CDV) collected from a geographic area are provided. The newly identified isolates exhibit attributes of both European wildlife lineage CDV and one or both of Arctic and American-2 lineage CDV. Therefore, the vaccines are broadly protective against infection with European wildlife lineage CDV and either Arctic lineage CDV or American-2 lineage CDV, or both Arctic and American-2 lineage CDV. | 08-05-2010 |
20120121645 | SUPRALINGUAL VACCINES AND APPLICATORS - Solid and semi-solid formulations are used for supralingual administration of vaccines to animals. The formulations, which comprise antigens dispersed in a solid or semi-solid matrix, or paste, are delivered via supralingual applicators. The supralingual applicators are designed so as to position the antigen-containing matrix directly on the dorsal surface of the tongue during vaccine delivery. Upon exposure to saliva and to suckling and/or licking action of the tongue, the matrix dissolves and releases antigens to the tongue. In some embodiments, the antigens are viruses, for example, attenuated viruses that are capable of infecting cells of the tongue, e.g. canine parvoviruses which infect basal tongue cells. The supralingual applicators are especially useful for the delivery of vaccines to newborn animals. | 05-17-2012 |
20120201848 | ISOLATION OF A VIRUS RELATED TO CANINE PARVOVIRUS-2 FROM A RACCOON - Vaccines preparations against canine parvovirus are provided. The vaccines include a novel canine parvovirus-2 isolated from a raccoon, and related nucleic acids and proteins. | 08-09-2012 |
20120263756 | VACCINES CONTAINING CANINE PARVOVIRUS GENETIC VARIANTS - Canine parvovirus vaccines and diagnostics and methods for their use are provided. The vaccines are effective against emerging canine parvovirus variants. | 10-18-2012 |
Patent application number | Description | Published |
20090327794 | Single Interface Access to Multiple Bandwidth and Power Memory Zones - In an embodiment, a system comprises a first memory module interface unit (MMIU) configured to couple to a first one or more memory modules, and a second MMIU configured to couple to a second one or more memory modules. The first MMIU is configured to operate the first one or more memory modules at a first frequency and the second MMIU is configured to concurrently operate the second one or more memory modules at a second operating frequency different from the first operating frequency. | 12-31-2009 |
20100031075 | Memory Power Profiling - In an embodiment, an apparatus comprises one or more registers and a control unit coupled to the one or more registers. The control unit is configured to monitor a power state in one or more memory modules during execution of an application, and to store data generated during the monitoring in the one or more registers. In an embodiment, a system comprises a memory controller and a plurality of memory module interface units (MMIUs) coupled to the memory controller. Each of the plurality of MMIUs: is coupled to a respective plurality of memory modules; comprises one or more registers; is configured to monitor a power state in the respective plurality of memory modules during execution of an application; and is configured to store data generated during the monitoring in the one or more registers. | 02-04-2010 |
20100293420 | CACHE COHERENT SUPPORT FOR FLASH IN A MEMORY HIERARCHY - System and method for using flash memory in a memory hierarchy. A computer system includes a processor coupled to a memory hierarchy via a memory controller. The memory hierarchy includes a cache memory, a first memory region of random access memory coupled to the memory controller via a first buffer, and an auxiliary memory region of flash memory coupled to the memory controller via a flash controller. The first buffer and the flash controller are coupled to the memory controller via a single interface. The memory controller receives a request to access a particular page in the first memory region. The processor detects a page fault corresponding to the request and in response, invalidates cache lines in the cache memory that correspond to the particular page, flushes the invalid cache lines, and swaps a page from the auxiliary memory region to the first memory region. | 11-18-2010 |
20100316065 | METHOD AND APPARATUS FOR MODULATING THE WIDTH OF A HIGH-SPEED LINK - The described embodiments include a system that modulates the width of a high-speed link. The system includes a transmitter circuit coupled to a high-speed link that includes N serial lanes. During operation, while using a first number of lanes to transmit frames on the high-speed link, the transmitter circuit determines a second number of lanes to be used to transmit frames on the high-speed link based on a bandwidth demand on the high-speed link. The transmitter circuit then sends an indicator of the second number of lanes to a receiver on the high-speed link. Upon receiving an error-free acknowledgment of the indicator from the receiver, starting from a predetermined frame, the transmitter circuit transmits subsequent frames on the high-speed link using the second number of lanes. | 12-16-2010 |
20100332727 | EXTENDED MAIN MEMORY HIERARCHY HAVING FLASH MEMORY FOR PAGE FAULT HANDLING - A computer system with flash memory in the main memory hierarchy is disclosed. In an embodiment, the computer system includes at least one processor, a memory management unit coupled to the at least one processor, and a random access memory (RAM) coupled to the memory management unit. The computer system may also include a flash memory coupled to the memory management unit, wherein the computer system is configured to store at least a subset of a plurality of pages in the flash memory during operation. Responsive to a page fault, the memory management unit may determine, without invoking an I/O driver, if a requested page associated with the page fault is stored in the flash memory and further configured to, if the page is stored in the flash memory, transfer the page into RAM. | 12-30-2010 |
20100332775 | HYBRID INTERLEAVING IN MEMORY MODULES - A memory system that interleaves storage of data across and within a plurality memory modules is described. The memory system includes a hybrid interleaving mechanism which maps physical addresses to locations within memory modules and ranks so that physical addresses for a given page all map to the same memory module, and physical addresses for the given page are interleaved across the plurality of ranks which comprise the same memory module. | 12-30-2010 |
20140095468 | HARDWARE FOR TABLE SCAN ACCELERATION - Techniques for processing a query are provided. One or more operations that are required to process a query are performed by a coprocessor that is separate from a general purpose microprocessor that executes query processing software. The query processing software receives a query, determines one or more operations that are required to be executed to fully process the query, and issues one or more commands to one or more coprocessors that are programmed to perform one of the operations, such as a table scan operation and/or a lookup operation. The query processing software obtains results from the coprocessor(s) and performs one or more additional operations thereon to generate a final result of the query. | 04-03-2014 |
20140095651 | Memory Bus Protocol To Enable Clustering Between Nodes Of Distinct Physical Domain Address Spaces - A system and method for transferring data and messages between nodes in a cluster is disclosed. Each node in the cluster is a separate physical domain but is connected to other nodes in the cluster through point-to-point high speed links. Each side of a link is coupled to a coprocessor which facilitates the movement of data between and among the nodes. Because each physical domain is separate from any other domain, the coprocessor in a physical domain uses a certificate, called and RKey, to obtain permission to transfer data to another physical domain. When an RKey is received from another physical domain, the coprocessor in the receiving domain validates the key and obtains the physical addresses associated with the key so that it can provide or accept the remote data. Data transfers between pairs of remote nodes in the cluster are permitted as well. | 04-03-2014 |
20140095805 | REMOTE-KEY BASED MEMORY BUFFER ACCESS CONTROL MECHANISM - A system and method implementing revocable secure remote keys is disclosed. A plurality of indexed base secrets is stored in a register of a coprocessor of a local node coupled with a local memory. When it is determined that a selected base secret expired, the base secret stored in the register based on the base secret index is changed, thereby invalidating remote keys generated based on the expired base secret. A remote key with validation data and a base secret index is received from a node requesting access to the local memory. A validation base secret is obtained from the register based on the base secret index. The coprocessor performs hardware validation on the validation data based on the validation base secret. Hardware validation fails if the base secret associated with the base secret index has been changed in the register of the selected coprocessor. | 04-03-2014 |