Patent application number | Description | Published |
20100261033 | Copper Foil for Printed Circuit Board and Copper Clad Laminate for Printed Circuit Board - Provided is a copper foil for a printed circuit board comprising a layer including nickel, zinc, a compound of nickel and that of zinc (hereinafter referred to a “nickel zinc layer”) on a roughened surface of a copper foil, and a chromate film layer on the nickel zinc layer, wherein the zinc add-on weight per unit area of the nickel zinc layer is 180 μg/dm | 10-14-2010 |
20110259848 | Rolled Copper Foil or Electrolytic Copper Foil for Electronic Circuit, and Method of Forming Electronic Circuit Using Same - Provided is a rolled copper foil or electrolytic copper foil for an electronic circuit to be used for forming a circuit by etching, wherein the rolled copper foil or the electrolytic copper foil comprises a nickel alloy layer with lower etching rate than copper, which is formed on an etching side of the copper foil, and the nickel alloy layer contains zinc. This invention aims to prevent sagging caused by the etching, to form a uniform circuit having the intended circuit width, and to shorten the time of forming a circuit by etching as much as possible, when forming a circuit by etching a copper foil of the copper-clad laminate; and also aims to make the thickness of the nickel alloy layer as thin as possible, to inhibit oxidation when exposed to heat, to prevent tarnish (discoloration) known as “YAKE”, to improve the etching properties in pattern etching, and to prevent the occurrence of short circuits and defects in the circuit width. | 10-27-2011 |
20110284496 | Method of Forming Electronic Circuit - Provided is a method of forming an electronic circuit, wherein a nickel or nickel alloy layer is formed on an etching side of a rolled copper foil or an electrolytic copper foil, the rolled copper foil or the electrolytic copper foil is bonded to a resin substrate to obtain a copper-clad laminate, a resist pattern for forming a circuit is subsequently applied on the copper foil, any unwanted portion of the copper foil and the nickel or nickel alloy layer of the copper-clad laminate other than the portion to which the resist pattern was applied is removed using an etching solution of an aqueous ferric chloride, the resist is further removed, and soft etching is additionally performed in order to remove the remnant nickel or nickel alloy layer and thereby form a circuit in which the space between copper circuit lines is of a width that is double or more from the thickness of copper. This invention aims to form a circuit with a uniform circuit width, improve the etching properties in pattern etching, and prevent the occurrence of short circuits and defects in the circuit width. | 11-24-2011 |
20110293960 | Rolled Copper Foil or Electrolytic Copper Foil for Electronic Circuit, and Method of Forming Electronic Circuit using same - Provided is a rolled copper foil or electrolytic copper foil for an electronic circuit to be used for forming a circuit by etching, wherein the copper foil comprises a heat resistance layer composed of zinc or zinc alloy or its oxide formed on an etching side of the rolled copper foil or electrolytic copper foil, and a layer of nickel or nickel alloy, which is a metal or alloy with a lower etching rate than copper, formed on the heat resistance layer. This invention aims to prevent sagging caused by the etching, to form a uniform circuit having the intended circuit width, and to shorten the time of forming a circuit by etching as much as possible, when forming a circuit by etching a copper foil of the copper-clad laminate; and also aims to make the thickness of the nickel or nickel alloy layer as thin as possible, to inhibit oxidation when exposed to heat, to prevent tarnish (discoloration) known as “YAKE”, to improve the etching properties in pattern etching, and to prevent the occurrence of short circuits and defects in the circuit width. | 12-01-2011 |
20110297641 | Rolled Copper Foil or Electrolytic Copper Foil for Electronic Circuit, and Method of Forming Electronic Circuit using same - Provided is a rolled copper foil or electrolytic copper foil for an electronic circuit to be used for forming a circuit by etching, wherein the copper foil comprises a nickel or nickel alloy layer with a lower etching rate than copper formed on an etching side of the rolled copper foil or electrolytic copper foil, and a heat resistance layer composed of zinc or zinc alloy or its oxide formed on the nickel or nickel alloy layer. This invention aims to prevent sagging caused by the etching, to form a uniform circuit having the intended circuit width, and to shorten the time of forming a circuit by etching as much as possible, when forming a circuit by etching a copper foil of the copper-clad laminate; and also aims to make the thickness of the nickel or nickel alloy layer as thin as possible, to inhibit oxidation when exposed to heat, to prevent tarnish (discoloration) known as “YAKS”, to improve the etching properties in pattern etching, and to prevent the occurrence of short circuits and defects in the circuit width. | 12-08-2011 |
20110300401 | Rolled Copper Foil or Electrolytic Copper Foil for Electronic Circuit, and Method of Forming Electronic Circuit using same - A rolled copper foil or electrolytic copper foil for an electronic circuit to be used for forming a circuit by etching, characterized in comprising a layer of metal of one or more types among a platinum group, gold and silver with an etching rate that is lower than the copper formed on an etching surface side of the rolled copper foil or the electrolytic copper foil, or alternatively comprising a layer of an alloy having the above-described metal as its main component. This invention aims to achieve the following upon forming a circuit by etching a copper foil of a copper clad laminate; specifically, to prevent sagging caused by the etching; to form a uniform circuit of the intended circuit width; to shorten the time of forming a circuit by etching as much as possible; to improve the etching properties in pattern etching; and to prevent the occurrence of short circuits and defects in the circuit width. | 12-08-2011 |
20120135266 | Copper Foil and Method for Producing Same - A copper foil comprising a plated layer containing nickel and zinc on a copper foil made of an electrolytic copper foil or a rolled copper foil, and a chromium plated layer on the plated layer containing nickel and zinc, wherein the zinc in the plated layer containing nickel and zinc is made of zinc oxide and metal zinc, and the ratio of metal zinc in the zinc oxide and metal zinc is 50% or less. This invention relates to a copper foil for a flexible printed board formed with a polyimide-based resin layer and in particular provides a copper foil having superior adhesive strength between the copper foil and the polyimide-based resin layer, having acid resistance and tin plating solution resistance, having high peel strength, comprising favorable etching properties and gloss level, and suitable for use in a flexible printed board capable of achieving fine patterning of wiring. | 05-31-2012 |
20120148862 | Copper Foil for Printed Circuit Board and Copper Clad Laminate for Printed Circuit Board - A copper foil for a printed circuit board is provided. The copper foil includes a layer including nickel, zinc, a compound of nickel and that of zinc (hereinafter referred to as a “nickel zinc layer”) on a roughened surface of a copper foil and a chromate film layer on the nickel zinc layer. The zinc add-on weight per unit area of the nickel zinc layer is 180 μg/dm | 06-14-2012 |
20120318568 | ELECTRONIC CIRCUIT, METHOD FOR FORMING SAME, AND COPPER CLAD LAMINATE FOR FORMING ELECTRONIC CIRCUIT - Provided is an electronic circuit as a laminated body configured from a layer (A) which is made of a copper or copper alloy foil formed on one surface or both surfaces of a resin substrate, a copper or copper alloy plated layer (B) formed on a part or whole surface of the (A) layer, a plated layer (C) formed on a part or whole surface of the (B) layer and having a slower etching rate than that of copper relative to a copper etching solution, and a copper or copper alloy plated layer (D) formed on the layer (C) and which has a thickness of 0.05 μm or more and less than 1 μm, and which is made of a copper circuit formed by etching and removing a part of the laminated portion of the (A) layer, the (B) layer, the (C) layer and the (D) layer up to the resin substrate surface. It is thereby possible to form a circuit having a uniform circuit width, improve the etching properties in pattern etching, and prevent the occurrence of short-circuits and defects in the circuit width. | 12-20-2012 |
20130011734 | COPPER FOIL FOR NEGATIVE ELECTRODE CURRENT COLLECTOR OF SECONDARY BATTERY - Provided is a copper foil for a negative electrode current collector of secondary battery, wherein: roughening treatment is performed to both front and rear surfaces of a rolled copper alloy foil; an average surface roughness Ra of both the front and rear surfaces based on laser microscope measurement is 0.04 to 0.20 μm; and the ratio of surface area factor is within a range of 1.0<(C)/(C′)<1.1, when a three-dimensional surface area upon measuring the roughened surfaces with a laser microscope is (A), a two-dimensional area as a projected area upon measuring the three-dimensional surface area is (B), and a calculated value of (A)/(B) is expressed in (C), and when a three-dimensional surface area upon measuring the surfaces of a non-roughened rolled copper or copper alloy foil with a laser microscope is (A′), a two-dimensional area as a projected area upon measuring the three-dimensional surface area is (B′), and a calculated value of (A′)/(B′) is expressed in (C′). This invention aims to provide a copper foil for a negative electrode current collector of a secondary battery in which the adhesiveness of the secondary battery active material is superior, and which can reduce the variation in the area weight of the secondary battery active material, and has superior weather resistance and thermal resistance. | 01-10-2013 |
20130270218 | Rolled Copper Foil or Electrolytic Copper Foil for Electronic Circuit, and Method of Forming Electronic Circuit Using Same - A rolled copper foil or electrolytic copper foil for an electronic circuit to be used for forming a circuit by etching, characterized in comprising a layer of metal of one or more types among a platinum group, gold and silver with an etching rate that is lower than the copper formed on an etching surface side of the rolled copper foil or the electrolytic copper foil, or alternatively comprising a layer of an alloy having the above-described metal as its main component. The following can be achieved upon forming a circuit by etching a copper foil of a copper clad laminate: sagging caused by the etching is prevented; a uniform circuit of the intended circuit width is formed; the time required to form a circuit by etching is reduced; etching properties in pattern etching are improved; and the occurrence of short circuits and defects in the circuit width are prevented. | 10-17-2013 |
20140093743 | Liquid Crystal Polymer Copper-Clad Laminate and Copper Foil Used For Said Laminate - Provided is a copper-clad laminate obtainable by bonding a copper foil on which roughening treatment including copper-cobalt-nickel alloy plating is performed and a liquid crystal polymer to each other, wherein the copper-clad laminate is free from a roughening particle residue on a surface of the liquid crystal polymer resin after copper foil circuit etching. The copper-clad laminate obtainable by bonding a copper foil and a liquid crystal polymer to each other, wherein the copper foil includes a copper primary particle layer formed on a surface bonded to the liquid crystal polymer and a secondary particle layer formed on the primary particle layer and made from a ternary alloy including copper, cobalt, and nickel; the primary particle layer has an average particle size of 0.25 to 0.45 μm; and the secondary particle layer has an average particle size of 0.05 to 0.25 μm. | 04-03-2014 |
20150303040 | Tungsten Sintered Compact Sputtering Target and Tungsten Film Formed Using Said Target - A tungsten sintered compact sputtering target, wherein a molybdenum strength detected with a secondary ion mass spectrometer (D-SIMS) is equal to or less than 1/10000 of the tungsten strength. This invention aims to reduce the specific resistance of a tungsten film sputtered using the tungsten sintered compact target by reducing the molybdenum in the tungsten sintered compact sputtering target and adjusting the grain size distribution of the W powder that is used during sintering. | 10-22-2015 |
Patent application number | Description | Published |
20120126219 | ORGANIC ELECTROLUMINESCENT ELEMENT AND METHOD FOR PRODUCING THE SAME - An organic electroluminescent element including: a first electrode; at least one organic deposition layer; and a second electrode, the first electrode, the organic deposition layer, and the second electrode being formed in this order, wherein the organic deposition layer satisfies the relationship 0.09305-24-2012 | |
20130264547 | MATERIALS FOR AN ORGANIC ELECTROLUMINESCENCE ELEMENT, ELECTROLUMINESCENT, DISPLAY AND ILLUMINATING DEVICES USING THE ELEMENTS - An organic electroluminescent element including a substrate, a pair of electrodes including an anode and a cathode, disposed on the substrate, and at least one layer of organic layers including a light emitting layer, disposed between the electrodes, in which at least one of the organic layers contains a compound represented by the following general formula: | 10-10-2013 |
20130313531 | Organic Electroluminescent Element - Disclosed is an organic electroluminescent element which is excellent with respect to luminous efficiency and driving voltage and rarely undergoes initial luminance drop. Specifically disclosed is an organic electroluminescent element which comprises, on a substrate, a pair of electrodes composed of an anode and a cathode and a light-emitting layer arranged between the electrodes, and additionally comprises at least one organic layer arranged between the light-emitting layer and the cathode, where in the light-emitting layer contains, for example, a compound (A-1), and the at least one layer arranged between the light-emitting layer and the cathode contains, for example, a compound (e-4). | 11-28-2013 |
20140008621 | ORGANIC ELECTROLUMINESCENT DEVICES - An organic electroluminescent element that includes a light-emitting layer composed of a light-emitting composition containing at least one type of host material and at least one type of light-emitting material is provided. The host material is a fluorescent anthracene derivative, which fluoresces blue light under DC current with a current density of 25 mA/cm | 01-09-2014 |
20140291660 | Organic Electroluminescent Element, Material for Organic Electroluminescent Element and Light Emitting Device, Display Device, and Illumination Device, Each Employing Organic Electroluminescent Element - This application relates in part to an organic electroluminescent element including a substrate, a pair of electrodes including an anode and a cathode, disposed on the substrate, and an organic layer(s) including a light emitting layer, in which the organic layer(s) contains a compound represented by the following formula (1), in which R | 10-02-2014 |
Patent application number | Description | Published |
20080283970 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME - A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area. | 11-20-2008 |
20100197105 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME - A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area. | 08-05-2010 |
20120091565 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME - A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area. | 04-19-2012 |
20120220104 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME - A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area. | 08-30-2012 |
20140045320 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME - A method of forming a semiconductor IC includes forming grooves in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area. | 02-13-2014 |
20150279788 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME - A semiconductor substrate includes scribe and product regions, with grooves formed in the scribe region. The grooves are embedded with an insulating film to provide an isolation region, and an active region, including semiconductor elements, is formed in the product region. Dummy patterns are formed in the scribe region, which include a first dummy pattern and second dummy patterns for preventing dishing of the insulating film. The second dummy patterns are surrounded and defined by the isolation region. A target pattern for optical pattern recognition is arranged over the first dummy pattern, and includes a first conductive film. A plane area of the first dummy pattern is larger than a plane area of each of the second dummy patterns, and the first dummy pattern and the second dummy patterns are arranged in order from an edge of the semiconductor substrate toward the product region. | 10-01-2015 |
Patent application number | Description | Published |
20090060120 | X-RAY COMPUTED TOMOGRAPHY APPARATUS AND TOMOGRAPHIC METHOD - An X-ray CT apparatus detects a predetermined characteristic wave from each electrocardiographic waveform acquired from an electrocardiograph, predicts intervals with which the characteristic wave appears based on appearance times of the detected predetermined characteristic wave in each electrocardiographic waveform, and determines an X-ray irradiation start time based on the predicted interval time. After an instruction to start collection of X-ray intensity distribution data is received, if an appearance interval of a detected predetermined characteristic wave is within an acceptable normal-heartbeat range, it is determined as a normal heartbeat. If the appearance interval of the detected predetermined characteristic wave is outside the acceptable normal-heartbeat range, it is determined as an abnormal heartbeat. During a period after receiving the instruction to start the collection until reaching a time of starting the collection of X-ray detection information, when determined as an abnormal heartbeat, an X-ray irradiation start time is recalculated, and then determined. | 03-05-2009 |
20100020923 | X-RAY CT SCANNER AND IMAGE CREATING METHOD - In an X-ray CT scanner having an X-ray tube which applies an X-ray spreading in a body axis direction of a subject, and an X-ray detector having a wide imaging range which detects the X-ray passed through the subject and converts the detected X-ray into an electric signal, a desired image creation time is set by use of a specific CT value curve in a console input unit before scanning with the X-ray. After the scanning, data of the CT value change curve is generated based on the obtained projection data. An image creation range in the generated change curve is determined based on an image creation range set in the console input unit, and the image creation is performed in the image creation unit based on the determined image creation time. | 01-28-2010 |
20140323858 | MEDICAL IMAGE DIAGNOSTIC APPARATUS - A medical image diagnostic apparatus according to an embodiment includes an estimation unit, an extraction unit, and a specifying unit. The estimation unit estimates a position of a plaque in a blood vessel based on data of CT images constituting a time series, with the blood vessel being enhanced by a contrast medium. The extraction unit extracts regions constituting the blood vessel from the CT images. The specifying unit specifies stress values respectively corresponding to the regions based on a moving displacement due to cardiac pulsation in each of the regions, and specifies an exfoliation risk of the plaque based on an index indicating hardness of the plaque and the stress value in the region corresponding to the position of the plaque. | 10-30-2014 |
Patent application number | Description | Published |
20150257655 | MEDICAL IMAGE PROCESSING APPARATUS - A centerline extraction unit extracts at least two coronary artery centerline structures from at least two images respectively corresponding to at least two cardiac phases concerning a heart, an interpolation processing unit interpolates coronary artery centerline structures concerning other cardiac phases from the at least two extracted coronary artery centerline structures to generate coronary artery centerline structures respectively corresponding to a plurality of cardiac phases throughout one heartbeat of the heart, and a displacement distribution calculation unit calculates a plurality of displacement distributions between the respective cardiac phases from a plurality of coronary artery centerline structures throughout the one heartbeat. | 09-17-2015 |
20150262357 | MEDICAL IMAGE PROCESSING APPARATUS AND MEDICAL IMAGE PROCESSING METHOD - There is provided a medical image processing apparatus which includes a first extraction unit configured to extract coronary arteries depicted in images of a plurality of time phases relating to the heart, and to extract at least one stenosed part depicted in each coronary artery; a calculation unit configured to calculate a pressure gradient of each of the extracted coronary arteries, based on tissue blood flow volumes of the coronary arteries; a second extraction unit configured to extract an ischemic region depicted in the images; and a specifying unit configured to specify a responsible blood vessel of the ischemic region by referring to a dominance map, in which each of the extracted coronary arteries and a dominance territory are associated, for the extracted ischemic region, and to specify a responsible stenosis, based on the pressure gradient corresponding to a stenosed part in the specified responsible blood vessel. | 09-17-2015 |
20150262388 | MEDICAL IMAGE DIAGNOSTIC APPARATUS - According to one embodiment, a medical image diagnostic apparatus includes a storage memory, processing circuitry, and a display. The storage memory stores data of a plurality of FFR distribution maps constituting a time series regarding a coronary artery, and data of a plurality of morphological images corresponding to the time series. The processing circuitry converts the plurality of FFR distribution maps into a plurality of corresponding color maps, respectively. The display displays a plurality of superposed images obtained by superposing the plurality of color maps and the plurality of morphological images respectively corresponding in phase to the plurality of color maps. The display restricts display targets for the plurality of color maps based on the plurality of FFR distribution maps or the plurality of morphological images. | 09-17-2015 |
20150327780 | IMAGE PROCESSING APPARATUS, IMAGE PROCESSING METHOD, AND STORAGE MEDIUM - An image processing apparatus according to an embodiment includes a processing circuitry. The processing circuitry is configured to obtain images in a time series including images of a blood vessel of a subject and correlation information indicating a correlational relationship between physical indices of the blood vessel and function indices of the blood vessel related to vascular hemodynamics, calculate blood vessel morphology indices in a time series indicating morphology of the blood vessel of the subject, on a basis of the images in the time series, and identify a function index of the blood vessel of the subject, by using a physical index of the blood vessel of the subject obtained from the blood vessel morphology indices, on a basis of the correlation information. | 11-19-2015 |
20150356734 | BLOOD VESSEL ANALYSIS APPARATUS, MEDICAL IMAGE DIAGNOSIS APPARATUS, AND BLOOD VESSEL ANALYSIS METHOD - According to one embodiment, a structuring circuitry temporarily structures a dynamical model of analysis processing based on the time-series medical image. The identification circuitry identifies a latent variable of the dynamical model so that at least one of a prediction value of a blood vessel morphology and a prediction value of a bloodstream based on the temporarily structured dynamical model is in conformity with at least one of an observation value of the blood vessel morphology and an observation value of the bloodstream measured in advance. The analysis circuitry analyzes the dynamical model to which the identified latent variable is allocated. | 12-10-2015 |
Patent application number | Description | Published |
20090013241 | CONTENT REPRODUCING UNIT, CONTENT REPRODUCING METHOD AND COMPUTER-READABLE MEDIUM - A reproducing unit, comprising: a time control section for controlling time in order to reproduce content having time and date information in an order according to that time and date information; a content search section for searching for content having time and date information corresponding to a time defined by the time control section from a plurality of categories of content; a storage section for storing a plurality of the searched contents of differing categories; a time image creation section for creating a time image, for representing time information representing a specified range of time, controlled by the time control section, by a specified length, and representing that content of time and data information corresponding to that time and date information exists, including content information arranged at a position of the time information corresponding to the time information; and a reproduction control unit for performing control so that the stored content of different categories is reproduced at a timing corresponding to the category of the content, on the basis of time controlled by the time control section. | 01-08-2009 |
20110058087 | IMAGE CONTROL APPARATUS, IMAGE CONTROL METHOD, AND RECORDING MEDIUM - An image control apparatus which controls a search screen for searching a related image, comprises: an attribute display section setting a reference image and causing to display a specific condition in each of the attributes of the reference image; a related image display section causing to display the related image which has been searched by an image search section according to the specific attribute condition selected from among the displayed specific conditions; a search screen display section causing to display the search screen including at least the reference image, the specific condition in each of the attributes of the reference image, and the searched related image; and a change screen display section causing to display a change screen for changing the specific attribute condition to be used for the search to a condition except the specific condition in each of the attributes related to the reference image. | 03-10-2011 |
20150339801 | DISPLAY DEVICE AND DISPLAY METHOD - A display device comprises a display, a display control circuit for causing operation screens, for selection of setting items to be used from among a plurality of provided setting items, to be displayed on the display, and causing switching from the operation screen to another operation screen to be displayed, and an operation member for operating in order to switch from the operation screen to another operation screen, wherein the display control circuit causes display of change in display appearance of the setting items, when there is a switch from the operation screen to another operation screen. | 11-26-2015 |