Patent application number | Description | Published |
20120066696 | GENERIC HARDWARE AND SOFTWARE PLATFORM FOR ELECTRONIC DEVICES IN MULTIMEDIA, GRAPHICS, AND COMPUTING APPLICATIONS - A generic hardware and software platform for electronic devices in multimedia, graphics, and computing applications are disclosed. In one embodiment, the generic hardware platform includes one of a single bus link or multiple bus link. Further, the generic hardware platform includes one or more of a power module, a processor, a memory device, a security engine, an environmental device, a man machine interface (MMI) device and a medical device coupled to the one of the single bus link or multiple bus link via an associated interface. Furthermore, the generic hardware platform includes one or more of a storage device, a video/image input device, a video/image output device, an audio input device, an audio output device, a location, position, and motion device, a wireless communication channel, a wired communication channel, and a timer coupled to the one of the single bus link or multiple bus link via an associated interface. | 03-15-2012 |
20140040495 | SYSTEM AND METHOD FOR LOW DELAY FAST UPDATE FOR VIDEO STREAMING - A system and method for low delay fast update, using multiple fast update pictures, for video streaming are disclosed. In one embodiment, a fast update request is received from a media client via a network by a media server to recover from packet losses. Further, one or more low delay fast update frames are generated based on packet loss statistics obtained during a steady state video streaming session by the media server. Furthermore, the generated one or more low delay fast update frames are sent to the media client to recover from the packet losses by the media server. | 02-06-2014 |
Patent application number | Description | Published |
20090058480 | SCHEME FOR CONTROLLING RISE-FALL TIMES IN SIGNAL TRANSITIONS - A serial interface interacting with a transmission pad system circuitry wherein a differential impedance is reckoned across the system voltage source, includes a scheme for controlling transmitter rise-fall transitions (to selectively speed up or slow down transitions) without requiring additional timing controls or affecting reflection coefficient of the transmitter port. The scheme uses at least one pre-charged capacitor, e.g., PMOS capacitor, interacting with the transmitter pad and connected through resistances or otherwise across the differential impedance with a switch. A modified scheme uses first and second parallely connected PMOS capacitors connectable with the transmission pad by switches, which may be NMOS switches. The scheme may be used in a MIPI D-PHY compliant DSI transmitter operating at, for e.g. 800 Mbps, and low signal common-modes. The scheme controls signal transition times of high speed circuitry including transmitters and uses a DATA signal which is already available to the circuitry. | 03-05-2009 |
20090245439 | Output Buffer In The Presence Of Multiple Power Supplies - An output buffer providing a buffered output signal using multiple power supplies. The output signal is driven using a first power supply during a first interval, and using another (second) power supply during a second interval. In an embodiment, the first power supply is designed to be a high capacity supply, and drives the output signal during a substantial portion of a logic 0 to logic 1 transition. The second power supply is designed to be a low capacity supply, and drives the output during steady states (logic 0/logic 1). | 10-01-2009 |
20100066455 | SIGMA DELTA DIGITAL TO ANALOG CONVERTER WITH WIDE OUTPUT RANGE AND IMPROVED LINEARITY - A sigma delta DAC using a single DAC to generate a first analog quantity portion and a second analog quantity portion, having a strength respectively proportionate to the most significant bits (MSBs) and least significant bits (LSBs) of a received digital value. The two portions are added to generate an analog output representing the strength of the digital value. In an embodiment, the single DAC contains a set of current sources, with some of the current sources (determined by the value of the MSBs) being connected to provide the corresponding output currents on a first path. Some of the other current sources, determined by a value of the LSBs, are controlled to be connected to provide the corresponding output currents on a second path. The time durations the currents are connected to the second path, are determined by the output of a sigma delta modulator. | 03-18-2010 |
20110254603 | PHASE INTERPOLATOR AND A DELAY CIRCUIT FOR THE PHASE INTERPOLATOR - Phase interpolator and a delay circuit for the phase interpolator. The phase interpolator includes a variable delay circuit to rotate phase of an input clock to generate a phase rotated signal. The phase interpolator also includes a delay locked loop coupled to the variable delay circuit to generate a plurality of phase shifted outputs. The delay locked loop includes a plurality of delay elements. Each delay element includes a multiplexer and a delay cell coupled to the multiplexer. The multiplexer is configurable using a first control signal to output one of the phase rotated signal and a phase shifted output of the plurality of phase shifted outputs. The delay cell delays one of the phase rotated signal and the phase shifted output to generate another phase shifted output of the plurality of phase shifted outputs. | 10-20-2011 |
20120139595 | DELAY LOCKED LOOP WITH OFFSET CORRECTION - A delay locked loop (DLL) is calibrated to obtain a measure of offset error in the DLL. The offset error is compensated for in normal operation. In an embodiment, a current corresponding to the measure of offset is forced into one of a pair of paths carrying error signals representing a phase-mismatch between a reference signal and a feedback signal. In another embodiment, additional delay corresponding to the measure of offset is introduced on one of the pair of paths. Offset error is thus largely removed in normal operation of the DLL. The DLL employs an amplifier in place of a charge pump to remove systematic offset errors due to a charge pump. A phase detector in the DLL is designed such that an overlap interval of error outputs of the phase detector is at least half the period of the reference signal, thereby lending to high-frequency operation. | 06-07-2012 |
20120213314 | DIGITAL DEMODULATION OF PULSE-WIDTH MODULATED SIGNALS - A digital PWM demodulator includes a first set of delay cells to receive a PWM signal and to propagate the PWM signal in a forward direction for a first interval. Delayed signals obtained at the end of the first interval are propagated in the reverse direction through the delay cells for a second interval. A logic zero feeds into the last cell at the start of the second interval. The output of a last cell in the delay cells at the end of the second interval is indicative of a data value modulated on the PWM signal. The digital PWM demodulator includes a second set of delay cells designed to operate identical to the first set of delay cells. The first set of delay cells and the second set of delay cells in conjunction with additional digital circuitry demodulate alternate periods of the PWM signal. | 08-23-2012 |
20140169038 | DIGITAL ISOLATOR - Several circuits and methods for transferring an input data signal in a digital isolator are disclosed. In an embodiment, the digital isolator includes an isolation element, input circuit, and output circuit. The isolation element includes at least one input node and at least one output node, the input circuit is electronically coupled to the input node and generates modulated differential data signals based on modulating the input data signal on a carrier signal. The input circuit operates using a first supply voltage with respect to a first ground. The output circuit is electronically coupled to the output node to receive the modulated differential data signals, operates using a second supply voltage with respect to a second ground and includes a frequency-shift keying demodulator configured to generate a demodulated data signal in response to detection of presence of the carrier signal. The output circuit further generates an output data signal. | 06-19-2014 |
Patent application number | Description | Published |
20100225960 | METHOD AND SYSTEM FOR PRINTING AN ADVERTISEMENT WITH A DOCUMENT - Presented is a method and system for printing an advertisement with a document. The method includes receiving a print request for a document from a user, converting the requested document into a vector graphics format document, selecting at least one advertisement for inclusion into the vector graphics format document, recording the vector graphics format document into a print driver queue enabled to print advertisements, inserting at least one advertisement into the vector graphics format document and printing the advertisement with the vector graphics format document. | 09-09-2010 |
20110007347 | WEB PRINTING - One embodiment is a method that analyzes a print request that is transmitted over an internet and received at a cloud print system. The method then executes with priorities a list of job tasks to print the print request at a web-enabled printer. | 01-13-2011 |
20120140285 | CLOUD PRINTER WITH A COMMON USER PRINT EXPERIENCE - One embodiment is a portable electronic device that prints a document to a printer. A common user print experience is displayed regardless of a type of operating system installed on the portable electronic device. | 06-07-2012 |
20140063553 | METHOD OF MANAGING PRINT JOBS USING VIRTUAL PRINT IDENTITY - A method of managing print jobs addressed to a virtual print identity. The virtual print identity is associated with a first user, but not tied to a particular user device and the virtual print identity has at least one parameter relating to where the print job should be printed. | 03-06-2014 |
20150248264 | USING DEVICE IDENTIFICATION INFORMATION FOR PAYMENT VIA A PRINTER - A technique performed by a printer includes receiving identification information from a computing device. The identification information may be sent to a server, such as a content management server. The identification information can be used for payment. Payment confirmation, authorization to provide content, or content itself may be received from the server. | 09-03-2015 |
Patent application number | Description | Published |
20120099497 | TRANSITIONING FROM MIMO TO SISO TO SAVE POWER - Various example embodiments are disclosed. According to an example embodiment, an apparatus may include at least one processor and at least one memory. The at least one memory may include computer-executable code that, when executed by the processor, is configured to cause the apparatus to send a message to a node in wireless communication with the apparatus, the message indicating a transition by the apparatus from multiple-input multiple-output (MIMO) to single-input single-output (SISO), and transition from wireless MIMO communication with the node to wireless SISO communication with the node after sending the message to the node. | 04-26-2012 |
20130223220 | Flow Control for Constrained Wireless Access Points - Disclosed are various embodiments that provide flow control for resource-constrained wireless access points. An access point service provides access to a network for wireless clients by way of a wireless network transceiver. A stop instruction is generated in response to determining that the wireless network transceiver is unable to process data received from the wireless clients. The stop instruction is sent to to the wireless clients by way of the wireless network transceiver. The stop instruction configures the wireless clients to cease sending data to the access point service. | 08-29-2013 |
20130242836 | TRANSITIONING FROM MIMO TO SISO TO SAVE POWER - Various example embodiments are disclosed. According to an example embodiment, an apparatus may include at least one processor and at least one memory. The at least one memory may include computer-executable code that, when executed by the processor, is configured to cause the apparatus to send a message to a node in wireless communication with the apparatus, the message indicating a transition by the apparatus from multiple-input multiple-output (MIMO) to single-input single-output (SISO), and transition from wireless MIMO communication with the node to wireless SISO communication with the node after sending the message to the node. | 09-19-2013 |
20150351036 | TRANSITIONING FROM MIMO TO SISO TO SAVE POWER - Various example embodiments are disclosed. According to an example embodiment, an apparatus may include at least one processor and at least one memory. The at least one memory may include computer-executable code that, when executed by the processor, is configured to cause the apparatus to send a message to a node in wireless communication with the apparatus, the message indicating a transition by the apparatus from multiple-input multiple-output (MIMO) to single-input single-output (SISO), and transition from wireless MIMO communication with the node to wireless SISO communication with the node after sending the message to the node. | 12-03-2015 |
Patent application number | Description | Published |
20110261145 | Determining Buffer Size Based on Forward Error Correction Rate - Determining a buffer size in a videoconference. In some embodiments, one or more of various different error correction methods may be used in a videoconference. For example, forward error correction (FEC) may be used and/or retransmission of lost packets (ReTxLP) may be used, e.g., based on a packet loss threshold. Where FEC is used, a buffer size of a receiving videoconferencing device may be determined based on the FEC rate. Where ReTxLP is used, a buffer size of the receiving videoconferencing device may be determined based on a retransmission latency. | 10-27-2011 |
20110261146 | Determining Buffer Size Based on Retransmission Latency - Determining a buffer size in a videoconference. In some embodiments, one or more of various different error correction methods may be used in a videoconference. For example, forward error correction (FEC) may be used and/or retransmission of lost packets (ReTxLP) may be used, e.g., based on a packet loss threshold. Where FEC is used, a buffer size of a receiving videoconferencing device may be determined based on the FEC rate. Where ReTxLP is used, a buffer size of the receiving videoconferencing device may be determined based on a retransmission latency. | 10-27-2011 |