Kaluzhny
Mikhail Kaluzhny, Newton, MA US
Patent application number | Description | Published |
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20080204887 | FLEXIBLE SUBSTRATE WITH ETCHED LENS ARRAY - A flexible substrate having a plurality of lenses disposed in an array on a surface of the substrate wherein the lenses are formed by etching the substrate. | 08-28-2008 |
20100097678 | Servo Feedback Control Based on Designated Scanning Servo Beam in Scanning Beam Display Systems with Light-Emitting Screens - Scanning beam display systems that scan one servo beam and an excitation beam onto a screen that emits visible light under excitation of the light of the excitation beam and control optical alignment of the excitation beam based on positioning of the servo beam on the screen via a feedback control. | 04-22-2010 |
20110080723 | EDGE ILLUMINATION OF BEZELLESS DISPLAY SCREEN - One or more embodiments of the invention provide an apparatus and method for producing an image on a display screen that extends to the pixels or image elements disposed at the edge of the display screen. The display screen has an optical element with a thickness and an index of refraction that are selected to direct light to pixels or image elements disposed at the edge of the display screen without passing through the portion of the optical element that is blocked by a support frame or other structural member disposed on the rear surface of the display screen. Positioning such display screens together into a single screen assembly produces a tiled display having a much less noticeable grid pattern visible to the viewer. | 04-07-2011 |
Uri Kaluzhny, Ramat Beit Shemesh IL
Patent application number | Description | Published |
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20130054991 | PROCESSOR WITH DIFFERENTIAL POWER ANALYSIS ATTACK PROTECTION - A device including a processor to perform an operation yielding a result, the processor including a register including bit it storage elements and including a first and second section, each element being operative to store a bit value, and a power consumption mask module to determine whether the whole result can be completely written in half or less than half of the register, determine a balancing entry if the result can be completely written in half or less than half of the register, a write module to perform a single write operation to the register including writing the result and the balancing entry to the first and second section, respectively, if the result can be completely written in half or less than half of the register else writing the result of the operation across at least part of the first and second section. Related apparatus and methods are also described. | 02-28-2013 |
20130262825 | Obfuscated Hardware Multi-Threading - Obfuscating a multi-threaded computer program is carried out using an instruction pipeline in a computer processor by streaming first instructions of a first thread of a multi-threaded computer application program into the pipeline, the first instructions entering the pipeline at the fetch stage, detecting a stall signal indicative of a stall condition in the pipeline, and responsively to the stall signal injecting second instructions of a second thread of the multi-threaded computer application program into the pipeline. The injected second instructions enter the pipeline at an injection stage that is disposed downstream from the fetch stage up to and including the register stage for processing therein. The stall condition exists at one of the stages that is located upstream from the in injection stage. | 10-03-2013 |
20140237251 | Digital Signature System - A message signing system including a processor operative to receive a seed S | 08-21-2014 |
Uri Kaluzhny, Beit Shemesh IL
Patent application number | Description | Published |
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20150089223 | PROTECTING MEMORY INTERFACE - An apparatus includes an interface and logic circuitry. The interface is configured to communicate over a communication link. The logic circuitry is configured to convert between a first stream of plaintext bits and a second stream of ciphered bits that are exchanged over the communication link, by applying a cascade of a stream ciphering operation and a mixing operation that cryptographically maps input bits to output bits. | 03-26-2015 |
20150089234 | SECURE MEMORY INTERFACE WITH CUMULATIVE AUTHENTICATION - A method includes generating a first sequence of data words for sending over an interface. A second sequence of signatures is computed and interleaved into the first sequence, so as to produce an interleaved sequence in which each given signature cumulatively signs the data words that are signed by a previous signature in the interleaved sequence and the data words located between the previous signature and the given signature. The interleaved sequence is transmitted over the interface. | 03-26-2015 |