Patent application number | Description | Published |
20090212349 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate, and a nonvolatile memory cell provided on the semiconductor substrate, the nonvolatile memory cell including a tunnel insulating film provided on a surface of the semiconductor substrate, the tunnel insulating film including semiconductor grains, the semiconductor grains included in both end portions of the tunnel insulating film having smaller grain size than the semiconductor grains included in other portions of the tunnel insulating film, a charge storage layer provided on the tunnel insulating film, an insulating film provided on the charge storage layer, and a control gate electrode provided on the insulating film. | 08-27-2009 |
20100157680 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor region, a tunnel insulating film formed on the semiconductor region, a charge-storage insulating film formed on the tunnel insulating film, a block insulating film formed on the charge-storage insulating film, and a control gate electrode formed on the block insulating film, wherein the tunnel insulating film comprises a first region which is formed on a surface of the semiconductor region and contains silicon and oxygen, a second region which contains silicon and nitrogen, a third region which is formed on a back surface of the charge-storage insulating film and contains silicon and oxygen, and an insulating region which is formed at least between the first region and the second region or between the second region and the third region, and contains silicon and nitrogen and oxygen and the second region is formed between the first region and the third region. | 06-24-2010 |
20100190317 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SILICON OXIDE FILM FORMING METHOD - A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches. | 07-29-2010 |
20100237402 | SEMICONDUCTOR MEMORY DEVICE HAVING THREE-DIMENSIONALLY ARRANGED MEMORY CELLS, AND MANUFACTURING METHOD THEREOF - A first select transistor is formed on a semiconductor substrate. Memory cell transistors are stacked on the first select transistor and connected in series. A second select transistor is formed on the memory cell transistors. The memory cell transistors include a tapered semiconductor pillar which increases in diameter from the first select transistor toward the second select transistor, a tunnel dielectric film formed on the side surface of the semiconductor pillar, a charge storage layer which is formed on the side surface of the tunnel dielectric film and which increases in charge trap density from the first select transistor side toward the second select transistor side, a block dielectric film formed on the side surface of the charge storage layer, and conductor films which are formed on the side surface of the block dielectric film and which serve as gate electrodes. | 09-23-2010 |
20110303969 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device with memory cells each composed of a vertical transistor, comprises a silicon layer formed into a columnar shape on a silicon substrate, a gate insulating film part in which a tunnel insulating film, a charge storage layer, and a block insulating film are formed to surround the sidewall surface of the silicon layer, and a stacked structure part formed to surround the sidewall surface of the gate insulating film part and in which a plurality of interlayer insulating films and a plurality of control gate electrode layers are stacked alternately. The silicon layer, gate insulating film part, and control gate electrode layer constitute the vertical transistor. The charge storage layer has a region lower in trap level than a region facing the control gate electrode layer between the vertical transistors. | 12-15-2011 |
20120034754 | SEMICONDUCTOR DEVICE MANUFACATURING METHOD AND SILICON OXIDE FILM FORMING METHOD - A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches. | 02-09-2012 |
20140308789 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device with memory cells each composed of a vertical transistor, comprises a silicon layer formed into a columnar shape on a silicon substrate, a gate insulating film part in which a tunnel insulating film, a charge storage layer, and a block insulating film are formed to surround the sidewall surface of the silicon layer, and a stacked structure part formed to surround the sidewall surface of the gate insulating film part and in which a plurality of interlayer insulating films and a plurality of control gate electrode layers are stacked alternately. The silicon layer, gate insulating film part, and control gate electrode layer constitute the vertical transistor. The charge storage layer has a region lower in trap level than a region facing the control gate electrode layer between the vertical transistors. | 10-16-2014 |
Patent application number | Description | Published |
20080250381 | PARAMETER ADJUSTMENT METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND RECORDING MEDIUM - A parameter adjustment method for a plurality of manufacturing devices to form a pattern of a semiconductor device on a substrate using the manufacturing devices includes: adjusting a parameter adjustable for a manufacturing device serving as a reference manufacturing device so as to fall within a range of a predetermined permissible variation and defining the adjusted parameter as a reference parameter of the reference manufacturing device; obtaining a first shape of a pattern of a semiconductor device to be formed on a substrate using the reference manufacturing device from a mask to form the pattern on the substrate when the reference parameter is set to the reference manufacturing device and defining the obtained first shape as a reference finished shape; defining an adjustable parameter of another to-be-adjusted manufacturing device as a to-be-adjusted parameter of the to-be-adjusted manufacturing device; obtaining a second shape of the pattern formed on the substrate using the to-be-adjusted manufacturing device from the mask when the defined to-be-adjusted parameter is set to the to-be-adjusted manufacturing device and defining the obtained second shape as a to-be-adjusted finished shape; calculating a difference amount between the reference finished shape and the to-be-adjusted finished shape; repeatedly calculating the difference amount by changing the to-be-adjusted parameter until the difference amount becomes equal to or less than a predetermined reference value; outputting as a parameter of the to-be-adjusted manufacturing device the to-be-adjusted parameter having the difference amount equal to or less than the predetermined reference value or the to-be-adjusted parameter having the difference amount which becomes equal to or less than the predetermined reference value through the repeated calculation. | 10-09-2008 |
20090220894 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes applying illumination light to a photomask, and projecting diffracted light components from the photomask via a projection optical system to form a photoresist pattern on a substrate. The photomask includes a plurality of opening patterns which are arranged on each of a plurality of parallel lines at regular second intervals in a second direction and which have regular first intervals in a first direction perpendicular to the second direction. The plurality of opening patterns arranged on the adjacent ones of the plurality of parallel lines are displaced from each other half the second interval in the second direction. Moreover, the dimensions of the plurality of opening patterns and the complex amplitude transmittance of nontransparent region in the photomask are set so that three of the diffracted light components passing through the pupil of the projection optical system have equal amplitude. | 09-03-2009 |
20100202181 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a semiconductor substrate on which memory cells are formed. Interconnects are arranged along a first direction above the semiconductor substrate, and have regular intervals along a second direction perpendicular to the first direction. Interconnect contacts connect the interconnects and the semiconductor substrate, are arranged on three or more rows. The center of each of two of the interconnect contacts which are connected to the interconnects adjacent in the second direction deviate from each other along the first direction. | 08-12-2010 |
20100304568 | PATTERN FORMING METHOD - A pattern forming method includes forming a first photoresist on an underlying region, forming a second photoresist on the first photoresist, the second photoresist having an exposure sensitivity which is different from an exposure sensitivity of the first photoresist, radiating exposure light on the first and second photoresists via a photomask including a first transmissive region and a second transmissive region which cause a phase difference of 180° between transmissive light components passing therethrough, the first transmissive region and the second transmissive region being provided in a manner to neighbor in an irradiation region, and developing the first and second photoresists which have been irradiated with the exposure light, thereby forming a structure includes a first region where the underlying region is exposed, a second region where the first photoresist is exposed and a third region where the first photoresist and the second photoresist are left. | 12-02-2010 |
20120328992 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes applying illumination light to a photomask, and projecting diffracted light components from the photomask via a projection optical system to form a photoresist pattern on a substrate. The photomask includes a plurality of opening patterns which are arranged on each of a plurality of parallel lines at regular second intervals in a second direction and which have regular first intervals in a first direction perpendicular to the second direction. The plurality of opening patterns arranged on the adjacent ones of the plurality of parallel lines are displaced from each other half the second interval in the second direction. Moreover, the dimensions of the plurality of opening patterns and the complex amplitude transmittance of nontransparent region in the photomask are set so that three of the diffracted light components passing through the pupil of the projection optical system have equal amplitude. | 12-27-2012 |
20150263026 | SEMICONDUCTOR DEVICE AND DESIGN APPARATUS FOR SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes: a substrate including silicon; and a first element provided on the substrate and extending in a thickness direction of the substrate, a center position of an end face on the substrate side of the first element and a center position of an end face on an opposite side of the substrate side of the first element being different in a direction parallel to a major surface of the substrate. | 09-17-2015 |