Patent application number | Description | Published |
20080265365 | METHOD FOR PREVENTING THE FORMATION OF ELECTRICAL SHORTS VIA CONTACT ILD VOIDS - Densely spaced gates of field effect transistors usually lead to voids in a contact interlayer dielectric. If such a void is opened by a contact via and filled with conductive material, an electrical short between neighboring contact regions of neighboring transistors may occur. By forming a recess between two neighboring contact regions, the void forms at a lower level. Thus, opening of the void by contact vias is prevented. | 10-30-2008 |
20080265419 | SEMICONDUCTOR STRUCTURE COMPRISING AN ELECTRICALLY CONDUCTIVE FEATURE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a layer of a dielectric material. A recess is provided in the layer of dielectric material. A first glue layer and a second glue layer are formed over the recess. The first glue layer comprises titanium and the second glue layer comprises tungsten nitride. The recess is filled with a material comprising tungsten. | 10-30-2008 |
20080296692 | TECHNIQUE FOR STRAIN ENGINEERING IN SILICON-BASED TRANSISTORS BY USING IMPLANTATION TECHNIQUES FOR FORMING A STRAIN-INDUCING LAYER UNDER THE CHANNEL REGION - By incorporating a semiconductor species having the same valence and a different covalent radius compared to the base semiconductor material on the basis of an ion implantation process, a strain-inducing material may be positioned locally within a transistor at an appropriate manufacturing stage, thereby substantially not contributing to overall process complexity and also not affecting the further processing of the semiconductor device. Hence, a high degree of flexibility may be provided with respect to enhancing transistor performance in a highly local manner. | 12-04-2008 |
20080299733 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE COMPRISING AN IMPLANTATION OF IONS IN A MATERIAL LAYER TO BE ETCHED - A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature having a side surface and a top surface is formed over the substrate. A material layer is formed over the substrate. The material layer covers at least the side surface of the feature. An ion implantation process is performed to create an ion-implanted portion in the material layer. An etch process adapted to remove the ion-implanted portion at a greater etch rate than other portions of the material layer is performed. | 12-04-2008 |
20090001526 | TECHNIQUE FOR FORMING AN INTERLAYER DIELECTRIC MATERIAL OF INCREASED RELIABILITY ABOVE A STRUCTURE INCLUDING CLOSELY SPACED LINES - By removing excess material of an interlayer dielectric material deposited by SACVD, the gap filling capabilities of this deposition technique may be exploited, while, on the other hand, negative effects of this material may be reduced. In other aspects, a buffer material, such as silicon dioxide, may be formed prior to depositing the interlayer dielectric material on the basis of SACVD, thereby creating enhanced uniformity during the deposition process when depositing the interlayer dielectric material on dielectric layers having different high intrinsic stress levels. Consequently, the reliability of the interlayer dielectric material may be enhanced while nevertheless maintaining the advantages provided by an SACVD deposition. | 01-01-2009 |
20090085030 | INCREASED RELIABILITY FOR A CONTACT STRUCTURE TO CONNECT AN ACTIVE REGION WITH A POLYSILICON LINE - By forming a direct contact structure connecting, for instance, a polysilicon line with an active region on the basis of an increased amount of metal silicide by removing the sidewall spacers prior to the silicidation process, a significantly increased etch selectivity may be achieved during the contact etch stop layer opening. Hence, undue etching of the highly doped silicon material of the active region would be suppressed. Additionally or alternatively, an appropriately designed test structure is disclosed, which may enable the detection of electrical characteristics of contact structures formed in accordance with a specified manufacturing sequence and on the basis of specific design criteria. | 04-02-2009 |
20090108336 | METHOD FOR ADJUSTING THE HEIGHT OF A GATE ELECTRODE IN A SEMICONDUCTOR DEVICE - By providing an implantation blocking material on the gate electrode structures of advanced semiconductor devices during high energy implantation processes, the required shielding effect with respect to the channel regions of the transistors may be accomplished. In a later manufacturing stage, the implantation blocking portion may be removed to reduce the gate electrode height to a desired level in order to enhance the process conditions during the deposition of an interlayer dielectric material, thereby significantly reducing the risk of creating irregularities, such as voids, in the interlayer dielectric material, even in densely packed device regions. | 04-30-2009 |
20090108462 | DUAL INTEGRATION SCHEME FOR LOW RESISTANCE METAL LAYERS - By forming a metal line extending through the entire interlayer dielectric material in resistance sensitive metallization layers, enhanced uniformity of these metallization layers may be obtained. The patterning of respective via openings may be accomplished on the basis of a recess formed in a cap layer, which additionally acts as an efficient etch stop layer during the patterning of the trenches, which extend through the entire interlayer dielectric material. Consequently, for a given design width of metal lines in resistance sensitive metallization layers, a maximum cross-sectional area may be obtained for the metal line with a high degree of process uniformity irrespective of a variation of the via density. | 04-30-2009 |
20090140348 | METHOD AND A SEMICONDUCTOR DEVICE COMPRISING A PROTECTION LAYER FOR REDUCING STRESS RELAXATION IN A DUAL STRESS LINER APPROACH - By providing a protection layer for suppressing stress relaxation in a tensile-stressed dielectric material during a dual stress liner approach, performance of N-channel transistors may be increased, while nevertheless maintaining a high degree of compatibility with conventional dual stress liner approaches. | 06-04-2009 |
20090140431 | HYBRID CONTACT STRUCTURE WITH LOW ASPECT RATIO CONTACTS IN A SEMICONDUCTOR DEVICE - By forming the first metallization layer of a semiconductor device as a dual damascene structure, the contact elements may be formed on the basis of a significantly reduced aspect ratio, thereby enhancing process robustness and also improving electrical performance of the contact structure. | 06-04-2009 |
20090194789 | METHOD OF CREATING A STRAINED CHANNEL REGION IN A TRANSISTOR BY DEEP IMPLANTATION OF STRAIN-INDUCING SPECIES BELOW THE CHANNEL REGION - By incorporating a carbon species below the channel region of a P-channel transistor prior to the formation of the gate electrode structure, an efficient strain-inducing mechanism may provided, thereby enhancing performance of P-channel transistors. The position and size of the strain-inducing region may be determined on the basis of an implantation mask and respective implantation parameters, thereby providing a high degree of compatibility with conventional techniques, since the strain-inducing region may be incorporated at an early manufacturing stage, directly to respective “large area” contact elements. | 08-06-2009 |
20090194825 | SELF-ALIGNED CONTACT STRUCTURE IN A SEMICONDUCTOR DEVICE - By forming an isolation structure that extends above the height level defined by the semiconductor material of an active region, respective recesses may be defined in combination with gate electrode structures of the completion of basic transistor structures. These recesses may be subsequently filled with an appropriate contact material, thereby forming large area contacts in a self-aligned manner without requiring deposition and patterning of an interlayer dielectric material. Thereafter, the first metallization layer may be formed, for instance, on the basis of well-established techniques wherein the metal lines may connect directly to respective “large area” contact elements. | 08-06-2009 |
20090194845 | SEMICONDUCTOR DEVICE COMPRISING A CAPACITOR IN THE METALLIZATION SYSTEM AND A METHOD OF FORMING THE CAPACITOR - By forming metal capacitors in the metallization structures of semiconductor devices, complex manufacturing sequences in the device level may be avoided. The process of manufacturing the metal capacitors may be performed on the basis of well-established patterning regimes of modern metallization systems by using appropriately selected etch stop materials, which may enable a high degree of compatibility for forming via openings in a metallization layer while providing a capacitor dielectric of a desired high dielectric constant in the capacitor. | 08-06-2009 |
20090221123 | METHOD FOR INCREASING PENETRATION DEPTH OF DRAIN AND SOURCE IMPLANTATION SPECIES FOR A GIVEN GATE HEIGHT - The thickness of drain and source areas may be reduced by a cavity etch used for refilling the cavities with an appropriate semiconductor material, wherein, prior to the epitaxial growth, an implantation process may be performed so as to allow the formation of deep drain and source areas without contributing to unwanted channel doping for a given critical gate height. In other cases, the effective ion blocking length of the gate electrode structure may be enhanced by performing a tilted implantation step for incorporating deep drain and source regions. | 09-03-2009 |
20090243049 | DOUBLE DEPOSITION OF A STRESS-INDUCING LAYER IN AN INTERLAYER DIELECTRIC WITH INTERMEDIATE STRESS RELAXATION IN A SEMICONDUCTOR DEVICE - Enhanced efficiency of a stress relaxation implantation process may be achieved by depositing a first layer of reduced thickness and relaxing the same at certain device regions, thereby obtaining an enhanced amount of substantially relaxed dielectric material in close proximity to the transistor under consideration, wherein a desired high amount of stressed dielectric material may be obtained above other transistors by performing a further deposition process. Hence, the negative effect of the highly stressed dielectric material for specific transistors, for instance in densely packed device regions, may be significantly reduced by depositing the highly stressed dielectric material in two steps with an intermediate relaxation implantation process. | 10-01-2009 |
20090243116 | REDUCING PATTERNING VARIABILITY OF TRENCHES IN METALLIZATION LAYER STACKS WITH A LOW-K MATERIAL BY REDUCING CONTAMINATION OF TRENCH DIELECTRICS - By forming a protection layer prior to the application of the planarization layer during a dual damascene strategy for first patterning vias and then trenches, enhanced etch fidelity may be accomplished. In other aspects disclosed herein, via openings and trenches may be patterned in separate steps, which may be accomplished by different etch behaviors of respective dielectric materials and/or the provision of an appropriate etch stop layer, while filling the via opening and the trench with a barrier material and a highly conductive metal may be achieved in a common fill sequence. Hence, the via opening may be formed on the basis of a reduced aspect ratio, while nevertheless providing a highly efficient overall process sequence. | 10-01-2009 |
20090273035 | METHOD FOR SELECTIVELY REMOVING A SPACER IN A DUAL STRESS LINER APPROACH - By integrating a spacer removal process into the sequence for patterning a first stress-inducing material during a dual stress liner approach, the sidewall spacer structure for one type of transistor may be maintained, without requiring additional lithography steps. | 11-05-2009 |
20090294809 | REDUCTION OF METAL SILICIDE DIFFUSION IN A SEMICONDUCTOR DEVICE BY PROTECTING SIDEWALLS OF AN ACTIVE REGION - By protecting sidewall portions of active semiconductor regions during a silicidation process, the probability of creating nickel silicide pipes may be reduced. Consequently, yield losses caused by the shorting of PN junctions in sophisticated semiconductor devices may be reduced. | 12-03-2009 |
20090294868 | DRIVE CURRENT ADJUSTMENT FOR TRANSISTORS FORMED IN THE SAME ACTIVE REGION BY LOCALLY INDUCING DIFFERENT LATERAL STRAIN LEVELS IN THE ACTIVE REGION - The drive current capability of a pull-down transistor and a pass transistor formed in a common active region may be adjusted on the basis of a strain-inducing mechanism, such as a stressed dielectric material and a stress memorization technique, thereby providing a simplified overall geometric configuration of the active region. Hence, static RAM cells may be formed on the basis of a minimum channel length with a simplified configuration of the active region, thereby avoiding significant yield losses as may be observed in sophisticated devices in which a pronounced variation of the transistor width may be used to adjust the ratio of the drive current capabilities for the pull-down transistor and the pass transistor. | 12-03-2009 |
20090294898 | MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH SELF-ALIGNED AIR GAPS BETWEEN CLOSELY SPACED METAL LINES - Air gaps may be provided in a self-aligned manner with sub-lithography resolution between closely spaced metal lines of sophisticated metallization systems of semiconductor devices by recessing the dielectric material in the vicinity of the metal lines and forming respective sidewall spacer elements. Thereafter, the spacer elements may be used as an etch mask so as to define the lateral dimension of a gap on the basis of the corresponding air gaps, which may then be obtained by depositing a further dielectric material. | 12-03-2009 |
20090298279 | METHOD FOR REDUCING METAL IRREGULARITIES IN ADVANCED METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES - In a manufacturing sequence for forming metallization levels of semiconductor devices, out-gassing of volatile components after an etch process may be initiated immediately after the etch process, thereby reducing the probability of creating contaminants in other substrates and transport carriers during transport activities. Consequently, the defect rate of deposition-related irregularities in the metallization level may be reduced. | 12-03-2009 |
20090321850 | Threshold adjustment for MOS devices by adapting a spacer width prior to implantation - Different threshold voltages of transistors of the same conductivity type in a complex integrated circuit may be adjusted on the basis of different Miller capacitances, which may be accomplished by appropriately adapting a spacer width and/or performing a tilted extension implantation. Thus, efficient process strategies may be available to controllably adjust the Miller capacitance, thereby providing enhanced transistor performance of low threshold transistors while not unduly contributing to process complexity compared to conventional approaches in which threshold voltage values may be adjusted on the basis of complex halo and well doping regimes. | 12-31-2009 |
20100025782 | TECHNIQUE FOR REDUCING SILICIDE NON-UNIFORMITIES IN POLYSILICON GATE ELECTRODES BY AN INTERMEDIATE DIFFUSION BLOCKING LAYER - Threshold variability in advanced transistor elements, as well as increased leakage currents, may be reduced by incorporating a barrier material in a polysilicon gate electrode. The barrier material results in a well-controllable and well-defined metal silicide in the polysilicon gate electrode during the silicidation sequence and during the further processing by significantly reducing the diffusion of a metal species, such as nickel, into the vicinity of the gate dielectric material. | 02-04-2010 |
20100052181 | USING A CAP LAYER IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES AS A CMP AND ETCH STOP LAYER - During the manufacture of advanced metallization systems, a dielectric cap layer formed on a sensitive dielectric material may be partially maintained during a CMP process for removing excess metal, thereby avoiding the necessity for depositing a dedicated etch stop material, as may be required in conventional approaches when substantially completely consuming the dielectric cap material during the CMP process. Hence, reduced process complexity and/or enhanced flexibility may be accomplished in combination with increased integrity of the low-k dielectric material. | 03-04-2010 |
20100055902 | REDUCING CRITICAL DIMENSIONS OF VIAS AND CONTACTS ABOVE THE DEVICE LEVEL OF SEMICONDUCTOR DEVICES - Contact elements may be formed on the basis of a mask layer having openings, the width of which may be reduced by etching or deposition, thereby extending the process margins for a given lithography technique. Consequently, yield losses caused by short circuits in the contact level of sophisticated semiconductor devices may be reduced. | 03-04-2010 |
20100055903 | ENHANCING STRUCTURAL INTEGRITY OF LOW-K DIELECTRICS IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES BY USING A CRACK SUPPRESSING MATERIAL LAYER - During the formation of metallization layers of sophisticated semiconductor devices, the damaging of sensitive dielectric materials, such as ULK materials, may be significantly reduced during a CMP process by applying a compressive stress level. This may be accomplished, in some illustrative embodiments, by forming a compressively stressed cap layer on the ULK material, thereby suppressing the propagation of micro cracks into the ULK material. | 03-04-2010 |
20100078653 | TRANSISTOR HAVING A HIGH-K METAL GATE STACK AND A COMPRESSIVELY STRESSED CHANNEL - In a manufacturing flow for adapting the band gap of the semiconductor material with respect to the work function of a metal-containing gate electrode material, a strain-inducing material may be deposited to provide an additional strain component in the channel region. For instance, a layer stack with silicon/carbon, silicon and silicon/germanium may be used for providing the desired threshold voltage for a metal gate while also providing compressive strain in the channel region. | 04-01-2010 |
20100078823 | CONTACTS AND VIAS OF A SEMICONDUCTOR DEVICE FORMED BY A HARD MASK AND DOUBLE EXPOSURE - A contact element may be formed on the basis of a hard mask, which may be patterned on the basis of a first resist mask and on the basis of a second resist mask, to define an appropriate intersection area which may represent the final design dimensions of the contact element. Consequently, each of the resist masks may be formed on the basis of a photolithography process with less restrictive constraints, since at least one of the lateral dimensions may be selected as a non-critical dimension in each of the two resist masks. | 04-01-2010 |
20100133621 | RESTRICTED STRESS REGIONS FORMED IN THE CONTACT LEVEL OF A SEMICONDUCTOR DEVICE - In sophisticated semiconductor devices, an efficient stress decoupling may be accomplished between neighboring transistor elements of a densely packed device region by providing a gap or a stress decoupling region between the corresponding transistors. For example, a gap may be formed in the stress-inducing material so as to reduce the mutual interaction of the stress-inducing material on the closely spaced transistor elements. In some illustrative aspects, the stress-inducing material may be provided as an island for each individual transistor element. | 06-03-2010 |
20100133628 | HIGH-K GATE ELECTRODE STRUCTURE FORMED AFTER TRANSISTOR FABRICATION BY USING A SPACER - During a replacement gate approach, the inverse tapering of the opening obtained after removal of the polysilicon material may be reduced by depositing a spacer layer and forming corresponding spacer elements on inner sidewalls of the opening. Consequently, the metal-containing gate electrode material and the high-k dielectric material may be deposited with enhanced reliability. | 06-03-2010 |
20100133699 | MICROSTRUCTURE DEVICE INCLUDING A METALLIZATION STRUCTURE WITH AIR GAPS FORMED COMMONLY WITH VIAS - Air gaps may be formed in a metallization layer of a microstructure device on the basis of a patterning sequence in which respective via openings are also formed. Thereafter, the via openings and the air gaps may be closed by a deposition process without significantly affecting the interior of the corresponding openings. Thereafter, the further processing may be continued by forming respective trenches while maintaining integrity of the covered air gaps. Thus, the relative permittivity of the interlayer dielectric material may be efficiently reduced without adding additional process complexity. | 06-03-2010 |
20100164121 | METALLIZATION SYSTEM OF A SEMICONDUCTOR DEVICE COMPRISING EXTRA-TAPERED TRANSITION VIAS - In a metallization system of a semiconductor device, a transition via may be provided with an increased degree of tapering by modifying a corresponding etch sequence. For example, the resist mask for forming the via opening may be eroded once or several times in order to increase the lateral size of the corresponding mask opening. Due to the pronounced degree of tapering, enhanced deposition conditions may be accomplished during the subsequent electrochemical deposition process for commonly filling the via opening and a wide trench connected thereto. | 07-01-2010 |
20100190309 | METHOD FOR ADJUSTING THE HEIGHT OF A GATE ELECTRODE IN A SEMICONDUCTOR DEVICE - By providing an implantation blocking material on the gate electrode structures of advanced semiconductor devices during high energy implantation processes, the required shielding effect with respect to the channel regions of the transistors may be accomplished. In a later manufacturing stage, the implantation blocking portion may be removed to reduce the gate electrode height to a desired level in order to enhance the process conditions during the deposition of an interlayer dielectric material, thereby significantly reducing the risk of creating irregularities, such as voids, in the interlayer dielectric material, even in densely packed device regions. | 07-29-2010 |
20100193963 | VOID SEALING IN A DIELECTRIC MATERIAL OF A CONTACT LEVEL OF A SEMICONDUCTOR DEVICE COMPRISING CLOSELY SPACED TRANSISTORS - In sophisticated semiconductor devices, a contact structure may be formed on the basis of a void positioned between closely spaced transistor elements wherein disadvantageous metal migration along the void may be suppressed by sealing the voids after etching a contact opening and prior to filling in the contact metal. Consequently, significant yield losses may be avoided in well-established dual stress liner approaches while, at the same time, superior device performance may be achieved. | 08-05-2010 |
20100197133 | METHOD OF FORMING A METALLIZATION SYSTEM OF A SEMICONDUCTOR DEVICE BY USING A HARD MASK FOR DEFINING THE VIA SIZE - In a “via first/trench last” approach for forming metal lines and vias in a metallization system of a semiconductor device, a combination of two hard masks may be used, wherein the desired lateral size of the via openings may be defined on the basis of spacer elements, thereby resulting in significantly less demanding lithography conditions compared to conventional approaches. | 08-05-2010 |
20100219527 | METALLIZATION SYSTEM OF A SEMICONDUCTOR DEVICE INCLUDING METAL PILLARS HAVING A REDUCED DIAMETER AT THE BOTTOM - In a metallization system of a complex semiconductor device, metal pillars, such as copper pillars, may be formed in a nail-like configuration in order to reduce the maximum mechanical stress acting on the metallization system while providing a required contact surface for connecting to the package substrate. The nail-like configuration may be obtained on the basis of appropriately configured resist masks. | 09-02-2010 |
20100248463 | ENHANCING ADHESION OF INTERLAYER DIELECTRIC MATERIALS OF SEMICONDUCTOR DEVICES BY SUPPRESSING SILICIDE FORMATION AT THE SUBSTRATE EDGE - Adhesion of dielectric layer stacks to be formed after completing the basic configuration of transistor elements may be increased by avoiding the formation of a metal silicide in the edge region of the substrate. For this purpose, a dielectric protection layer may be selectively formed in the edge region prior to a corresponding pre-clean process or immediately prior to deposition of the refractory metal. Hence, non-reacted metal may be efficiently removed from the edge region without creating a non-desired metal silicide. Hence, the further processing may be continued on the basis of enhanced process conditions for forming interlayer dielectric materials. | 09-30-2010 |
20100301486 | HIGH-ASPECT RATIO CONTACT ELEMENT WITH SUPERIOR SHAPE IN A SEMICONDUCTOR DEVICE FOR IMPROVING LINER DEPOSITION - Contact elements of sophisticated semiconductor devices may be formed by lithographical patterning, providing a spacer element for defining the final critical width in combination with increasing a width of the contact opening prior to depositing the spacer material. The width may be increased, for instance by ion sputtering, thereby resulting in superior process conditions during the deposition of a contact metal. As a result, the probability of generating contact failures for contact elements having critical dimensions of approximately 50 nm and less may be significantly reduced. | 12-02-2010 |
20100327367 | CONTACT OPTIMIZATION FOR ENHANCING STRESS TRANSFER IN CLOSELY SPACED TRANSISTORS - By appropriately designing the geometric configuration of a contact level of a sophisticated semiconductor device, the tensile stress level of contact elements in N-channel transistors may be increased, while the tensile strain component of contact elements caused in the P-channel transistor may be reduced. | 12-30-2010 |
20110049640 | SUPERIOR FILL CONDITIONS IN A REPLACEMENT GATE APPROACH BY USING A TENSILE STRESSED OVERLAYER - In a replacement gate approach for forming high-k metal gate electrodes in semiconductor devices, a tapered configuration of the gate openings may be accomplished by using a tensile stressed dielectric material provided laterally adjacent to the gate electrode structure. Consequently, superior deposition conditions may be achieved while the tensile stress component may be efficiently used for the strain engineering in one type of transistor. Furthermore, an additional compressively stressed dielectric material may be applied after providing the replacement gate electrode structures. | 03-03-2011 |
20110049713 | DUAL CONTACT METALLIZATION INCLUDING ELECTROLESS PLATING IN A SEMICONDUCTOR DEVICE - Contact elements of sophisticated semiconductor devices may be formed for gate electrode structures and for drain and source regions in separate process sequences in order to apply electroless plating techniques without causing undue overfill of one type of contact opening. Consequently, superior process uniformity in combination with a reduced overall contact resistance may be accomplished. In some illustrative embodiments, cobalt may be used as a contact metal without any additional conductive barrier materials. | 03-03-2011 |
20110073959 | STRESS ENGINEERING IN A CONTACT LEVEL OF SEMICONDUCTOR DEVICES BY STRESSED CONDUCTIVE LAYERS AND AN ISOLATION SPACER - In sophisticated semiconductor devices, strain-inducing materials having a reduced dielectric strength or having certain conductivity, such as metal nitride and the like, may be used in the contact level in order to enhance performance of circuit elements, such as field effect transistors. For this purpose, a strain-inducing material may be efficiently encapsulated on the basis of a dielectric layer stack that may be patterned prior to forming the actual interlayer dielectric material in order to mask sidewall surface areas on the basis of spacer elements. | 03-31-2011 |
20110076028 | SEMICONDUCTOR DEVICE COMPRISING A BURIED WAVEGUIDE FOR DEVICE INTERNAL OPTICAL COMMUNICATION - In an integrated circuit device, such as a microprocessor, a device internal optical communication system is provided in order to enhance signal transfer capabilities while relaxing overall thermal conditions. Furthermore, the device internal optical data or signal transfer capabilities may result in superior operating speed and a high degree of design flexibility. The optical communication system may be applied as a chip internal system in single chip systems or as an inter-chip optical system in three-dimensional chip configurations provided in a single package. | 03-31-2011 |
20110101426 | SEMICONDUCTOR DEVICE COMPRISING REPLACEMENT GATE ELECTRODE STRUCTURES WITH AN ENHANCED DIFFUSION BARRIER - In sophisticated semiconductor devices, the integrity of the device level may be enhanced after applying a replacement gate approach by providing an additional diffusion barrier layer, such as a silicon nitride layer, thereby obtaining a similar degree of diffusion blocking capabilities as in semiconductor devices without performing a replacement gate approach. | 05-05-2011 |
20110101460 | SEMICONDUCTOR FUSES IN A SEMICONDUCTOR DEVICE COMPRISING METAL GATES - In a replacement gate approach, the semiconductor material of the gate electrode structures may be efficiently removed during a wet chemical etch process, while this material may be substantially preserved in electronic fuses. Consequently, well-established semiconductor-based electronic fuses may be used instead of requiring sophisticated metal-based fuse structures. The etch selectivity of the semiconductor material may be modified on the basis of ion implantation or electron bombardment. | 05-05-2011 |
20110104867 | FABRICATING VIAS OF DIFFERENT SIZE OF A SEMICONDUCTOR DEVICE BY SPLITTING THE VIA PATTERNING PROCESS - When forming a complex metallization system in which vias of different lateral size have to be provided, a split patterning sequence may be applied. For this purpose, a lithography process may be specifically designed for the critical via openings and a subsequent second patterning process may be applied for forming the vias of increased lateral dimensions, while the critical vias are masked. In this manner, superior process conditions may be established for each of the patterning sequences. | 05-05-2011 |
20110186929 | SOI SEMICONDUCTOR DEVICE COMPRISING SUBSTRATE DIODES HAVING A TOPOGRAPHY TOLERANT CONTACT STRUCTURE - In an SOI semiconductor device, substrate diodes may be formed on the basis of a superior design of the contact level and the metallization layer, thereby avoiding the presence of metal lines connecting to both diode electrodes in the critical substrate diode area. To this end, contact trenches may be provided so as to locally connect one type of diode electrodes within the contact level. Consequently, additional process steps for planarizing the surface topography upon forming the contact level may be avoided. | 08-04-2011 |
20110189825 | SOI SEMICONDUCTOR DEVICE WITH REDUCED TOPOGRAPHY ABOVE A SUBSTRATE WINDOW AREA - In sophisticated SOI devices, circuit elements, such as substrate diodes, may be formed in the crystalline substrate material on the basis of a substrate window, wherein the pronounced surface topography may be compensated for or at least reduced by performing additional planarization processes, such as the deposition of a planarization material, and a subsequent etch process when forming the contact level of the semiconductor device. | 08-04-2011 |
20110201135 | Method of Reducing Contamination by Providing a Removable Polymer Protection Film During Microstructure Processing - By providing a protective layer in an intermediate manufacturing stage, an increased surface protection with respect to particle contamination and surface corrosion may be achieved. In some illustrative embodiments, the protective layer may be used during an electrical test procedure, in which respective contact portions are contacted through the protective layer, thereby significantly reducing particle contamination during a respective measurement process. | 08-18-2011 |
20110210447 | CONTACT ELEMENTS OF SEMICONDUCTOR DEVICES COMPRISING A CONTINUOUS TRANSITION TO METAL LINES OF A METALLIZATION LAYER - In sophisticated semiconductor devices, contact elements in the contact level may be formed by patterning the contact openings and filling the contact openings with the metal of the first metallization layer in a common deposition sequence. To this end, in some illustrative embodiments, a sacrificial fill material may be provided in contact openings prior to depositing the dielectric material of the first metallization layer. | 09-01-2011 |
20110223732 | THRESHOLD ADJUSTMENT FOR MOS DEVICES BY ADAPTING A SPACER WIDTH PRIOR TO IMPLANTATION - Different threshold voltages of transistors of the same conductivity type in a complex integrated circuit may be adjusted on the basis of different Miller capacitances, which may be accomplished by appropriately adapting a spacer width and/or performing a tilted extension implantation. Thus, efficient process strategies may be available to controllably adjust the Miller capacitance, thereby providing enhanced transistor performance of low threshold transistors while not unduly contributing to process complexity compared to conventional approaches in which threshold voltage values may be adjusted on the basis of complex halo and well doping regimes. | 09-15-2011 |
20110241167 | Semiconductor Device Comprising a Capacitor in the Metallization System Formed by a Hard Mask Patterning Regime - Capacitors may be formed in the metallization system of semiconductor devices without requiring a modification of the hard mask patterning process for forming vias and trenches in the dielectric material of the metallization layer under consideration. To this end, a capacitor opening is formed prior to actually forming the hard mask for patterning the trench and via openings, wherein the hard mask material may thus preserve integrity of the capacitor opening and may remain as a portion of the electrode material after filling in the conductive material for the metal lines, vias and the capacitor electrode. | 10-06-2011 |
20110266638 | Semiconductor Device Comprising Contact Elements and Metal Silicide Regions Formed in a Common Process Sequence - A metal silicide in sophisticated semiconductor devices may be provided in a late manufacturing stage on the basis of contact openings, wherein the deposition of the contact material, such as tungsten, may be efficiently combined with the silicidation process. In this case, the thermally activated deposition process may initiate the formation of a metal silicide in highly doped semiconductor regions. | 11-03-2011 |
20110291292 | Selective Shrinkage of Contact Elements in a Semiconductor Device - In sophisticated semiconductor devices, the contact elements connecting to active semiconductor regions having formed thereabove closely spaced gate electrode structures may be provided on the basis of a liner material so as to reduce the lateral width of the contact opening, while, on the other hand, non-critical contact elements may be formed on the basis of non-reduced lateral dimensions. To this end, at least a first portion of the critical contact element is formed and provided with a liner material prior to forming the non-critical contact element. | 12-01-2011 |
20120001263 | Replacement Gate Approach for High-K Metal Gate Stacks Based on a Non-Conformal Interlayer Dielectric - In replacement gate approaches for forming sophisticated high-k metal gate electrode structures in a late manufacturing stage, the exposing of the placeholder material may be accomplished on the basis of a substantially uniform interlayer dielectric material, for instance in the form of a silicon nitride material, which may have a similar removal rate compared to the dielectric cap material, the spacer elements and the like of the gate electrode structures. Consequently, a pronounced degree of recessing of the interlayer dielectric material may be avoided, thereby reducing the risk of forming metal residues upon removing any excess material of the gate metal. | 01-05-2012 |
20120001323 | Semiconductor Device Including Ultra Low-K (ULK) Metallization Stacks with Reduced Chip-Package Interaction - In complex semiconductor devices, sophisticated ULK materials may be used in metal line layers in combination with a via layer of enhanced mechanical stability by increasing the amount of dielectric material of superior mechanical strength. Due to the superior mechanical stability of the via layers, reflow processes for directly connecting the semiconductor die and a package substrate may be performed on the basis of a lead-free material system without unduly increasing yield losses. | 01-05-2012 |
20120021581 | SELF-ALIGNED CONTACT STRUCTURE LATERALLY ENCLOSED BY AN ISOLATION STRUCTURE OF A SEMICONDUCTOR DEVICE - By forming an isolation structure that extends above the height level defined by the semiconductor material of an active region, respective recesses may be defined in combination with gate electrode structures of the completion of basic transistor structures. These recesses may be subsequently filled with an appropriate contact material, thereby forming large area contacts in a self-aligned manner without requiring deposition and patterning of an interlayer dielectric material. Thereafter, the first metallization layer may be formed, for instance, on the basis of well-established techniques wherein the metal lines may connect directly to respective “large area” contact elements. | 01-26-2012 |
20120025318 | Reduced Topography in Isolation Regions of a Semiconductor Device by Applying a Deposition/Etch Sequence Prior to Forming the Interlayer Dielectric - Contact failures in sophisticated semiconductor devices may be reduced by relaxing the pronounced surface topography in isolation regions prior to depositing the interlayer dielectric material system. To this end, a deposition/etch sequence may be applied in which a fill material may be removed from the active region, while the recesses in the isolation regions may at least be partially filled. | 02-02-2012 |
20120091535 | Method and Semiconductor Device Comprising a Protection Layer for Reducing Stress Relaxation in a Dual Stress Liner Approach - By providing a protection layer for suppressing stress relaxation in a tensile-stressed dielectric material during a dual stress liner approach, performance of N-channel transistors may be increased, while nevertheless maintaining a high degree of compatibility with conventional dual stress liner approaches. | 04-19-2012 |
20120115326 | Method of Forming Metal Silicide Regions - The method described herein involves the formation of metal silicide regions. The method may involve forming a layer of refractory metal on a structure comprising silicon, forming a layer of silicon on the layer of refractory metal and, after forming the layer of silicon, performing at least one heat treatment process to form a metal silicide region in the structure. | 05-10-2012 |
20120153405 | Semiconductor Device Comprising a Contact Structure with Reduced Parasitic Capacitance - In sophisticated semiconductor devices, at least a portion of the interlayer dielectric material of the contact level may be provided in the form of a low-k dielectric material which may, in some illustrative embodiments, be accomplished on the basis of a replacement gate approach. Hence, superior electrical performance, for instance with respect to the parasitic capacitance, may be accomplished. | 06-21-2012 |
20120161210 | Embedding Metal Silicide Contact Regions Reliably Into Highly Doped Drain and Source Regions by a Stop Implantation - When forming metal silicide regions, such as nickel silicide regions, in sophisticated transistors requiring a shallow drain and source dopant profile, superior controllability may be achieved by incorporating a silicide stop layer. To this end, in some illustrative embodiments, a carbon species may be incorporated on the basis of an implantation process in order to significantly modify the metal diffusion during the silicidation process. Consequently, an increased thickness of the metal silicide may be provided, while not unduly increasing the probability of creating contact failures. | 06-28-2012 |
20120161324 | Semiconductor Device Comprising Contact Elements with Silicided Sidewall Regions - When forming a metal silicide within contact openings in complex semiconductor devices, a silicidation of sidewall surface areas of the contact openings may be initiated by forming a silicon layer therein, thereby reducing unwanted diffusion of the refractory metal species into the laterally adjacent dielectric material. In this manner, superior reliability and electrical performance of the resulting contact elements may be achieved on the basis of a late silicide process. | 06-28-2012 |
20120181692 | HYBRID CONTACT STRUCTURE WITH LOW ASPECT RATIO CONTACTS IN A SEMICONDUCTOR DEVICE - In sophisticated semiconductor devices, superior contact resistivity may be accomplished for a given contact configuration by providing hybrid contact elements, at least a portion of which may be comprised of a highly conductive material, such as copper. To this end, a well-established contact material, such as tungsten, may be used as buffer material in order to preserve integrity of sensitive device areas upon depositing the highly conductive metal. | 07-19-2012 |
20120217582 | SOI Semiconductor Device Comprising a Substrate Diode with Reduced Metal Silicide Leakage - When forming substrate diodes in SOI devices, superior diode characteristics may be preserved by providing an additional spacer element in the substrate opening and/or by using a superior contact patterning regime on the basis of a sacrificial fill material. In both cases, integrity of a metal silicide in the substrate diode may be preserved, thereby avoiding undue deviations from the desired ideal diode characteristics. In some illustrative embodiments, the superior diode characteristics may be achieved without requiring any additional lithography step. | 08-30-2012 |
20120223388 | SUPERIOR FILL CONDITIONS IN A REPLACEMENT GATE APPROACH BY USING A TENSILE STRESSED OVERLAYER - In a replacement gate approach for forming high-k metal gate electrodes in semiconductor devices, a tapered configuration of the gate openings may be accomplished by using a tensile stressed dielectric material provided laterally adjacent to the gate electrode structure. Consequently, superior deposition conditions may be achieved while the tensile stress component may be efficiently used for the strain engineering in one type of transistor. Furthermore, an additional compressively stressed dielectric material may be applied after providing the replacement gate electrode structures. | 09-06-2012 |
20120256240 | METHOD FOR INCREASING PENETRATION DEPTH OF DRAIN AND SOURCE IMPLANTATION SPECIES FOR A GIVEN GATE HEIGHT - The thickness of drain and source areas may be reduced by a cavity etch used for refilling the cavities with an appropriate semiconductor material, wherein, prior to the epitaxial growth, an implantation process may be performed so as to allow the formation of deep drain and source areas without contributing to unwanted channel doping for a given critical gate height. In other cases, the effective ion blocking length of the gate electrode structure may be enhanced by performing a tilted implantation step for incorporating deep drain and source regions. | 10-11-2012 |
20120313176 | Buried Sublevel Metallizations for Improved Transistor Density - Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein electrical interconnects between circuit elements based on a buried sublevel metallization may provide improved transistor density. One illustrative method disclosed herein includes forming a contact dielectric layer above first and second transistor elements of a semiconductor device, and after forming the contact dielectric layer, forming a buried conductive element below an upper surface of the contact dielectric layer, the conductive element providing an electrical connection between the first and second transistor elements. | 12-13-2012 |
20130072016 | METHODS OF FORMING CONDUCTIVE CONTACTS WITH REDUCED DIMENSIONS - Disclosed herein are various methods of forming conductive contacts with reduced dimensions and various semiconductor devices incorporating such conductive contacts. In one example, one method disclosed herein includes forming a layer of insulating material above a semiconducting substrate, wherein the layer of material has a first thickness, forming a plurality of contact openings in the layer of material having the first thickness and forming an organic material in at least a portion of each of the contact openings. This illustrative method further includes the steps of, after forming the organic material, performing an etching process to reduce the first thickness of the layer of insulating material to a second thickness that is less than the first thickness, after performing the etching process, removing the organic material from the contact openings and forming a conductive contact in each of the contact openings. | 03-21-2013 |
20130084703 | RESTRICTED STRESS REGIONS FORMED IN THE CONTACT LEVEL OF A SEMICONDUCTOR DEVICE - In sophisticated semiconductor devices, an efficient stress decoupling may be accomplished between neighboring transistor elements of a densely packed device region by providing a gap or a stress decoupling region between the corresponding transistors. For example, a gap may be formed in the stress-inducing material so as to reduce the mutual interaction of the stress-inducing material on the closely spaced transistor elements. In some illustrative aspects, the stress-inducing material may be provided as an island for each individual transistor element. | 04-04-2013 |
20130130498 | REDUCING PATTERNING VARIABILITY OF TRENCHES IN METALLIZATION LAYER STACKS WITH A LOW-K MATERIAL BY REDUCING CONTAMINATION OF TRENCH DIELECTRICS - Generally, the present disclosure is related to various techniques that may be used for forming metallization systems in a highly efficient manner by filling via openings and trenches in a common fill process, while reducing negative effects during the patterning of the via opening and the trenches. One illustrative method disclosed herein includes, among other things, forming a via opening in a first dielectric material of a metallization layer of a semiconductor device. Moreover, a second dielectric material is formed above the first dielectric material, wherein the second dielectric material fills the via opening. Furthermore, the method also includes forming a trench in the second dielectric material so as to connect to the via opening, and filling the trench and the via opening with a metal in a common fill process. | 05-23-2013 |
20130140645 | SEMICONDUCTOR FUSES IN A SEMICONDUCTOR DEVICE COMPRISING METAL GATES - In a replacement gate approach, the semiconductor material of the gate electrode structures may be efficiently removed during a wet chemical etch process, while this material may be substantially preserved in electronic fuses. Consequently, well-established semiconductor-based electronic fuses may be used instead of requiring sophisticated metal-based fuse structures. The etch selectivity of the semiconductor material may be modified on the basis of ion implantation or electron bombardment. | 06-06-2013 |
20130178057 | Methods of Forming Conductive Structures Using a Dual Metal Hard Mask Technique - Disclosed herein are various methods of forming conductive structures, such as conductive lines and vias, using a dual metal hard mask integration technique. In one example, the method includes forming a first layer of insulating material, forming a first patterned metal hard mask layer above the first layer of insulating material, forming a second patterned metal hard mask layer above the first patterned metal hard mask layer, performing at least one etching process through both of the second patterned metal hard mask layer and the first patterned metal hard mask layer to define a trench in the first layer of insulating material and forming a conductive structure in the trench. | 07-11-2013 |
20130189822 | METHODS OF FABRICATING INTEGRATED CIRCUITS WITH THE ELIMINATION OF VOIDS IN INTERLAYER DIELECTICS - Methods are provided for fabricating integrated circuits that include forming first and second spaced apart gate structures overlying a semiconductor substrate, and forming first and second spaced apart source/drain regions in the semiconductor substrate between the gate structures. A first layer of insulating material is deposited overlying the gate structures and the source/drain regions by a process of atomic layer deposition, and a second layer of insulating material is deposited overlying the first layer by a process of chemical vapor deposition. First and second openings are etched through the second layer and the first layer to expose portions of the source/drain regions. The first and second openings are filled with conductive material to form first and second spaced apart contacts, electrically isolated from each other, in electrical contact with the first and second source/drain regions. | 07-25-2013 |
20130252409 | HIGH-K GATE ELECTRODE STRUCTURE FORMED AFTER TRANSISTOR FABRICATION BY USING A SPACER - During a replacement gate approach, the inverse tapering of the opening obtained after removal of the polysilicon material may be reduced by depositing a spacer layer and forming corresponding spacer elements on inner sidewalls of the opening. Consequently, the metal-containing gate electrode material and the high-k dielectric material may be deposited with enhanced reliability. | 09-26-2013 |
20140264641 | SEMICONDUCTOR DEVICE COMPRISING CONTACT STRUCTURES WITH PROTECTION LAYERS FORMED ON SIDEWALLS OF CONTACT ETCH STOP LAYERS - When forming semiconductor devices with contact plugs comprising protection layers formed on sidewalls of etch stop layers to reduce the risk of shorts, the protection layers may be formed by performing a sputter process to remove material from a contact region and redeposit the removed material on the sidewalls of the etch stop layers. | 09-18-2014 |