Patent application number | Description | Published |
20110263069 | METHODS TO AVOID LASER ANNEAL BOUNDARY EFFECT WITHIN BSI CMOS IMAGE SENSOR ARRAY - Methods are disclosed herein for determining the laser beam size and the scan pattern of laser annealing when fabricating backside illumination (BSI) CMOS image sensors to keep dark-mode stripe patterns corresponding to laser scan boundary effects from occurring within the sensor array regions of the image sensors. Each CMOS image sensor has a sensor array region and a periphery circuit. The methods determines a size of the laser beam from a length of the sensor array region and a length of the periphery circuit so that the laser beam covers an integer number of the sensor array region for at least one alignment of the laser beam on the array of BSI image sensors. The methods further determines a scan pattern so that the boundary of the laser beam does not overlap the sensor array regions during the laser annealing, but only overlaps the periphery circuits. | 10-27-2011 |
20130040446 | Backside Surface Treatment of Semiconductor Chips - A method includes performing a grinding to a backside of a semiconductor substrate, wherein a remaining portion of the semiconductor substrate has a back surface. A treatment is then performed on the back surface using a method selected from the group consisting essentially of a dry treatment and a plasma treatment. Process gases that are used in the treatment include oxygen (O | 02-14-2013 |
20150155326 | SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF - A semiconductor arrangement and method of formation are provided herein. A semiconductor arrangement includes an active area on a substrate, where the active area is at least one of a p-type region or an n-type region. The substrate includes a well, where the well is a p-well when the active area is a p-type region, and the well is an n-well when the active area is an n-type region. The well includes a photodiode. The active area is connected to a voltage supply having a voltage level, such as ground. The active area on the substrate increases a distance between the photodiode and the active area, which reduces junction leakage as compared to a semiconductor arrangement where the active area is formed at least partially within the substrate. | 06-04-2015 |
20150255400 | Method for Forming Alignment Marks and Structure of Same - A method of fabrication of alignment marks for a non-STI CMOS image sensor is introduced. In some embodiments, zero layer alignment marks and active are alignment marks may be simultaneously formed on a wafer. A substrate of the wafer may be patterned to form one or more recesses in the substrate. The recesses may be filled with a dielectric material using, for example, a field oxidation method and/or suitable deposition methods. Structures formed by the above process may correspond to elements of the zero layer alignment marks and/or to elements the active area alignment marks. | 09-10-2015 |
Patent application number | Description | Published |
20130070519 | READ ARCHITECTURE FOR MRAM - A read architecture for reading random access memory (RAM) cells includes a multi-level sense amplifier, the multi-level sense amplifier including a plurality of sense amplifiers, each sense amplifier having a respective sense threshold and a respective sense output, and a storage module coupled to the multi-level sense amplifier for storing the sense outputs of the multi-level sense amplifier. The storage module stores a first set of sense outputs corresponding to a first read of an RAM cell and stores a second set of sense outputs corresponding to a second read of the RAM cell. The architecture also includes a decision module for comparing the first and second set of sense outputs and determining a data state of the RAM cell based on the comparison. | 03-21-2013 |
20130188418 | MAGNETORESISTIVE RANDOM ACCESS MEMORY - A magnetoresistive random access memory (MRAM) cell includes a magnetic tunnel junction (MTJ), a top electrode disposed over the MTJ, a bottom electrode disposed below the MTJ, and an induction line disposed above or below the MTJ. The induction line is configured to induce a magnetic field at the MTJ. | 07-25-2013 |
20130242676 | FAST-SWITCHING WORD LINE DRIVER - A word line driver of a semiconductor memory includes logic circuitry for coupling a word line to a first node set at a first voltage level when the word line driver is in a first state or to a second node set at a second voltage level when the word line driver is in a second state. A capacitor is configured to be charged to a third voltage level that is greater than the first and second voltage levels. First and second transistors are configured to selectively couple the word line to the capacitor and to a third node set at a fourth voltage level when the word line driver is in a third state. The fourth voltage level is greater than the first voltage level and less than the second voltage level. | 09-19-2013 |
20130265820 | ADJUSTING REFERENCE RESISTANCES IN DETERMINING MRAM RESISTANCE STATES - Magneto-resistive memory bit cells in an array have high or low resistance states storing logic values. During read operations, a bias source is coupled to an addressed memory word, coupling a parameter related to cell resistance to a sense amplifier at each bit position. The sense amplifiers determine whether the parameter value is greater or less than a reference value between the high and low resistance states. The reference value is derived by averaging or splitting a difference of resistances of reference cells at high and/or low resistance states. Bias current is conducted over address lines with varying resistance, due to different distances between the sense amplifiers and addressed memory words, which is canceled by inserting into the comparison circuit a resistance from a dummy addressing array, equal to the resistance of the conductor addressing the selected word line and bit position. | 10-10-2013 |
20130272059 | DIFFERENTIAL MRAM STRUCTURE WITH RELATIVELY REVERSED MAGNETIC TUNNEL JUNCTION ELEMENTS ENABLING WRITING USING SAME POLARITY CURRENT - A magnetoresistive memory has first and second magnetic tunnel junction (MTJ) elements operated differentially, each with a pinned magnetic layer and a free magnetic layer that can have field alignments that are parallel or anti-parallel, producing differential high and low resistance states representing a bit cell value. Writing a high resistance state to an element requires an opposite write current polarity through the pinned and free layers, and differential operation requires that the two MTJ elements be written to different resistance states. One aspect is to arrange or connect the layers in normal and reverse order relative to a current bias source, thereby achieving opposite write current polarities relative to the layers using the same current polarity relative to the current bias source. The differentially operated MTJ elements can supplement or replace single MTJ elements in a nonvolatile memory bit cell array. | 10-17-2013 |
20140071750 | ADAPTIVE WORD-LINE BOOST DRIVER - A word line driver circuit includes a first transistor having its gate coupled to a first node configured to receive a word line select signal. A second transistor has its gate coupled to the first node and a drain coupled to a drain of the first transistor at a second node that is coupled to a word line. A word line assist control circuit is coupled to the first node, to the word line, and to a gate of a third transistor. The word line assist control circuit is configured to turn on or turn off the third transistor to adjust a voltage of the word line. | 03-13-2014 |
20140157088 | MRAM Smart Bit Write Algorithm with Error Correction Parity Bits - Some aspects of the present disclosure relate a method. The method attempts to write an expected multi-bit word to a memory location in memory. After writing of the multi-bit word has been attempted, an actual multi-bit word is read from the memory location. The actual multi-bit word is then compared with the expected multi-bit word to identify a number of erroneous bits and a number of correct bits stored in the memory location. The number of erroneous bits is re-written to the memory location without attempting to re-write the correct bits to the memory location. | 06-05-2014 |
20140211537 | RESISTANCE-BASED RANDOM ACCESS MEMORY - A resistance-based random access memory circuit includes a first data line, a second data line, a plurality of memory cells, a first driving unit, and a second driving unit. The memory cells are arranged one following another in parallel with the first and second data lines. Each of the memory cells are coupled between the first data line and the second data line. The first driving unit is coupled with first ends of the first and second data lines. The first driving unit is configured to electrically couple one of the first data line and the second data line to a first voltage node. The second driving unit is coupled with second ends of the first and second data lines. The second driving unit is configured to electrically couple the other one of the first data line and the second data line to a second voltage node. | 07-31-2014 |
20140211549 | ACCOMMODATING BALANCE OF BIT LINE AND SOURCE LINE RESISTANCES IN MAGNETORESISTIVE RANDOM ACCESS MEMORY - A memory has magnetic tunnel junction elements with different resistances in different logic states, for bit positions in memory words accessed by a word line signal coupling each bit cell in the addressed word between a bit line and source line for that bit position. The bit lines and source lines are longer and shorter at different word line locations, causing a resistance body effect. A clamping transistor couples the bit line to a sensing circuit when reading, applying a current through the bit cell and producing a read voltage compared by the sensing circuit to a reference such as a comparable voltage from a reference bit cell circuit having a similar structure. A drive control varies an input to the switching transistor as a function of the word line location, e.g., by word line address, to offset the different bit and source line resistances. | 07-31-2014 |
20140269030 | METHOD AND APPARATUS FOR MRAM SENSE REFERENCE TRIMMING - A trimming process for setting a reference current used in operating an MRAM module comprising an operational MRAM cell coupled to a bit line, multiple reference MRAM cells coupled to a reference bit line, and a sense amplifier coupled to the bit line and the reference bit line is disclosed in some embodiments. The process includes applying a bit line reference voltage to the reference bit line to provide a reference cell current formed by a sum of respective currents through the plurality of reference MRAM cells. The reference cell current is detected. A determination is made as to whether the detected reference cell current differs from a target reference cell current. The bit line reference voltage is varied, or a sensing ratio of the sense amplifier is varied, if it is determined that the detected reference cell current differs from the target reference cell current. | 09-18-2014 |
20150144860 | RESISTIVE MEMORY ARRAY AND FABRICATING METHOD THEREOF - The present disclosure provides a method of fabricating a resistive memory array. In one embodiment, a method of fabricating a resistive memory array includes forming a plurality of insulators and a conductive structure on a first substrate, performing a resistor-forming process to transform the insulators into a plurality of resistors, polishing the conductive structure to expose a plurality of contact points respectively electrically connected to the resistors, providing a second substrate having a plurality of transistors and a plurality of interconnect pads, bonding respectively the interconnect pads and the contact points, and removing the first substrate from the resistors and the conductive structure. | 05-28-2015 |
20150180210 | SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF - A semiconductor arrangement and a method of forming the same are described. A semiconductor arrangement includes a first layer including a first optical transceiver and a second layer including a second optical transceiver. A first serializer/deserializer (SerDes) is connected to the first optical transceiver and a second SerDes is connected to the second optical transceiver. The SerDes converts parallel data input into serial data output including a clock signal that the first transceiver transmits to the second transceiver. The semiconductor arrangement has a lower area penalty than traditional intra-layer communication arrangements that do not use optics for alignment, and mitigates alignment issues associated with conventional techniques. | 06-25-2015 |
20150234403 | LOW-DROPOUT REGULATOR - A low-dropout (LDO) regulator is provided. The LDO regulator comprises a first circuit operating as a closed loop control system. The first circuit is configured to control a voltage at a first node such that the voltage at the first node is substantially equal to a specified regulator output voltage. The LDO regulator comprises a second circuit operating as an open loop control system. The second circuit is configured to increase the voltage at the first node when a current flowing through a load changes from a first current to a second current. The first current is substantially equal to 0 amperes. | 08-20-2015 |
20150269997 | Resistive Memory Array - A circuit that includes a current source module, a current sink module and a memory bank is disclosed. Each of the current source module, the current sink module and the memory bank is connected to the first bit/source line and the second bit/source line. The memory bank is bounded by the current source module and the current sink module. When the current source module and the current sink module receive a triggering pulse from the first bit/source line and a select signal with a first state, the current source module is activated to generate an operating current to the first bit/source line that transmits through a conducted memory cell of the memory bank and the current sink module is activated to drain the operating current from the second bit/source line. | 09-24-2015 |
20150294696 | STABILIZING CIRCUIT - A stabilizing circuit is provided that is connected to a biased voltage. The stabilizing circuit is configured to inhibit a change in voltage of the biased voltage caused by a first change in voltage of one or more nodes that are connected to the biased voltage through a first parasitic capacitance. In some embodiments, the stabilizing circuit induces a voltage on the biased voltage through a second parasitic capacitance that changes from a first voltage level to a second voltage level during the first change in voltage such that a total change in parasitic voltage that is induced at the biased voltage during the first change in voltage is close to 0 V. | 10-15-2015 |
20150355963 | MRAM SMART BIT WRITE ALGORITHM WITH ERROR CORRECTION PARITY BITS - Some embodiments relate to a system that includes write circuitry, read circuitry, and comparison circuitry. The write circuitry is configured to attempt to write an expected multi-bit word to a memory location in a memory device. The read circuitry is configured to read an actual multi-bit word from the memory location. The comparison circuitry is configured to compare the actual multi-bit word read from the memory location with the expected multi-bit word which was previously written to the memory location to distinguish between a number of erroneous bits in the actual multi-bit word and a number of correct bits in the actual multi-bit word. The write circuitry is further configured to re-write the number of erroneous bits to the memory location without attempting to re-write the number of correct bits to the memory location. | 12-10-2015 |