Patent application number | Description | Published |
20150054078 | METHODS OF FORMING GATE STRUCTURES FOR FINFET DEVICES AND THE RESULTING SMEICONDUCTOR PRODUCTS - One method disclosed herein includes forming a stack of material layers to form gate structures, performing a first etching process to define an opening through the stack of materials that defines an end surface of the gate structures, forming a gate separation structure in the opening and performing a second etching process to define side surfaces of the gate structures. A device disclosed herein includes first and second active regions that include at least one fin, first and second gate structures, wherein each of the gate structures have end surfaces, and a gate separation structure positioned between the gate structures, wherein opposing surfaces of the gate separation structure abut the end surfaces of the gate structures, and wherein an upper surface of the gate separation structure is positioned above an upper surface of the at least one fin. | 02-26-2015 |
20150129970 | METHODS AND STRUCTURES FOR ELIMINATING OR REDUCING LINE END EPI MATERIAL GROWTH ON GATE STRUCTURES - One method disclosed herein includes, among other things, forming a line-end protection layer in an opening on an entirety of each opposing, spaced-apart first and second end face surfaces of first and second spaced-apart gate electrode structures, respectively, and forming a sidewall spacer adjacent opposing sidewall surfaces of each of the gate electrode structures but not adjacent the opposing first and second end face surfaces having the line-end protection layer positioned thereon. | 05-14-2015 |
20150270262 | GATE STRUCTURES WITH PROTECTED END SURFACES TO ELIMINATE OR REDUCE UNWANTED EPI MATERIAL GROWTH - One method disclosed herein includes, among other things, forming a line-end protection layer in an opening on an entirety of each opposing, spaced-apart first and second end face surfaces of first and second spaced-apart gate electrode structures, respectively, and forming a sidewall spacer adjacent opposing sidewall surfaces of each of the gate electrode structures but not adjacent the opposing first and second end face surfaces having the line-end protection layer positioned thereon. | 09-24-2015 |
20150340323 | SELF-FORMING EMBEDDED DIFFUSION BARRIERS - Interconnect structures containing metal oxide embedded diffusion barriers and methods of forming the same. Interconnect structures may include an M | 11-26-2015 |
20150372145 | HIGH DENSITY VERTICAL NANOWIRE STACK FOR FIELD EFFECT TRANSISTOR - An alternating stack of layers of a first epitaxial semiconductor material and a second epitaxial semiconductor material is formed on a substrate. A fin stack is formed by patterning the alternating stack into a shape of a fin having a parallel pair of vertical sidewalls. After formation of a disposable gate structure and an optional gate spacer, raised active regions can be formed on end portions of the fin stack. A planarization dielectric layer is formed, and the disposable gate structure is subsequently removed to form a gate cavity. A crystallographic etch is performed on the first epitaxial semiconductor material to form vertically separated pairs of an upright triangular semiconductor nanowire and an inverted triangular semiconductor nanowire. Portions of the epitaxial disposable material are subsequently removed. After an optional anneal, the gate cavity is filled with a gate dielectric and a gate electrode to form a field effect transistor. | 12-24-2015 |
20160071928 | METHODS OF FORMING GATE STRUCTURES FOR FINFET DEVICES AND THE RESULTING SEMICONDUCTOR PRODUCTS - A transistor device includes first and second spaced-apart active regions positioned in a semiconductor substrate, each of the respective first and second spaced-apart active regions having at least one fin. First and second spaced-apart gate structures are positioned above the respective first and second active regions, each of the first and second gate structures having end surfaces. A gate separation structure is positioned between the first and second spaced-apart gate structures, wherein first and second opposing surfaces of the gate separation structure abut an entirety of the respective end surfaces of the first and second spaced-apart gate structures, and wherein an upper surface of the gate separation structure is positioned at a greater height level above the semiconductor substrate than an upper surface of the at least one fin of each of the respective first and second spaced-apart active regions. | 03-10-2016 |
20160116435 | NANOCHANNEL ELECTRODE DEVICES - A nanoscale electrode device can be fabricated by forming a pair of semiconductor fins laterally spaced from each other by a uniform distance and formed on a substrate. The pair of semiconductor fins can function as a pair of electrodes that can be biased to detect the leakage current through a nanoscale string to pass therebetween. A nanochannel having a uniform separation distance is formed between the pair of semiconductor fins. The nanochannel may be defined by a gap between a pair of raised active regions formed on the pair of semiconductor fins, or between proximal sidewalls of the pair of semiconductor fins. An opening is formed through the portion of the substrate underlying the region of the nanochannel to enable passing of a nanoscale string. | 04-28-2016 |
20160133573 | MICROSTRUCTURE OF METAL INTERCONNECT LAYER - A metal interconnect layer, a method of forming the metal interconnect layer, a method of forming a device that includes the metal interconnect layer are described. The method of forming the metal interconnect layer includes forming an opening in a dielectric layer, forming a metal layer in the opening and over a top surface of the dielectric layer. The method also includes disposing a metal passivation layer on an overburden portion of the metal layer formed over the top surface of the dielectric layer. The metal passivation layer includes a metal selected from a group of: cobalt (Co), ruthenium (Ru), tantalum (Ta), titanium (Ti), nickel (Ni), tungsten (W), any alloy thereof, nitrides of Co, Ru, Ti, Ni, or W, and any combination thereof. The method also includes performing an anneal at a temperature exceeding 100 degrees centigrade and below 300 degrees centigrade. | 05-12-2016 |