Patent application number | Description | Published |
20110249177 | METHOD, APPARATUS AND SYSTEM FOR IMPLEMENTING MOSAIC TV SERVICE - A method, an apparatus and a system for implementing a mosaic TV service are provided in embodiments of the present invention. The application relates to the field of TV technologies, and solves the problem in the prior art that the operability about each small video previewing image is poor. At a front end, a video stream of a TV program of each channel is zoomed out in proportion, to obtain a small video stream corresponding to the TV program of each channel. All the small video streams are multiplexed into at least one mosaic TV service stream to be transmitted to a terminal. The at least one mosaic TV service stream delivered from the front end is obtained at the terminal, from which at least one small video stream is demultiplexed. An image of the small video stream is adjusted to a preset size, and the adjusted small video stream image is displayed. | 10-13-2011 |
20130113994 | Method and Apparatus for Determining Type of Video Signal to be Output - A method for determining a type of video signal to be output is provided. The method includes: respectively extracting detection signals in video signals in different video output interface modes; respectively converting the extracted detection signal into a direct current voltage signal; and respectively comparing the direct current voltage signal with a voltage threshold, and determining, according to a comparison result, a type of video signal to be output. An embodiment further provides an apparatus for determining a type of video signal to be output. The embodiments of the present invention, by respectively extracting a detection signal included in a video signal in each video output interface mode, and comparing a voltage of the detection signal with a voltage threshold, determine whether a corresponding DAC port in the each video output interface mode is connected to a load terminal, and thereby determine a video signal to be output. | 05-09-2013 |
Patent application number | Description | Published |
20140061793 | SUBLITHOGRAPHIC WIDTH FINFET EMPLOYING SOLID PHASE EPITAXY - A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different semiconductor material. Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer with uniform thickness. Remaining portions of the epitaxial semiconductor material layer are single crystalline semiconductor fins and thickness of these fins are sublithographic. After removal of the dielectric mandrel structure, the single crystalline semiconductor fins can be employed to form a semiconductor device. | 03-06-2014 |
20140264279 | FACETED SEMICONDUCTOR NANOWIRE - Selective epitaxy of a semiconductor material is performed on a semiconductor fin to form a semiconductor nanowire. Surfaces of the semiconductor nanowire include facets that are non-horizontal and non-vertical. A gate electrode can be formed over the semiconductor nanowire such that the faceted surfaces can be employed as channel surfaces. The epitaxially deposited portions of the faceted semiconductor nanowire can apply stress to the channels. Further, an additional semiconductor material may be added to form an outer shell of the faceted semiconductor nanowire prior to forming a gate electrode thereupon. The faceted surfaces of the semiconductor nanowire provide well-defined charge carrier transport properties, which can be advantageously employed to provide a semiconductor device with well-controlled device characteristics. | 09-18-2014 |
20140273360 | FACETED SEMICONDUCTOR NANOWIRE - Selective epitaxy of a semiconductor material is performed on a semiconductor fin to form a semiconductor nanowire. Surfaces of the semiconductor nanowire include facets that are non-horizontal and non-vertical. A gate electrode can be formed over the semiconductor nanowire such that the faceted surfaces can be employed as channel surfaces. The epitaxially deposited portions of the faceted semiconductor nanowire can apply stress to the channels. Further, an additional semiconductor material may be added to form an outer shell of the faceted semiconductor nanowire prior to forming a gate electrode thereupon. The faceted surfaces of the semiconductor nanowire provide well-defined charge carrier transport properties, which can be advantageously employed to provide a semiconductor device with well-controlled device characteristics. | 09-18-2014 |
20140273425 | CYCLICAL PHYSICAL VAPOR DEPOSITION OF DIELECTRIC LAYERS - Embodiments include methods of forming dielectric layers. According to an exemplary embodiment, a dielectric layer may be formed by determining a desired thickness of the dielectric layer, forming a first dielectric sub-layer having a thickness less than the desired thickness by depositing a first metal layer above a substrate and oxidizing the first metal layer, and forming n (where n is greater than 1) additional dielectric sub-layers having a thickness less than the desired thickness above the first dielectric sub-layer by the same method of the first dielectric sub-layer so that a combined thickness of all dielectric sub-layers is approximately equal to the desired thickness. | 09-18-2014 |
20140299988 | SELF-FORMING EMBEDDED DIFFUSION BARRIERS - Interconnect structures containing metal oxide embedded diffusion barriers and methods of forming the same. Interconnect structures may include an M | 10-09-2014 |
20140327054 | Raised Source/Drain and Gate Portion with Dielectric Spacer or Air Gap Spacer - A semiconductor structure and method of manufacturing the same are provided. The semiconductor device includes epitaxial raised source/drain (RSD) regions formed on the surface of a semiconductor substrate through selective epitaxial growth. In one embodiment, the faceted side portions of the RSD regions are utilized to form cavity regions which may be filled with a dielectric material to form dielectric spacer regions. Spacers may be formed over the dielectric spacer regions. In another embodiment, the faceted side portions may be selectively grown to form air gap spacer regions in the cavity regions. A conformal spacer layer with interior and exterior surfaces may be formed in the cavity region, creating an air gap spacer defined by the interior surfaces of the conformal spacer layer. | 11-06-2014 |
20140353497 | TRANSMISSION ELECTRON MICROSCOPE SAMPLE FABRICATION - A method of preparing a transmission electron microscopy (TEM) sample from a semiconductor structure may include milling a region of the semiconductor structure with a focused ion beam and generating the transmission electron microscopy (TEM) sample. The focused ion beam providing the milling may include a rotation angle relative to the crystallographic axis of the semiconductor structure. A transmission electron microscopy image of a cross-sectional plane of the generated transmission electron microscopy (TEM) sample may be generated using a transmission electron microscope, whereby the transmission electron microscopy image of the cross-sectional plane includes an image projection-free region based on the rotation angle. | 12-04-2014 |
20150069625 | ULTRA-THIN METAL WIRES FORMED THROUGH SELECTIVE DEPOSITION - The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a pair of ultra-thin metal wires in an opening using a selective deposition process. | 03-12-2015 |
20150087120 | Raised Source/Drain and Gate Portion with Dielectric Spacer or Air Gap Spacer - A semiconductor structure and method of manufacturing the same are provided. The semiconductor device includes epitaxial raised source/drain (RSD) regions formed on the surface of a semiconductor substrate through selective epitaxial growth. In one embodiment, the faceted side portions of the RSD regions are utilized to form cavity regions which may be filled with a dielectric material to form dielectric spacer regions. Spacers may be formed over the dielectric spacer regions. In another embodiment, the faceted side portions may be selectively grown to form air gap spacer regions in the cavity regions. A conformal spacer layer with interior and exterior surfaces may be formed in the cavity region, creating an air gap spacer defined by the interior surfaces of the conformal spacer layer. | 03-26-2015 |
20150091181 | SELF-ALIGNED VIAS FORMED USING SACRIFICIAL METAL CAPS - A method including forming a sacrificial metal cap on a metal line formed in a first dielectric layer; forming a second dielectric layer on the first dielectric layer; removing the sacrificial metal cap selective to the second dielectric layer and metal line to form a cap opening; forming a dielectric cap in the cap opening and on the metal line; forming an interconnect dielectric layer over the dielectric cap and the second dielectric layer; forming an interconnect opening in the interconnect dielectric layer; removing a portion of the dielectric cap exposed by the interconnect opening selective to the interconnect dielectric layer, the second dielectric layer, and the metal line; and forming an interconnect structure in the interconnect opening, the interconnect structure comprising a contact line above a via, the via having an upper via portion with angled sidewalls and a lower via portion with substantially vertical sidewalls. | 04-02-2015 |
20150162337 | PATTERN FACTOR DEPENDENCY ALLEVIATION FOR EDRAM AND LOGIC DEVICES WITH DISPOSABLE FILL TO EASE DEEP TRENCH INTEGRATION WITH FINS - Dummy deep trenches can be formed within a logic device region in which logic devices are to be formed while deep trench capacitors are formed within a memory device region. Semiconductor fins are formed over a top surface prior to forming trenches, and disposable material is filled around said semiconductor fins. A top surface of said disposable filler material layer can be coplanar with a top surface of said semiconductor fins, which eases deep trench formation. Conductive material portions of the dummy deep trenches can be recessed to avoid electrical contact with semiconductor fins within the logic device region, while an inner electrode of each deep trench can contact a semiconductor fin within the memory device region. A dielectric material portion can be formed above each conductive material portion of a dummy deep trench. | 06-11-2015 |
20150287721 | SUBLITHOGRAPHIC WIDTH FINFET EMPLOYING SOLID PHASE EPITAXY - A dielectric mandrel structure is formed on a single crystalline semiconductor layer. An amorphous semiconductor material layer is deposited on the physically exposed surfaces of the single crystalline semiconductor layer and surfaces of the mandrel structure. Optionally, the amorphous semiconductor material layer can be implanted with at least one different semiconductor material. Solid phase epitaxy is performed on the amorphous semiconductor material layer employing the single crystalline semiconductor layer as a seed layer, thereby forming an epitaxial semiconductor material layer with uniform thickness. Remaining portions of the epitaxial semiconductor material layer are single crystalline semiconductor fins and thickness of these fins are sublithographic. After removal of the dielectric mandrel structure, the single crystalline semiconductor fins can be employed to form a semiconductor device. | 10-08-2015 |
Patent application number | Description | Published |
20150054078 | METHODS OF FORMING GATE STRUCTURES FOR FINFET DEVICES AND THE RESULTING SMEICONDUCTOR PRODUCTS - One method disclosed herein includes forming a stack of material layers to form gate structures, performing a first etching process to define an opening through the stack of materials that defines an end surface of the gate structures, forming a gate separation structure in the opening and performing a second etching process to define side surfaces of the gate structures. A device disclosed herein includes first and second active regions that include at least one fin, first and second gate structures, wherein each of the gate structures have end surfaces, and a gate separation structure positioned between the gate structures, wherein opposing surfaces of the gate separation structure abut the end surfaces of the gate structures, and wherein an upper surface of the gate separation structure is positioned above an upper surface of the at least one fin. | 02-26-2015 |
20150129970 | METHODS AND STRUCTURES FOR ELIMINATING OR REDUCING LINE END EPI MATERIAL GROWTH ON GATE STRUCTURES - One method disclosed herein includes, among other things, forming a line-end protection layer in an opening on an entirety of each opposing, spaced-apart first and second end face surfaces of first and second spaced-apart gate electrode structures, respectively, and forming a sidewall spacer adjacent opposing sidewall surfaces of each of the gate electrode structures but not adjacent the opposing first and second end face surfaces having the line-end protection layer positioned thereon. | 05-14-2015 |
20150270262 | GATE STRUCTURES WITH PROTECTED END SURFACES TO ELIMINATE OR REDUCE UNWANTED EPI MATERIAL GROWTH - One method disclosed herein includes, among other things, forming a line-end protection layer in an opening on an entirety of each opposing, spaced-apart first and second end face surfaces of first and second spaced-apart gate electrode structures, respectively, and forming a sidewall spacer adjacent opposing sidewall surfaces of each of the gate electrode structures but not adjacent the opposing first and second end face surfaces having the line-end protection layer positioned thereon. | 09-24-2015 |
20150340323 | SELF-FORMING EMBEDDED DIFFUSION BARRIERS - Interconnect structures containing metal oxide embedded diffusion barriers and methods of forming the same. Interconnect structures may include an M | 11-26-2015 |
Patent application number | Description | Published |
20090105512 | Process for producing lower olefins under negative pressure - The present invention provides a process for producing lower olefins. The technical problem mainly addressed in the present invention is to overcome the defects presented in the prior art including high reaction pressure, high reaction temperature, low yield and selectivity of lower olefins as the target products, poor stability and short life of catalyst, and limited suitable feedstocks. The present process, which is carried out under the conditions of catalytic cracking olefins and adopts as a feedstock an olefins-enriched mixture containing one or more C4 or higher olefins and optionally an organic oxygenate compound, comprises the steps of: a) letting the feedstock contact with a crystalline aluminosilicate catalyst having a SiO | 04-23-2009 |
20100056831 | ENERGY-EFFECTIVE PROCESS FOR CO-PRODUCING ETHYLENE AND DIMETHYL ETHER - The present invention discloses a process for the co-production of ethylene and dimethyl ether, comprising (i) providing a feedstock comprising ethanol and methanol, with a weight ratio of methanol to ethanol being in a range of from 1:10 to 10:1; (ii) feeding the feedstock into a reaction zone containing a solid catalyst to give an effluent, wherein a reaction temperature is in a range of from 200 to 480° C., a reaction pressure is in a range of from 0 to 2 MPa (gauge), and a weight hourly space velocity of the feedstock is in a range of from 0.1 to 10 h | 03-04-2010 |
20100063335 | PROCESS FOR PRODUCING LIGHT OLEFINS FROM METHANOL OR DIMETHYL ETHER - A process for producing light olefins from methanol and/or dimethyl ether comprising the steps of: (a) introducing a feed comprising methanol and/or dimethyl ether into a fluidized-bed reactor from its bottom, and reacting the feed in a dense phase zone and a transition zone of the fluidized-bed reactor by contacting it with a catalyst, to form an effluent I comprising unreacted feed, reaction products and entrained solid particulate catalyst; (b) introducing a terminating agent at upper portion of the transition zone and/or lower portion of a gas-solid separating zone of the fluidized-bed reactor into the effluent I, to give an effluent II, wherein the terminating agent is at least one selected from the group consisting of water, C | 03-11-2010 |
20100160671 | Processes for Producing an Oxalate by Coupling of CO - Provided are processes for producing an oxalate by coupling of CO in the presence of a nitrite, wherein two or more reaction zones in series are used, and at least a portion of the oxalate as reaction product is separated between the reaction zones, and/or the nitrite is fed stagewise. The processes described herein can effectively enhance the selectivity to the oxalate and the single-pass conversion of the feedstock. | 06-24-2010 |
20100179356 | PROCESSES FOR PRODUCING ETHYLENE GLYCOL FROM OXALATE(S) - Provided are processes for producing ethylene glycol from oxalate(s), wherein two or more reaction zones in series are used, and oxalate feedstock is fed stagewise, or hydrogen feedstock and optionally a solvent are fed stagewise. The present processes achieve higher selectivity for the product and improved stability of catalysts. | 07-15-2010 |
20110257424 | Process for Producing C1-C4 Alkyl Nitrite - A process of producing C | 10-20-2011 |
20110257425 | Process for Producing Cl-C4 Alkyl Nitrite - The present invention relates to a process for producing C | 10-20-2011 |
20110263726 | PROCESS FOR SELECTIVE OXIDATIVE DEHYDROGENATION OF A HYDROGEN-CONTAINING CO MIXED GAS - A process for selective oxidative dehydrogenation of a hydrogen-containing CO mixed gas, comprising contacting a hydrogen-containing CO mixed gas raw material with at least one catalyst entity having an increased activity gradient disposed in a reactor under at least one reaction condition chosen from a reaction temperature ranging from 100 to 300° C., a volume space velocity ranging from 100 to 10000 h | 10-27-2011 |
20110308999 | METHOD FOR SELECTIVE HYDROGENATION OF PHENYLACETYLENE IN THE PRESENCE OF STYRENE - The present invention discloses a process for the selective hydrogenation of phenylacetylene in the presence of styrene, comprising contacting a phenylacetylene and styrene-containing hydrocarbon fraction feedstock with a carbon-containing catalyst under hydrogenation reaction conditions, wherein the carbon-containing catalyst has a carbon content of from 0.02 to 8 wt % based on the weight of the catalyst. | 12-22-2011 |
20130079549 | PROCESS OF PRODUCING OXALATE BY CO GAS PHASE METHOD - A process of producing oxalate by CO gas phase method includes the following steps: a) introducing nitrite salt, water and an inorganic acid first into a reactor I to produce a NO containing effluent I; and separating the resultant effluent to obtain the effluent II of NO; b) introducing the effluent II of NO, a C | 03-28-2013 |
20130197265 | PROCESS OF PRODUCING OXALATE BY CO GAS PHASE METHOD - The present invention relates to a process of producing oxalate by CO gas phase method for chiefly solving the technical problem of the low utilization efficiency of nitrogen oxides or nitrous acid esters in the prior art. The present invention solves the problem in a better way by using the following steps including: a gas phase stream V containing NO and methanol and oxygen enter a supergravity rotating bed reactor II and are subjected to the oxidative esterification reaction to produce an effluent VI containing methyl nitrite; a methyl nitrite effluent VII obtained from separating said effluent VI together with a CO gas II enter a coupling reactor II and is contacted with a catalyst II to react to form a dimethyl oxalate effluent VIII and a gas phase effluent IX containing NO; the resultant dimethyl oxalate effluent VIII is separated to obtain a dimethyl oxalate product I; optionally, the gas phase effluent IX containing NO is returned to the step above so as to be mixed with the gas phase stream V containing NO for being recycled. Therefore, the process is applicable to the industrial production of oxalate by CO gas phase method. | 08-01-2013 |
20130331617 | METHOD FOR PRODUCING ETHYLENE GLYCOL FROM OXALATE THROUGH THE FLUIDIZED BED CATALYTIC REACTION - A process for producing ethylene glycol includes contacting an oxalate with a fluidized bed catalyst under the following conditions: a reaction temperature of from about 170 to about 270° C., a weight space velocity of oxalate of from about 0.2 to about 7 hours | 12-12-2013 |
20130331618 | METHOD FOR IMPROVING THE QUALITY OF ETHYLENE GLYCOL PRODUCTS - A method for improving the quality of ethylene glycol products, which mainly solves the technical problem of low UV-light transmittance of the ethylene glycol products present in the prior art. The method successfully solves the problem by use of the technical solution wherein the ethylene glycol raw material and hydrogen are passed through a rotating packed bed reactor loaded with solid oxide catalyst at a temperature of about 20 to about 280 ° C., a pressure of about 0.1 to about 4.0 MPa, a space velocity of about 0.2 to about 100.0 hr | 12-12-2013 |
20130338406 | METHOD FOR THE PRODUCTION OF ETHYLENE GLYCOL - The present invention relates to a method for the production of ethylene glycol using a feedstock comprising an oxalate and a catalyst containing copper and/or a copper oxide, comprising contacting the feedstock with the catalyst in a reactor under the conditions of a temperature in the range from about 170 to about 270° C., a weight hourly space velocity of the oxalate in the range from about 0.2 to about 5 h | 12-19-2013 |
Patent application number | Description | Published |
20100038297 | Poly (Vinyl Alcohol) Polymers, Uses and Preparation Thereof - There are provided poly(vinyl alcohol) polymers and copolymers containing vinyl alcohol or vinyl acetate and derivatives thereof such as poly(ethylene glycol)-grafted poly(vinyl alcohol) polymers or polyether-grafted poly(vinyl alcohol) polymers. These polymers can contain various functional groups. Such polymers can be use as polymer matrix or solid support for various chemical substrates such as organic substrates and reagents. Cross-linked poly(vinyl alcohol) polymers and copolymers are also provided. Methods for preparing such polymers as well as several of their uses are also included. | 02-18-2010 |
20110144281 | AMPHIPHILIC POLYMERS HAVING A CHOLANE CORE - The present invention relates to a polymer comprising a cholane core having at least one derivatizable group covalently bonded thereto and a hydrophilic polymer chain covalently bonded to derivatizable group(s) and a process for producing it The present invention also relates to micellar aggregate formed from the polymer of the present. | 06-16-2011 |
20110286915 | Nanocarriers for Drug Delivery - The present invention provides a nanocarrier having an interior and an exterior, the nanocarrier comprising at least one conjugate, wherein each conjugate includes a polyethylene glycol (PEG) polymer. Each conjugate also includes at least two amphiphilic compounds having both a hydrophilic face and a hydrophobic face. In addition, each conjugate includes an oligomer, wherein at least 2 of the amphiphilic compounds are covalently attached to the oligomer which is covalently attached to the PEG. The nanocarrier is such that each conjugate self-assembles in an aqueous solvent to form the nanocarrier such that a hydrophobic pocket is formed in the interior of the nanocarrier by the orientation of the hydrophobic face of each amphiphilic compound towards each other, and wherein the PEG of each conjugate self-assembles on the exterior of the nanocarrier. | 11-24-2011 |
20120322145 | THREE-DIMENSIONAL CELL ADHESION MATRIX - The present invention provides a cell adhesion matrix having poly(vinyl alcohol) chains crosslinked via carboxy phenyl boronic acid crosslinkers. The cell adhesion matrix can also include a molecular recognition element bound to the poly(vinyl alcohol) chains via a carboxy phenyl boronic acid group, as well as including cells. The present invention also provides a method for making and de-gelling the cell adhesion matrix. | 12-20-2012 |