Patent application number | Description | Published |
20090028140 | SWITCHING DEVICE, SWITCHING METHOD, AND SWITCH CONTROL PROGRAM - A switching device includes an input stage switch group | 01-29-2009 |
20090059928 | COMMUNICATION APPARATUS, COMMUNICATION SYSTEM, ABSENT PACKET DETECTING METHOD AND ABSENT PACKET DETECTING PROGRAM - Any packet loss is detected very quickly by means of only a series of sequence number in a multi-path environment where a transmitter and a receiver are connected to each other by way of a plurality of networks when no inversion of sequence arises in any of the networks. A communication apparatus includes a plurality of sequence buffers arranged at each network to accumulate packets until a sequence acknowledgement and an absence detecting section adapted to determine the occurrence of an absence of a packet when one or more packets are accumulated in all the sequence buffers. With this arrangement, the absence detecting section of the receiver monitors the packets staying in the sequence guaranteeing buffer arranged in each of the network, paying attention to the characteristic that packets are stored in the sequence buffers of all the networks when a packet loss takes place. | 03-05-2009 |
20090175281 | SWITCH DEVICE, SWITCHING METHOD AND SWITCH CONTROL PROGRAM - A switch device is composed of a switch portion | 07-09-2009 |
20100180062 | INTERNET CONNECTION SWITCH AND INTERNET CONNECTION SYSTEM | 07-15-2010 |
20110064089 | PCI EXPRESS SWITCH, PCI EXPRESS SYSTEM, AND NETWORK CONTROL METHOD - Provided are a first PCI-PCI bridge that handles Multi Root to connect to a plurality of root complexes; a second PCI-PCI bridge that connects to an endpoint; a virtual PCI Express switch that performs a switching process between the first and second PCI-PCI bridges; and a network control device that transfers data that is to be processed in the virtual PCI Express switch to an external switch through a network without passing through a PCI-PCI bridge. | 03-17-2011 |
20110145647 | TROUBLE ANALYSIS APPARATUS - A trouble analysis apparatus is provided which includes: a system topology storing portion; an error detection information receiving portion which collects error detection information; and a trouble source determination portion which, based on both the error detection information collected by the error detection information receiving portion and system topology information stored in the system topology information storing portion, determines a trouble source functional element that is presumed as a functional element which is a source of a system trouble. Links included in the system topology information have information indicating spreading directions of error operations between the functional elements when trouble occurs. When the trouble source detection portion receives the error detection information with regard to multiple error functional elements, the trouble source determination portion sequentially selects one of the multiple error functional elements. The trouble source detection portion determines whether or not directions from the selected error functional element to other error functional elements conform to the spreading directions included in the system topology information. The trouble source determination portion determines the selected error functional element as the trouble source functional element when the spreading directions are conformable. | 06-16-2011 |
20110153906 | SWITCH AND NETWORK BRIDGE APPARATUS - A network system that is part of a main system includes: a first PCI express-network bridge with a first control unit and a first PCI express adapter terminating a first PCI express bus; and a second PCI express-network bridge connected to the first PCI express-network bridge through a network. The second PCI express-network bridge includes a second control unit and a second PCI express adapter terminating a second PCI express bus, wherein the first control unit detects a destination of a packet sent from the first PCI express adapter, searches a physical address of the destination from a packet encapsulating table, and encapsulates the packet in a frame so that the frame includes the physical address, and wherein the second control unit removes the encapsulation tagged to the packet, and transfers the packet to the destination through the second PCI express bus by referring to a PCI express configuration register. | 06-23-2011 |
20110213902 | INFORMATION PROCESSING SYSTEM - An information processing system includes a plurality of processors for executing processing according to a predetermined processing request sent from a different device; a switching device for performing data transfer between the individual processors and the different device; and a storage device which is connected to the switching device and enables data transfer to and from the individual processors. At least one of the processors includes a processing request storing unit for storing processing request data sent from the different device to the processor, into the storage device by data transfer. At least another one of the processors includes a processing request reading unit for reading the processing request data stored in the storage device from the storage device by data transfer. | 09-01-2011 |
20120016949 | DISTRIBUTED PROCESSING SYSTEM, INTERFACE, STORAGE DEVICE, DISTRIBUTED PROCESSING METHOD, DISTRIBUTED PROCESSING PROGRAM - A distributed processing system which distributes a load of a request from a client without being restricted by a processing status and processing performance of transfer processing means is provided: | 01-19-2012 |
20120110233 | I/O SYSTEM, DOWNSTREAM PCI EXPRESS BRIDGE, INTERFACE SHARING METHOD, AND PROGRAM - Fault tolerance is improved, a functional limitation at the time of start-up of an I/O system is avoided, and a start-up time is shortened. A downstream PCI Express bridge sets a PCI Express device connected to the downstream PCI Express bridge itself, among a plurality of single root-compatible PCI Express devices shared by a plurality of root complexes connected to a plurality of upstream PCI Express bridges that exchange data with the downstream PC Express bridge itself through a network, controls and monitors a state of a physical link with the PCI Express device connected to the downstream PCI Express bridge itself, and performs monitoring and notification of an error of the PCI Express device connected to the downstream PCI Express bridge itself. | 05-03-2012 |
20120263182 | Communication Apparatus, Communication System, Absent Packet Detecting Method and Absent Packet Detecting Program - Any packet loss is detected very quickly by means of only a series of sequence number in a multi-path environment where a transmitter and a receiver are connected to each other by way of a plurality of networks when no inversion of sequence arises in any of the networks. A communication apparatus includes a plurality of sequence buffers arranged at each network to accumulate packets until a sequence acknowledgement and an absence detecting section adapted to determine the occurrence of an absence of a packet when one or more packets are accumulated in all the sequence buffers. With this arrangement, the absence detecting section of the receiver monitors the packets staying in the sequence guaranteeing buffer arranged in each of the network, paying attention to the characteristic that packets are stored in the sequence buffers of all the networks when a packet loss takes place. | 10-18-2012 |
20120290764 | SHARED SYSTEM OF I/O EQUIPMENT, SHARED SYSTEM OF INFORMATION PROCESSING APPARATUS, AND METHOD USED THERETO - An I/O equipment sharing system includes CPUs, a plurality of route complexes coupled to the CPUs, upstream PCI Express-bridges coupled to the route complexes, downstream PCI Express-bridges coupled to the upstream PCI Express-bridges through a network, and I/O equipment coupled to the downstream PCI Express-bridges. In the above configuration, the I/O equipment are shared between the CPUs using the identifiers of the network (for example, Ethernet VLAN IDs), the identifiers are set so that they do not overlap between the respective CPUs and necessary I/O equipment is set to a set identifier. Further, an identifier is set to a plurality of the same I/O equipment required by the respective CPUs. | 11-15-2012 |
20140059250 | NETWORK SYSTEM - A network system of the present invention includes a computer and a device connected via a network, and a system management device. The computer and the device include, respectively, bridges that encapsulate transmission/reception data transmitted and received to and from each other and transmit and receive the data to and from each other via the network. Each of the bridges includes a control data transmitting means for generating control data for controlling the state of the system based on control auxiliary data issued from the computer or the device and used for controlling the state of the system, and transmitting the control data to the system management device via the network. The system management device includes a system controlling means for controlling the state of the system in accordance with the control data received thereby. | 02-27-2014 |
20140281053 | I/O DEVICE CONTROL SYSTEM AND METHOD FOR CONTROLLING I/O DEVICE - A plurality of bridge units which connect a computer, a data movement source I/O device, and a data movement destination I/O device to a network, a memory unit which relays movement of data between the data movement source I/O device and the data movement destination I/O device outside the computer, and an I/O data movement control unit which causes the data movement source I/O device to write data to the memory unit and causes the data movement destination I/O device to read the data from the memory unit are included. | 09-18-2014 |
20140379994 | DATA TRANSFER DEVICE, DATA TRANSFER METHOD, AND COMPUTER DEVICE - A local-memory side data transfer unit increments the number of addresses, reads out data from a local memory, and stores the data into a cache memory of a remote-memory side data transfer unit. For preventing data mismatching with the local memory from being stored into the cache memory, a cache clearing operation is executed in units of an elapse of a round trip time period for data transfer between the local memory and the remote memory. Alternatively, the cache clearing operation is executed upon receipt of a signal notifying data transfer of data stored at a specified address. | 12-25-2014 |